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  /external/llvm/test/Transforms/SimplifyCFG/
common-dest-folding.ll 46 %tmp6 = icmp eq i32 %tmp5, 0
47 br i1 %tmp6, label %bb9, label %bb7
  /external/llvm/test/CodeGen/PowerPC/
vec_splat.ll 16 %tmp6 = insertelement %f4 %tmp4, float %X, i32 3 ; <%f4> [#uses=1]
18 %R = fadd %f4 %q, %tmp6 ; <%f4> [#uses=1]
27 %tmp6 = insertelement %i4 %tmp4, i32 %X, i32 3 ; <%i4> [#uses=1]
29 %R = add %i4 %q, %tmp6 ; <%i4> [#uses=1]
vec_shuffle.ll 20 %tmp6 = extractelement <16 x i8> %tmp.upgrd.1, i32 9 ; <i8> [#uses=1]
36 %tmp22 = insertelement <16 x i8> %tmp21, i8 %tmp6, i32 4 ; <<16 x i8>> [#uses=1]
62 %tmp6 = extractelement <16 x i8> %tmp.upgrd.5, i32 9 ; <i8> [#uses=1]
78 %tmp22 = insertelement <16 x i8> %tmp21, i8 %tmp6, i32 4 ; <<16 x i8>> [#uses=1]
117 %tmp6 = extractelement <16 x i8> %tmp, i32 10 ; <i8> [#uses=1]
133 %tmp22 = insertelement <16 x i8> %tmp21, i8 %tmp6, i32 4 ; <<16 x i8>> [#uses=1]
157 %tmp6 = extractelement <8 x i16> %tmp, i32 6 ; <i16> [#uses=1]
165 %tmp14 = insertelement <8 x i16> %tmp13, i16 %tmp6, i32 4 ; <<8 x i16>> [#uses=1]
181 %tmp6 = insertelement <4 x i32> undef, i32 %tmp.upgrd.14, i32 0 ; <<4 x i32>> [#uses=1]
182 %tmp7 = insertelement <4 x i32> %tmp6, i32 %tmp3, i32 1 ; <<4 x i32>> [#uses=1
    [all...]
2007-09-08-unaligned.ll 44 %tmp6 = getelementptr [8 x i8], [8 x i8]* @.str, i32 0, i32 0 ; <i8*> [#uses=1]
45 %tmp7 = call i32 (i8*, ...) @printf( i8* %tmp6, double %tmp23, double %tmp5 ) ; <i32> [#uses=0]
bswap-load-store.ll 35 %tmp6 = call i16 @llvm.bswap.i16( i16 %tmp ) ; <i16> [#uses=1]
36 ret i16 %tmp6
vec_misaligned.ll 29 %tmp6 = getelementptr %struct.S2203, %struct.S2203* @s, i32 0, i32 0 ; <%struct.u16qi*> [#uses=1]
31 %tmp8 = getelementptr %struct.u16qi, %struct.u16qi* %tmp6, i32 0, i32 0 ; <<16 x i8>*> [#uses=1]
  /external/llvm/test/CodeGen/X86/
2010-04-06-SSEDomainFixCrash.ll 29 %tmp6.i = extractelement <4 x float> %1, i32 1 ; <float> [#uses=1]
34 %.tmp6.0.i.i = phi float [ %tmp2.i, %bb.nph.i.i ], [ %5, %bb1.i.i ] ; <float> [#uses=1]
35 %.tmp5.0.i.i = phi float [ %tmp6.i, %bb.nph.i.i ], [ %4, %bb1.i.i ] ; <float> [#uses=1]
39 %5 = fadd float %.tmp6.0.i.i, undef ; <float> [#uses=2]
2008-01-16-InvalidDAGCombineXform.ll 13 %tmp6 = load %struct.node_t*, %struct.node_t** %cur_node, align 4 ; <%struct.node_t*> [#uses=1]
14 %tmp7 = getelementptr %struct.node_t, %struct.node_t* %tmp6, i32 0, i32 3 ; <double***> [#uses=1]
2011-05-27-CrossClassCoalescing.ll 23 %tmp6.i12 = load i32, i32* undef, align 4
27 %shr.i14 = lshr i32 %tmp6.i12, 8
  /external/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/
split-gep-and-gvn-addrspace-addressing-modes.ll 18 %tmp6 = add i32 %y, 1
19 %tmp7 = sext i32 %tmp6 to i64
51 %tmp6 = add i32 %y, 255
52 %tmp7 = sext i32 %tmp6 to i64
81 %tmp6 = add i32 %y, 255
82 %tmp8 = getelementptr inbounds [4096 x [4 x float]], [4096 x [4 x float]] addrspace(3)* @lds_array, i32 0, i32 %x, i32 %tmp6
89 %tmp18 = getelementptr inbounds [4096 x [4 x float]], [4096 x [4 x float]] addrspace(3)* @lds_array, i32 0, i32 %tmp12, i32 %tmp6
  /external/libvpx/libvpx/vpx_dsp/mips/
intrapred16_dspr2.c 16 int32_t tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7, tmp8; local
25 "lb %[tmp6], 5(%[left]) \n\t"
42 "replv.qb %[tmp6], %[tmp6] \n\t"
84 "sw %[tmp6], (%[dst]) \n\t"
85 "sw %[tmp6], 4(%[dst]) \n\t"
86 "sw %[tmp6], 8(%[dst]) \n\t"
87 "sw %[tmp6], 12(%[dst]) \n\t"
152 [tmp6] "=&r" (tmp6), [tmp8] "=&r" (tmp8)
    [all...]
  /external/llvm/test/CodeGen/ARM/
vlddup.ll 104 %tmp6 = getelementptr i16, i16* %A, i32 2
105 store i16* %tmp6, i16** %ptr
140 %tmp6 = shufflevector <8 x i8> %tmp5, <8 x i8> undef, <8 x i32> zeroinitializer
142 %tmp8 = add <8 x i8> %tmp7, %tmp6
158 %tmp6 = shufflevector <4 x i16> %tmp5, <4 x i16> undef, <4 x i32> zeroinitializer
160 %tmp8 = add <4 x i16> %tmp7, %tmp6
182 %tmp6 = shufflevector <4 x i16> %tmp5, <4 x i16> undef, <4 x i32> zeroinitializer
186 %tmp10 = add <4 x i16> %tmp6, %tmp8
204 %tmp6 = shufflevector <2 x i32> %tmp5, <2 x i32> undef, <2 x i32> zeroinitializer
208 %tmp10 = add <2 x i32> %tmp6, %tmp
    [all...]
2011-04-26-SchedTweak.ll 45 %tmp6 = load i32, i32* %block_count, align 4
48 %tmp10 = zext i32 %tmp6 to i64
2014-01-09-pseudo_expand_implicit_reg.ll 46 %tmp6 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 3
48 %tmp8 = call <8 x i8> @llvm.arm.neon.vtbx4(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5, <8 x i8> %tmp6, <8 x i8> %tmp7)
ldaex-stlex.ll 25 %tmp6 = lshr i64 %val, 32
26 %tmp7 = trunc i64 %tmp6 to i32
  /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp9/common/mips/dspr2/
vp9_intrapred16_dspr2.c 19 int32_t tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7, tmp8; local
28 "lb %[tmp6], 5(%[left]) \n\t"
45 "replv.qb %[tmp6], %[tmp6] \n\t"
87 "sw %[tmp6], (%[dst]) \n\t"
88 "sw %[tmp6], 4(%[dst]) \n\t"
89 "sw %[tmp6], 8(%[dst]) \n\t"
90 "sw %[tmp6], 12(%[dst]) \n\t"
155 [tmp6] "=&r" (tmp6), [tmp8] "=&r" (tmp8)
    [all...]
  /external/llvm/test/Bitcode/
metadata-2.ll 34 %tmp6 = lshr i32 %tmp4, 2 ; <i32> [#uses=1]
35 %tmp7 = and i32 %tmp6, 858993459 ; <i32> [#uses=1]
56 %tmp6 = or i32 %tmp2, %tmp5 ; <i32> [#uses=2]
57 %tmp8 = lshr i32 %tmp6, 2 ; <i32> [#uses=1]
59 %tmp11 = shl i32 %tmp6, 2 ; <i32> [#uses=1]
  /external/opencv3/3rdparty/libjpeg/
jfdctint.c 1589 INT32 tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6; local
1788 INT32 tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6; local
1988 INT32 tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7; local
2167 INT32 tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7; local
2375 INT32 tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7; local
2556 INT32 tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6; local
3343 INT32 tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7; local
3531 INT32 tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6; local
    [all...]
  /external/llvm/test/Transforms/InstCombine/
vec_shuffle.ll 79 define <4 x i8> @test9(<16 x i8> %tmp6) nounwind {
83 %tmp7 = shufflevector <16 x i8> %tmp6, <16 x i8> undef, <4 x i32> < i32 13, i32 9, i32 4, i32 13 > ; <<4 x i8>> [#uses=1]
91 define <4 x i8> @test9a(<16 x i8> %tmp6) nounwind {
96 %tmp7 = shufflevector <16 x i8> %tmp6, <16 x i8> undef, <4 x i32> < i32 undef, i32 9, i32 4, i32 8 > ; <<4 x i8>> [#uses=1]
103 define <4 x i8> @test9b(<4 x i8> %tmp6, <4 x i8> %tmp7) nounwind {
107 %tmp1 = shufflevector <4 x i8> %tmp6, <4 x i8> %tmp7, <8 x i32> <i32 0, i32 1, i32 4, i32 5, i32 4, i32 5, i32 2, i32 3> ; <<4 x i8>> [#uses=1]
117 %tmp6 = shufflevector <4 x i32> %tmp5, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
118 %tmp7 = shufflevector <4 x i32> %tmp6, <4 x i32> undef, <4 x i32> zeroinitializer
124 define <8 x i8> @test11(<16 x i8> %tmp6) nounwind {
126 ; CHECK-NEXT: shufflevector <16 x i8> %tmp6, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7
    [all...]
  /external/libjpeg-turbo/simd/
jfdctflt-3dn.asm 99 pfsub mm4,mm2 ; mm4=data1-data6=tmp6
111 movq MMWORD [wk(0)], mm4 ; wk(0)=tmp6
154 movq mm0, MMWORD [wk(0)] ; mm0=tmp6
214 pfsub mm4,mm2 ; mm4=data1-data6=tmp6
226 movq MMWORD [wk(0)], mm4 ; wk(0)=tmp6
269 movq mm0, MMWORD [wk(0)] ; mm0=tmp6
  /external/llvm/test/Analysis/BasicAA/
pure-const-dce.ll 33 %tmp6 = call i32 @TestPure( i32 6 ) readonly ; <i32> [#uses=1]
41 %sum5 = add i32 %sum4, %tmp6 ; <i32> [#uses=1]
  /external/llvm/test/Analysis/ScalarEvolution/
sext-iv-2.ll 34 %tmp6 = sext i32 %j.01 to i64 ; <i64> [#uses=1]
35 %tmp7 = getelementptr [32 x [256 x i32]], [32 x [256 x i32]]* @table, i64 0, i64 %tmp5, i64 %tmp6 ; <i32*> [#uses=1]
trip-count5.ll 23 %tmp6 = sext i32 %hiPart.035 to i64 ; <i64> [#uses=1]
24 %tmp7 = getelementptr float, float* %pTmp1, i64 %tmp6 ; <float*> [#uses=1]
  /external/llvm/test/CodeGen/Mips/Fast-ISel/
bswap1.ll 46 ; 32R1: sll $[[TMP6:[0-9]+]], $[[TMP5]], 8
48 ; 32R1: or $[[TMP8:[0-9]+]], $[[TMP4]], $[[TMP6]]
  /external/llvm/test/CodeGen/Thumb2/
v8_IT_3.ll 45 %tmp6 = load i32, i32* %block_count, align 4
48 %tmp10 = zext i32 %tmp6 to i64

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