| /external/llvm/test/Transforms/LoopStrengthReduce/ |
| pr2570.ll | 101 udiv i32 %44, 34162 ; <i32>:46 [#uses=1]
113 udiv i32 -1, %.0329 ; <i32>:53 [#uses=1]
165 udiv i32 %p_52, 1538244727 ; <i32>:90 [#uses=1]
232 udiv i32 -8, %.0317 ; <i32>:123 [#uses=1]
|
| post-inc-icmpzero.ll | 35 %div = udiv i32 %i.addr.0, 10
|
| /external/llvm/unittests/IR/ |
| ConstantsTest.cpp | 84 // @q = constant i1 udiv(i1 -1, i1 1)
88 // @r = constant i1 udiv(i1 1, i1 -1)
220 CHECK(ConstantExpr::getUDiv(P0, P0), "udiv i32 " P0STR ", " P0STR);
245 CHECK(ConstantExpr::getExactUDiv(P0, P0), "udiv exact i32 " P0STR ", " P0STR);
|
| /external/llvm/utils/emacs/ |
| llvm-mode.el | 43 `(,(regexp-opt '("add" "sub" "mul" "sdiv" "udiv" "urem" "srem" "and" "or" "xor"
|
| /external/llvm/utils/vim/syntax/ |
| llvm.vim | 34 syn keyword llvmStatement store sub switch trunc udiv ueq uge ugt uitofp ule ult
|
| /toolchain/binutils/binutils-2.25/opcodes/ |
| moxie-opc.c | 105 { 0x32, MOXIE_F1_AB, "udiv.l" },
|
| /external/llvm/test/Transforms/InstSimplify/ |
| compare.ll | 566 %A = udiv i32 %X, 1000000
574 %A = udiv exact i32 10, %Z
575 %B = udiv exact i32 20, %Z
583 %A = udiv i32 %X, %Y
591 %A = udiv i32 %X, %Y
599 %A = udiv i32 123, %X
608 %A = udiv i32 1, %X
|
| /external/llvm/test/CodeGen/ARM/ |
| vector-promotion.ll | 128 ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = udiv i32 [[EXTRACT]], 7
130 ; IR-STRESS-NEXT: [[DIV:%[a-zA-Z_0-9-]+]] = udiv <2 x i32> [[LOAD]], <i32 7, i32 7>
138 %out = udiv i32 %extract, 7
243 ; IR-BOTH-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = udiv i32 7, [[EXTRACT]]
249 %out = udiv i32 7, %extract
|
| /external/llvm/lib/Support/ |
| APInt.cpp | [all...] |
| /external/valgrind/none/tests/arm64/ |
| integer.stdout.exp | [all...] |
| /external/llvm/unittests/ADT/ |
| APIntTest.cpp | 187 EXPECT_EQ(neg_one, one.udiv(neg_one));
188 EXPECT_EQ(neg_one, neg_one.udiv(one));
189 EXPECT_EQ(one, neg_one.udiv(neg_one));
190 EXPECT_EQ(one, one.udiv(one));
399 auto q = p.udiv(a);
415 q = p.udiv(b);
[all...] |
| /external/llvm/include/llvm/ADT/ |
| APSInt.h | 110 *this = udiv(RHS);
121 return IsUnsigned ? APSInt(udiv(RHS), true) : APSInt(sdiv(RHS), false);
|
| /art/compiler/utils/arm/ |
| assembler_arm32_test.cc | 719 TEST_F(AssemblerArm32Test, Udiv) {
720 T4Helper(&arm::Arm32Assembler::udiv, true, "udiv{cond} {reg1}, {reg2}, {reg3}", "udiv");
|
| /external/llvm/lib/Target/XCore/ |
| XCoreLowerThreadLocal.cpp | 92 case Instruction::UDiv:
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| r600cfg.ll | 75 %49 = udiv i32 %48, 2
|
| /external/llvm/test/CodeGen/Hexagon/ |
| expand-condsets-rm-segment.ll | 75 %div = udiv i32 -1, %1
|
| /external/llvm/test/CodeGen/Mips/ |
| mips64instrs.ll | 149 %div = udiv i64 %0, %1
|
| /external/llvm/test/CodeGen/WebAssembly/ |
| i32.ll | 58 %a = udiv i32 %x, %y
|
| i64.ll | 58 %a = udiv i64 %x, %y
|
| /external/llvm/test/CodeGen/X86/ |
| early-ifcvt.ll | 169 %3 = udiv i32 %a, %b
|
| /external/llvm/test/Other/ |
| lint.ll | 39 %ud = udiv i32 2, 0
|
| /external/llvm/test/Transforms/InstCombine/ |
| sext.ll | 37 %t = udiv i32 %x, 3
|
| /external/llvm/utils/kate/ |
| llvm.xml | 125 <item> udiv </item>
|
| /external/valgrind/VEX/priv/ |
| host_generic_simd64.h | 168 // the ARMv7 UDIV and SDIV instructions.
|
| /prebuilts/go/darwin-x86/src/cmd/internal/rsc.io/arm/armasm/ |
| objdump_test.go | 249 udiv
|
