| /external/llvm/test/Analysis/ScalarEvolution/ |
| flags-from-poison.ll | 582 %forub = udiv i32 1, %v
|
| /external/llvm/test/Bitcode/ |
| compatibility.ll | [all...] |
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-ccmp.ll | 105 ; The sdiv/udiv instructions do not trap when the divisor is zero, so they are
|
| /external/llvm/test/CodeGen/X86/ |
| 2007-08-09-IllegalX86-64Asm.ll | 98 %tmp7.i = udiv i8 %tmp42, %tmp40 ; <i8> [#uses=2]
|
| vector-idiv.ll | 55 %div = udiv <4 x i32> %a, <i32 7, i32 7, i32 7, i32 7>
126 %div = udiv <8 x i32> %a, <i32 7, i32 7, i32 7, i32 7,i32 7, i32 7, i32 7, i32 7>
159 %div = udiv <8 x i16> %a, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
204 %div = udiv <16 x i16> %a, <i16 7, i16 7, i16 7, i16 7,i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7,i16 7, i16 7, i16 7, i16 7>
[all...] |
| /external/llvm/tools/llvm-stress/ |
| llvm-stress.cpp | 354 case 4:{Op = (isFloat?Instruction::FDiv : Instruction::UDiv); break; }
|
| /external/opencv3/3rdparty/libwebp/cpu-features/ |
| cpu-features.c | 703 // sdiv/udiv properly.
|
| /external/v8/test/cctest/ |
| test-disasm-arm64.cc | 484 COMPARE(udiv(w6, w7, w8), "udiv w6, w7, w8");
485 COMPARE(udiv(x9, x10, x11), "udiv x9, x10, x11");
[all...] |
| test-assembler-arm.cc | [all...] |
| /external/vixl/test/ |
| test-assembler-a64.cc | [all...] |
| /art/compiler/utils/ |
| assembler_thumb_test.cc | 967 __ udiv(R0, R1, R2);
968 __ udiv(R8, R9, R10);
[all...] |
| /external/clang/test/CodeGen/ |
| builtins-ppc-vsx.c | 158 // CHECK: udiv <2 x i64>
159 // CHECK-LE: udiv <2 x i64>
|
| zvector.c | 745 // CHECK: %{{.*}} = udiv <16 x i8> [[VAL1]], [[VAL2]]
[all...] |
| /external/llvm/lib/Analysis/ |
| LazyValueInfo.cpp | 856 case Instruction::UDiv:
857 Result.markConstantRange(LHSRange.udiv(RHSRange));
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 150 setOperationAction(ISD::UDIV, MVT::i8, Expand);
156 setOperationAction(ISD::UDIV, MVT::i16, Expand);
[all...] |
| /external/llvm/test/Bindings/OCaml/ |
| core.ml | 273 * CHECK: @const_udiv = global i64 udiv
[all...] |
| /external/v8/src/arm/ |
| disasm-arm.cc | [all...] |
| /prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/lib/gcc/x86_64-w64-mingw32/4.8.3/plugin/include/ |
| rtl.def | 458 DEF_RTL_EXPR(UDIV, "udiv", "ee", RTX_BIN_ARITH)
[all...] |
| /toolchain/binutils/binutils-2.25/cpu/ |
| xstormy16.cpu | [all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/frv/ |
| allinsn.d | 15 00000008 <udiv>:
16 8: 82 00 13 c1 udiv sp,sp,sp
|
| /toolchain/binutils/binutils-2.25/include/ |
| longlong.h | [all...] |
| /art/compiler/utils/arm/ |
| assembler_thumb2.h | 139 void udiv(Register rd, Register rn, Register rm, Condition cond = AL) OVERRIDE;
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMScheduleSwift.td | 305 (instregex "SDIV", "UDIV", "t2SDIV", "t2UDIV")>;
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 169 setOperationAction(ISD::UDIV, MVT::i32, Legal);
216 setOperationAction(ISD::UDIV, MVT::i64, Legal);
272 setOperationAction(ISD::UDIV, Ty, Legal);
[all...] |
| /external/llvm/test/CodeGen/PowerPC/ |
| ctrloop-intrin.ll | 169 %div47 = udiv i64 %conv46, 1000000
|
