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  /toolchain/binutils/binutils-2.25/ld/testsuite/ld-sh/arch/
sh2a-nofpu-or-sh3-nommu.s 10 ! Make sure there are no unexpected or missing instructions.
14 ! Instructions introduced into sh2a-nofpu-or-sh3-nommu
18 ! Instructions inherited from ancestors: sh sh2
sh2a-nofpu-or-sh4-nommu-nofpu.s 10 ! Make sure there are no unexpected or missing instructions.
14 ! Instructions introduced into sh2a-nofpu-or-sh4-nommu-nofpu
17 ! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
sh2a-or-sh3e.s 10 ! Make sure there are no unexpected or missing instructions.
14 ! Instructions introduced into sh2a-or-sh3e
17 ! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2e
sh2e.s 10 ! Make sure there are no unexpected or missing instructions.
14 ! Instructions introduced into sh2e
52 ! Instructions inherited from ancestors: sh sh2
sh3-nommu.s 10 ! Make sure there are no unexpected or missing instructions.
14 ! Instructions introduced into sh3-nommu
28 ! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
sh3.s 10 ! Make sure there are no unexpected or missing instructions.
14 ! Instructions introduced into sh3
17 ! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh3-nommu
sh3e.s 10 ! Make sure there are no unexpected or missing instructions.
14 ! Instructions introduced into sh3e
16 ! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-or-sh3e sh2e sh3 sh3-nommu
sh4-nofpu.s 10 ! Make sure there are no unexpected or missing instructions.
14 ! Instructions introduced into sh4-nofpu
16 ! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
sh4-nommu-nofpu.s 10 ! Make sure there are no unexpected or missing instructions.
14 ! Instructions introduced into sh4-nommu-nofpu
28 ! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
sh4a-nofpu.s 10 ! Make sure there are no unexpected or missing instructions.
14 ! Instructions introduced into sh4a-nofpu
23 ! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
  /external/mesa3d/src/gallium/auxiliary/tgsi/
tgsi_exec.c 45 * ContMask) which are controlled by the flow control instructions (namely:
623 * Initialize machine state by expanding tokens to full instructions,
636 struct tgsi_full_instruction *instructions; local
662 if (mach->Instructions) {
663 FREE( mach->Instructions );
665 mach->Instructions = NULL;
715 instructions = (struct tgsi_full_instruction *)
718 if (!instructions) {
783 instructions = REALLOC(instructions,
    [all...]
  /external/llvm/lib/MC/
MCDwarf.cpp     [all...]
  /external/llvm/lib/Target/Hexagon/Disassembler/
HexagonDisassembler.cpp 357 auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle);
358 auto i = Instructions.end() - 1;
359 for (auto n = Instructions.begin() - 1;; --i, ++Offset) {
413 // relative and absolute addressing instructions since they both have
416 // addressing instructions first and uses this code to change them into
779 // Please note that the instructions must be ordered in the descending order
    [all...]
  /external/mesa3d/src/gallium/drivers/r300/compiler/
radeon_program_alu.c 31 * Shareable transformations that transform "special" ALU instructions
32 * into ALU instructions that are supported by hardware.
358 * to pair instructions correctly.
649 * Eliminates the following ALU instructions:
901 * instructions of the r300 up to r500 vertex engine.
999 * using only the basic instructions
    [all...]
  /external/llvm/test/MC/ARM/
thumb-diagnostics.s 18 @ Instructions which require v6+ for both registers to be low regs.
195 @ Out of range immediate for ADD SP instructions
  /external/llvm/test/MC/Mips/mips2/
valid.s 0 # Instructions that are valid
  /external/llvm/test/MC/Mips/mips32/
valid.s 0 # Instructions that are valid
  /external/llvm/utils/TableGen/
CodeGenTarget.cpp 165 for (const CodeGenInstruction *Inst : instructions()) {
282 // Parse the instructions defined in the .td file.
284 Instructions[Insts[i]] = llvm::make_unique<CodeGenInstruction>(Insts[i]);
300 /// \brief Return all of the instructions defined by the target, ordered by
329 // All of the instructions are now in random order based on the map iteration.
346 /// encodings, reverse the bit order of all instructions.
  /external/mesa3d/src/mesa/drivers/dri/i965/
brw_vs_emit.c 108 struct prog_instruction *inst = vp->Base.Instructions + i;
255 struct prog_instruction *inst = &c->vp->program.Base.Instructions[i];
    [all...]
  /external/mesa3d/src/mesa/drivers/dri/r200/
r200_fragshader.c 145 struct atifs_instruction *inst = &shader->Instructions[pass][pc];
281 /* fglrx does clamp the last instructions to 0_1 it seems */
  /external/mesa3d/src/mesa/swrast/
s_atifragshader.c 344 inst = &shader->Instructions[pass][pc];
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/
vfp1xD.s 1 @ VFP Instructions for v1xD variants (Single precision only)
352 @ ARM VMSR/VMRS instructions
384 @ Priviledged extensions to VMSR/VMRS instructions
vfp1xD_t2.s 1 @ VFP Instructions for v1xD variants (Single precision only)
  /external/llvm/test/MC/Mips/mips1/
invalid-mips4.s 0 # Instructions that are invalid
invalid-mips5.s 0 # Instructions that are invalid

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