| /external/llvm/lib/Target/Mips/ |
| MipsLongBranch.cpp | 77 void splitMBB(MachineBasicBlock *MBB);
80 void replaceBranch(MachineBasicBlock &MBB, Iter Br, DebugLoc DL,
111 llvm_unreachable("This instruction does not have an MBB operand.");
124 // Split MBB if it has two direct jumps/branches.
125 void MipsLongBranch::splitMBB(MachineBasicBlock *MBB) {
126 ReverseIter End = MBB->rend();
127 ReverseIter LastBr = getNonDebugInstr(MBB->rbegin(), End);
129 // Return if MBB has no branch instructions.
136 // MBB has only one branch instruction if FirstBr is not a branch
144 // Create a new MBB. Move instructions in MBB to the newly created MBB
[all...] |
| MipsSERegisterInfo.cpp | 180 MachineBasicBlock &MBB = *MI.getParent();
184 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
188 MBB.getParent()->getSubtarget().getInstrInfo());
189 BuildMI(MBB, II, DL, TII.get(ABI.GetPtrAddiuOp()), Reg)
199 MachineBasicBlock &MBB = *MI.getParent();
204 MBB.getParent()->getSubtarget().getInstrInfo());
205 unsigned Reg = TII.loadImmediate(Offset, MBB, II, DL,
207 BuildMI(MBB, II, DL, TII.get(ABI.GetPtrAdduOp()), Reg).addReg(FrameReg)
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCTLSDynamicCall.cpp | 53 bool processBlock(MachineBasicBlock &MBB) {
55 bool Is64Bit = MBB.getParent()->getSubtarget<PPCSubtarget>().isPPC64();
57 for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
103 MachineInstr *Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3)
112 MachineInstr *Call = (BuildMI(MBB, I, DL, TII->get(Opc2), GPR3)
116 BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), OutReg)
128 LIS->repairIntervalsInRange(&MBB, First, Last, OrigRegs);
|
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyRegStackify.cpp | 136 for (MachineBasicBlock &MBB : MF) {
137 for (MachineInstr &MI : reverse(MBB)) {
202 if (Def->getParent() != &MBB)
213 MBB.insert(MachineBasicBlock::instr_iterator(Insert),
228 for (MachineBasicBlock &MBB : MF)
229 MBB.addLiveIn(WebAssembly::EXPR_STACK);
235 for (MachineBasicBlock &MBB : MF) {
236 for (MachineInstr &MI : MBB) {
|
| WebAssemblyStoreResults.cpp | 78 for (auto &MBB : MF) {
79 DEBUG(dbgs() << "Basic Block: " << MBB.getName() << '\n');
80 for (auto &MI : MBB)
104 if (!MDT.dominates(&MBB, Pred))
|
| WebAssemblyLowerBrUnless.cpp | 63 for (auto &MBB : MF) {
64 for (auto MII = MBB.begin(); MII != MBB.end(); ) {
111 BuildMI(MBB, MI, MI->getDebugLoc(), TII.get(WebAssembly::CONST_I32), ZeroReg)
115 BuildMI(MBB, MI, MI->getDebugLoc(), TII.get(WebAssembly::EQ_I32), Tmp)
125 BuildMI(MBB, MI, MI->getDebugLoc(), TII.get(WebAssembly::BR_IF))
128 MBB.erase(MI);
|
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| AsmPrinterHandler.h | 55 virtual void beginFunclet(const MachineBasicBlock &MBB,
|
| /external/llvm/lib/CodeGen/ |
| MachineCSE.cpp | 39 "Number of cross-MBB physreg referencing CS eliminated");
84 MachineBasicBlock *MBB);
89 const MachineBasicBlock *MBB,
100 void EnterScope(MachineBasicBlock *MBB);
101 void ExitScope(MachineBasicBlock *MBB);
102 bool ProcessBlock(MachineBasicBlock *MBB);
123 MachineBasicBlock *MBB) {
218 const MachineBasicBlock *MBB,
233 if (!MRI->isConstantPhysReg(Reg, *MBB->getParent()))
257 if (!MO.isDead() && !isPhysDefTriviallyDead(Reg, I, MBB->end())
[all...] |
| ShrinkWrap.cpp | 151 /// \brief Update the Save and Restore points such that \p MBB is in
156 void updateSaveRestorePoints(MachineBasicBlock &MBB, RegScavenger *RS);
269 void ShrinkWrap::updateSaveRestorePoints(MachineBasicBlock &MBB,
273 Save = &MBB;
275 Save = MDT->findNearestCommonDominator(Save, &MBB);
283 Restore = &MBB;
285 Restore = MPDT->findNearestCommonDominator(Restore, &MBB);
289 if (Restore == &MBB) {
290 for (const MachineInstr &Terminator : MBB.terminators()) {
294 if (MBB.succ_empty())
[all...] |
| LiveRangeCalc.cpp | 174 // MBB. PHI operands are paired: (Reg, PredMBB).
202 MachineBasicBlock *MBB = I.DomNode->getBlock();
205 std::tie(Start, End) = Indexes->getMBBRange(MBB);
213 assert(Seen.test(MBB->getNumber()));
214 Map[MBB] = LiveOutPair(I.Value, nullptr);
229 assert(UseMBB && "No MBB at Use");
231 // Is there a def in the same MBB we can extend?
271 MachineBasicBlock *MBB = MF->getBlockNumbered(WorkList[i]);
274 if (MBB->pred_empty()) {
275 MBB->getParent()->verify()
[all...] |
| StackMapLivenessAnalysis.cpp | 122 for (auto &MBB : MF) {
123 DEBUG(dbgs() << "****** BB " << MBB.getName() << " ******\n");
125 LiveRegs.addLiveOuts(&MBB);
129 for (auto I = MBB.rbegin(), E = MBB.rend(); I != E; ++I) {
|
| ExecutionDepsFix.cpp | 355 void ExeDepsFix::enterBasicBlock(MachineBasicBlock *MBB) {
366 // Set up LiveRegs to represent registers entering MBB.
377 if (MBB->pred_empty()) {
378 for (const auto &LI : MBB->liveins()) {
386 DEBUG(dbgs() << "BB#" << MBB->getNumber() << ": entry\n");
391 for (MachineBasicBlock::const_pred_iterator pi = MBB->pred_begin(),
392 pe = MBB->pred_end(); pi != pe; ++pi) {
428 DEBUG(dbgs() << "BB#" << MBB->getNumber()
432 void ExeDepsFix::leaveBasicBlock(MachineBasicBlock *MBB) {
434 // Save live registers at end of MBB - used by enterBasicBlock()
[all...] |
| SplitKit.cpp | 58 const MachineBasicBlock *MBB = MF.getBlockNumbered(Num);
60 const MachineBasicBlock *LPad = MBB->getLandingPadSuccessor();
62 SlotIndex MBBEnd = LIS.getMBBEndIdx(MBB);
67 MachineBasicBlock::const_iterator FirstTerm = MBB->getFirstTerminator();
68 if (FirstTerm == MBB->end())
78 for (MachineBasicBlock::const_iterator I = MBB->end(), E = MBB->begin();
93 // Find the value leaving MBB.
98 // If the value leaving MBB was defined after the call in MBB, it can'
[all...] |
| DFAPacketizer.cpp | 194 void VLIWPacketizerList::endPacket(MachineBasicBlock *MBB,
198 finalizeBundle(*MBB, MIFirst->getIterator(), MI->getIterator());
205 void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB,
209 VLIWScheduler->startBlock(MBB);
210 VLIWScheduler->enterRegion(MBB, BeginItr, EndItr,
229 endPacket(MBB, MI);
234 if (this->ignorePseudoInstruction(MI, MBB))
255 endPacket(MBB, MI);
263 endPacket(MBB, MI);
271 endPacket(MBB, EndItr)
[all...] |
| ImplicitNullChecks.cpp | 96 bool analyzeBlockForNullChecks(MachineBasicBlock &MBB,
98 MachineInstr *insertFaultingLoad(MachineInstr *LoadMI, MachineBasicBlock *MBB,
212 for (auto &MBB : MF)
213 analyzeBlockForNullChecks(MBB, NullCheckList);
221 /// Analyze MBB to check if its terminating branch can be turned into an
225 MachineBasicBlock &MBB, SmallVectorImpl<NullCheck> &NullCheckList) {
229 if (auto *BB = MBB.getBasicBlock())
237 if (TII->AnalyzeBranchPredicate(MBB, MBP, true))
332 NullCheckList.emplace_back(MI, MBP.ConditionDef, &MBB, NotNullSucc,
348 /// faults. The FAULTING_LOAD_OP instruction is inserted at the end of MBB
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIInsertWaits.cpp | 98 void pushInstruction(MachineBasicBlock &MBB,
102 bool insertWait(MachineBasicBlock &MBB,
113 void handleSendMsg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I);
249 void SIInsertWaits::pushInstruction(MachineBasicBlock &MBB,
270 if (MBB.getParent()->getSubtarget<AMDGPUSubtarget>().getGeneration() >=
284 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::S_NOP))
320 bool SIInsertWaits::insertWait(MachineBasicBlock &MBB,
325 if (I != MBB.end() && I->getOpcode() == AMDGPU::S_ENDPGM)
374 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::S_WAITCNT))
428 void SIInsertWaits::handleSendMsg(MachineBasicBlock &MBB,
[all...] |
| SIFixSGPRLiveRanges.cpp | 127 for (MachineBasicBlock *MBB : depth_first(Entry)) {
128 for (const MachineInstr &MI : *MBB) {
143 if (LV->isLiveOut(Def, *MBB))
150 if (MBB->succ_size() < 2)
155 assert(MBB->succ_size() == 2);
156 MachineBasicBlock *SuccA = *MBB->succ_begin();
157 MachineBasicBlock *SuccB = *(++MBB->succ_begin());
|
| R600Packetizer.cpp | 166 const MachineBasicBlock *MBB) override {
350 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
351 MBB != MBBe; ++MBB) {
352 MachineBasicBlock::iterator End = MBB->end();
353 MachineBasicBlock::iterator MI = MBB->begin();
359 MBB->erase(DeleteMI);
360 End = MBB->end();
368 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
369 MBB != MBBe; ++MBB)
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 66 MachineBasicBlock &MBB = *MI.getParent();
71 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
77 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
84 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
99 MachineBasicBlock &MBB = *MI.getParent();
103 TII.loadImmediate(MBB, II, ScratchOffset, Offset);
107 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
113 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r))
120 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
133 MachineBasicBlock &MBB = *MI.getParent()
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64DeadRegisterDefinitionsPass.cpp | 40 bool processMachineBasicBlock(MachineBasicBlock &MBB);
81 MachineBasicBlock &MBB) {
83 for (MachineInstr &MI : MBB) {
139 for (auto &MBB : MF)
140 if (processMachineBasicBlock(MBB))
|
| /external/llvm/lib/Target/ARM/ |
| MLxExpansionPass.cpp | 68 void ExpandFPMLxInstruction(MachineBasicBlock &MBB, MachineInstr *MI,
71 bool ExpandFPMLxInstructions(MachineBasicBlock &MBB);
94 MachineBasicBlock *MBB = MI->getParent();
97 if (DefMI->getParent() != MBB)
123 MachineBasicBlock *MBB = MI->getParent();
125 if (UseMI->getParent() != MBB)
134 if (UseMI->getParent() != MBB)
142 /// a single-MBB loop.
148 MachineBasicBlock *MBB = MI->getParent();
152 if (DefMI->getParent() != MBB)
[all...] |
| ARMFrameLowering.cpp | 123 static void emitRegPlusImmediate(bool isARM, MachineBasicBlock &MBB,
131 emitARMRegPlusImmediate(MBB, MBBI, dl, DestReg, SrcReg, NumBytes,
134 emitT2RegPlusImmediate(MBB, MBBI, dl, DestReg, SrcReg, NumBytes,
138 static void emitSPUpdate(bool isARM, MachineBasicBlock &MBB,
144 emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM::SP, NumBytes,
208 void emitDefCFAOffsets(MachineModuleInfo &MMI, MachineBasicBlock &MBB,
218 BuildMI(MBB, std::next(Info.I), dl,
236 MachineBasicBlock &MBB,
258 AddDefaultPred(BuildMI(MBB, MBBI, DL, TII.get(ARM::BFC), Reg)
263 AddDefaultPred(BuildMI(MBB, MBBI, DL, TII.get(ARM::BICri), Reg
[all...] |
| ARMLoadStoreOptimizer.cpp | 130 void moveLiveRegsBefore(const MachineBasicBlock &MBB,
133 void UpdateBaseRegUses(MachineBasicBlock &MBB,
137 MachineInstr *CreateLoadStoreMulti(MachineBasicBlock &MBB,
141 MachineInstr *CreateLoadStoreDouble(MachineBasicBlock &MBB,
147 bool FixInvalidRegPairOp(MachineBasicBlock &MBB,
152 bool LoadStoreMultipleOpti(MachineBasicBlock &MBB);
153 bool MergeReturnIntoLDM(MachineBasicBlock &MBB);
154 bool CombineMovBx(MachineBasicBlock &MBB);
440 ARMLoadStoreOpt::UpdateBaseRegUses(MachineBasicBlock &MBB,
448 for (; MBBI != MBB.end(); ++MBBI)
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600ExpandSpecialInstrs.cpp | 57 MachineBasicBlock &MBB = *BB;
58 MachineBasicBlock::iterator I = MBB.begin();
59 while (I != MBB.end()) {
151 BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(Opcode), DstReg)
|
| /external/llvm/include/llvm/CodeGen/ |
| LiveVariables.h | 103 /// findKill - Find a kill instruction in MBB. Return NULL if none is found.
104 MachineInstr *findKill(const MachineBasicBlock *MBB) const;
106 /// isLiveIn - Is Reg live in to MBB? This means that Reg is live through
107 /// MBB, or it is killed in MBB. If Reg is only used by PHI instructions in
108 /// MBB, it is not considered live in.
109 bool isLiveIn(const MachineBasicBlock &MBB,
181 void runOnBlock(MachineBasicBlock *MBB, unsigned NumRegs);
282 void HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
285 bool isLiveIn(unsigned Reg, const MachineBasicBlock &MBB) {
[all...] |
