| /external/llvm/lib/Target/ARM/ |
| Thumb2InstrInfo.h | 39 bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
42 void copyPhysReg(MachineBasicBlock &MBB,
47 void storeRegToStackSlot(MachineBasicBlock &MBB,
53 void loadRegFromStackSlot(MachineBasicBlock &MBB,
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| A15SDOptimizer.cpp | 69 unsigned createDupLane(MachineBasicBlock &MBB,
75 unsigned createExtractSubreg(MachineBasicBlock &MBB,
81 unsigned createVExt(MachineBasicBlock &MBB,
86 unsigned createRegSequence(MachineBasicBlock &MBB,
91 unsigned createInsertSubreg(MachineBasicBlock &MBB,
96 unsigned createImplicitDef(MachineBasicBlock &MBB,
430 A15SDOptimizer::createDupLane(MachineBasicBlock &MBB,
436 AddDefaultPred(BuildMI(MBB,
449 A15SDOptimizer::createExtractSubreg(MachineBasicBlock &MBB,
455 BuildMI(MBB,
[all...] |
| ARMOptimizeBarriersPass.cpp | 57 for (auto &MBB : MF) {
61 for (auto &MI : MBB) {
|
| ThumbRegisterInfo.h | 41 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
54 bool saveScavengerRegister(MachineBasicBlock &MBB,
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILFrameLowering.h | 42 virtual void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
|
| R600InstrInfo.cpp | 49 R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
58 BuildMI(MBB, MI, DL, get(AMDGPU::MOV))
71 BuildMI(MBB, MI, DL, get(AMDGPU::MOV), DestReg)
163 findFirstPredicateSetterFrom(MachineBasicBlock &MBB,
166 while (I != MBB.begin()) {
177 R600InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
186 MachineBasicBlock::iterator I = MBB.end();
187 if (I == MBB.begin())
191 if (I == MBB.begin())
204 if (I == MBB.begin() |
[all...] |
| R600InstrInfo.h | 43 virtual void copyPhysReg(MachineBasicBlock &MBB,
68 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
71 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const;
73 unsigned RemoveBranch(MachineBasicBlock &MBB) const;
80 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
83 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
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| /external/llvm/include/llvm/Target/ |
| TargetFrameLowering.h | 157 MachineBasicBlock &MBB) const = 0;
159 MachineBasicBlock &MBB) const = 0;
185 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
196 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
285 MachineBasicBlock &MBB,
291 /// Check whether or not the given \p MBB can be used as a prologue
295 /// \p MBB will be correctly handled by the target.
299 virtual bool canUseAsPrologue(const MachineBasicBlock &MBB) const {
303 /// Check whether or not the given \p MBB can be used as a epilogue
307 /// \p MBB will be correctly handled by the target
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreFrameLowering.cpp | 62 static void EmitDefCfaRegister(MachineBasicBlock &MBB,
68 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
72 static void EmitDefCfaOffset(MachineBasicBlock &MBB,
78 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
82 static void EmitCfiOffset(MachineBasicBlock &MBB,
88 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
98 static void IfNeededExtSP(MachineBasicBlock &MBB,
108 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(OpImm);
111 EmitDefCfaOffset(MBB, MBBI, dl, TII, MMI, Adjusted*4);
122 static void IfNeededLDAWSP(MachineBasicBlock &MBB,
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 328 const MachineBasicBlock &MBB = *BI;
329 if (!MBB.isReturnBlock())
331 const MachineInstr &Ret = MBB.back();
559 bool PPCFrameLowering::findScratchRegister(MachineBasicBlock *MBB,
568 // If MBB is an entry or exit block, use R0 as the scratch register
569 if ((UseAtEnd && MBB->isReturnBlock()) ||
570 (!UseAtEnd && (&MBB->getParent()->front() == MBB)))
573 RS.enterBasicBlock(MBB);
575 if (UseAtEnd && !MBB->empty())
[all...] |
| PPCRegisterInfo.cpp | 324 MachineBasicBlock &MBB = *MI.getParent();
326 MachineFunction &MF = *MBB.getParent();
359 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
363 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
367 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
384 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg)
389 BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg)
395 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
399 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
409 BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| DelaySlotFiller.cpp | 54 bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
86 findDelayInstr(MachineBasicBlock &MBB, MachineBasicBlock::iterator slot);
90 bool tryCombineRestoreWithPrevInst(MachineBasicBlock &MBB,
108 bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
110 Subtarget = &MBB.getParent()->getSubtarget<SparcSubtarget>();
113 for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {
121 Changed |= tryCombineRestoreWithPrevInst(MBB, MI);
130 BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP));
139 MachineBasicBlock::iterator D = MBB.end()
[all...] |
| /external/llvm/lib/CodeGen/ |
| MachineSink.cpp | 106 bool ProcessBlock(MachineBasicBlock &MBB);
128 bool AllUsesDominatedByBlock(unsigned Reg, MachineBasicBlock *MBB,
131 MachineBasicBlock *FindSuccToSinkTo(MachineInstr *MI, MachineBasicBlock *MBB,
134 MachineBasicBlock *MBB,
139 MachineBasicBlock *MBB);
142 GetAllSortedSuccessors(MachineInstr *MI, MachineBasicBlock *MBB,
158 MachineBasicBlock *MBB) {
196 MachineBasicBlock *MBB,
207 // BreakPHIEdge is true if all the uses are in the successor MBB being sunken
227 if (!(UseBlock == MBB && UseInst->isPHI() &
[all...] |
| LivePhysRegs.cpp | 129 /// Add live-in registers of basic block \p MBB to \p LiveRegs.
130 static void addLiveIns(LivePhysRegs &LiveRegs, const MachineBasicBlock &MBB) {
131 for (const auto &LI : MBB.liveins())
149 void LivePhysRegs::addLiveOuts(const MachineBasicBlock *MBB,
152 const MachineFunction &MF = *MBB->getParent();
154 if (!MBB->isReturnBlock()) {
163 for (const MachineBasicBlock *Succ : MBB->successors())
167 void LivePhysRegs::addLiveIns(const MachineBasicBlock *MBB,
170 const MachineFunction &MF = *MBB->getParent();
173 ::addLiveIns(*this, *MBB);
[all...] |
| SplitKit.h | 68 MachineBasicBlock *MBB;
170 /// isThroughBlock - Return true if CurLI is live through MBB without uses.
171 bool isThroughBlock(unsigned MBB) const { return ThroughBlocks.test(MBB); }
320 MachineBasicBlock &MBB,
327 /// getShallowDominator - Returns the least busy dominator of MBB that is
329 MachineBasicBlock *findShallowDominator(MachineBasicBlock *MBB,
379 /// enterIntvAtEnd - Enter the open interval at the end of MBB.
380 /// Use the open interval from the inserted copy to the MBB end.
382 SlotIndex enterIntvAtEnd(MachineBasicBlock &MBB);
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZFrameLowering.cpp | 109 // block MBB. IsImplicit says whether this is an explicit operand to the
112 static void addSavedGPR(MachineBasicBlock &MBB, MachineInstrBuilder &MIB,
115 MBB.getParent()->getSubtarget().getRegisterInfo();
117 bool IsLive = MBB.isLiveIn(GPR64) || MBB.isLiveIn(GPR32);
121 MBB.addLiveIn(GPR64);
126 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
133 MachineFunction &MF = *MBB.getParent();
178 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::STMG));
181 addSavedGPR(MBB, MIB, LowGPR, false)
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsDelaySlotFiller.cpp | 81 /// Set bits in Uses corresponding to MBB's live-out registers except for
83 void addLiveOut(const MachineBasicBlock &MBB,
198 bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
200 Iter replaceWithCompactBranch(MachineBasicBlock &MBB,
203 Iter replaceWithCompactJump(MachineBasicBlock &MBB,
215 bool searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End,
221 bool searchBackward(MachineBasicBlock &MBB, Iter Slot) const;
223 /// This function searches MBB in the forward direction for an instruction
225 bool searchForward(MachineBasicBlock &MBB, Iter Slot) const;
227 /// This function searches one of MBB's successor blocks for an instructio
[all...] |
| Mips16RegisterInfo.cpp | 61 (MachineBasicBlock &MBB,
67 const TargetInstrInfo &TII = *MBB.getParent()->getSubtarget().getInstrInfo();
68 TII.copyPhysReg(MBB, I, DL, Mips::T0, Reg, true);
69 TII.copyPhysReg(MBB, UseMI, DL, Reg, Mips::T0, true);
138 MachineBasicBlock &MBB = *MI.getParent();
143 FrameReg = TII.loadImmediate(FrameReg, Offset, MBB, II, DL, NewImm);
|
| /external/llvm/lib/Target/AMDGPU/ |
| R600InstrInfo.h | 40 MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
46 MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
64 void copyPhysReg(MachineBasicBlock &MBB,
68 bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
162 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
165 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
169 unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
176 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
179 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
222 MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
[all...] |
| SIFrameLowering.cpp | 50 MachineBasicBlock &MBB) const {
54 assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
101 MBB.addLiveIn(PreloadedScratchWaveOffsetReg);
105 MBB.addLiveIn(PreloadedPrivateBufferReg);
161 MachineBasicBlock::iterator I = MBB.begin();
167 BuildMI(MBB, I, DL, SMovB32, ScratchWaveOffsetReg)
185 BuildMI(MBB, I, DL, SMovB64, Rsrc01)
187 BuildMI(MBB, I, DL, SMovB64, Rsrc23)
197 BuildMI(MBB, I, DL, SMovB32, Rsrc0)
201 BuildMI(MBB, I, DL, SMovB32, Rsrc1
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonFrameLowering.cpp | 232 bool needsStackFrame(const MachineBasicBlock &MBB, const BitVector &CSR) {
233 for (auto &I : MBB) {
268 /// Returns true if MBB has a machine instructions that indicates a tail call
270 bool hasTailCall(const MachineBasicBlock &MBB) {
271 MachineBasicBlock::const_iterator I = MBB.getLastNonDebugInstr();
276 /// Returns true if MBB contains an instruction that returns.
277 bool hasReturn(const MachineBasicBlock &MBB) {
278 for (auto I = MBB.getFirstTerminator(), E = MBB.end(); I != E; ++I)
395 MachineBasicBlock &MBB) const
[all...] |
| HexagonAsmPrinter.h | 41 const MachineBasicBlock *MBB) const override;
46 const MachineInstr &MBB);
|
| HexagonCFGOptimizer.cpp | 105 MachineBasicBlock *MBB = &*MBBb;
108 MachineBasicBlock::iterator MII = MBB->getFirstTerminator();
109 if (MII != MBB->end()) {
143 unsigned NumSuccs = MBB->succ_size();
144 MachineBasicBlock::succ_iterator SI = MBB->succ_begin();
150 if (MBB->isLayoutSuccessor(FirstSucc)) {
153 } else if (MBB->isLayoutSuccessor(SecondSucc)) {
189 MBB->replaceSuccessor(JumpAroundTarget, UncondTarget);
|
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| DbgValueHistoryCalculator.cpp | 145 // \brief Returns the first instruction in @MBB which corresponds to
146 // the function epilogue, or nullptr if @MBB doesn't contain an epilogue.
147 static const MachineInstr *getFirstEpilogueInst(const MachineBasicBlock &MBB) {
148 auto LastMI = MBB.getLastNonDebugInstr();
149 if (LastMI == MBB.end() || !LastMI->isReturn())
156 E = MBB.rend();
162 // If all instructions have the same debug location, assume whole MBB is
164 return MBB.begin();
172 for (const auto &MBB : *MF) {
173 auto FirstEpilogueInst = getFirstEpilogueInst(MBB);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86OptimizeLEAs.cpp | 83 void findLEAs(const MachineBasicBlock &MBB,
102 const MachineBasicBlock *MBB = First.getParent();
105 assert(Last.getParent() == MBB &&
108 return std::distance(MBB->begin(), MachineBasicBlock::const_iterator(&Last)) -
109 std::distance(MBB->begin(), MachineBasicBlock::const_iterator(&First));
220 void OptimizeLEAPass::findLEAs(const MachineBasicBlock &MBB,
222 for (auto &MI : MBB) {
236 MachineBasicBlock *MBB = List[0]->getParent();
239 for (auto I = MBB->begin(), E = MBB->end(); I != E;)
[all...] |
