| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| r6.s | 198 bgeuc $2, $3, ext
199 bgeuc $2, $3, . + 4 + (-32768 << 2)
200 bgeuc $2, $3, . + 4 + (32767 << 2)
201 bgeuc $2, $3, 1f
202 bgeuc $3, $2, 1f
|
| r6-n32.d | 373 0+0448 <[^>]*> 18430000 bgeuc v0,v1,0000044c <[^>]*>
376 0+0450 <[^>]*> 18430000 bgeuc v0,v1,00000454 <[^>]*>
379 0+0458 <[^>]*> 18430000 bgeuc v0,v1,0000045c <[^>]*>
382 0+0460 <[^>]*> 18430000 bgeuc v0,v1,00000464 <[^>]*>
385 0+0468 <[^>]*> 18620000 bgeuc v1,v0,0000046c <[^>]*>
|
| r6.d | 372 0+0448 <[^>]*> 1843ffff bgeuc v0,v1,00000448 <[^>]*>
375 0+0450 <[^>]*> 18438000 bgeuc v0,v1,fffe0454 <[^>]*>
378 0+0458 <[^>]*> 18437fff bgeuc v0,v1,00020458 <[^>]*>
381 0+0460 <[^>]*> 1843ffff bgeuc v0,v1,00000460 <[^>]*>
384 0+0468 <[^>]*> 1862ffff bgeuc v1,v0,00000468 <[^>]*>
|
| r6-n64.d | 549 0+0448 <[^>]*> 18430000 bgeuc v0,v1,0+044c <[^>]*>
554 0+0450 <[^>]*> 18430000 bgeuc v0,v1,0+0454 <[^>]*>
559 0+0458 <[^>]*> 18430000 bgeuc v0,v1,0+045c <[^>]*>
564 0+0460 <[^>]*> 18430000 bgeuc v0,v1,0+0464 <[^>]*>
569 0+0468 <[^>]*> 18620000 bgeuc v1,v0,0+046c <[^>]*>
|
| /external/v8/test/cctest/ |
| test-disasm-mips.cc | 310 COMPARE_PC_REL_COMPACT(bgeuc(a0, a1, -32768),
311 "18858000 bgeuc a0, a1, -32768", -32768);
312 COMPARE_PC_REL_COMPACT(bgeuc(a0, a1, -1),
313 "1885ffff bgeuc a0, a1, -1", -1);
314 COMPARE_PC_REL_COMPACT(bgeuc(a0, a1, 1), "18850001 bgeuc a0, a1, 1",
316 COMPARE_PC_REL_COMPACT(bgeuc(a0, a1, 32767),
317 "18857fff bgeuc a0, a1, 32767", 32767);
[all...] |
| test-disasm-mips64.cc | [all...] |
| /external/v8/src/mips/ |
| constants-mips.cc | 136 case BLEZ: // POP06 bgeuc/bleuc, blezalc, bgezalc
|
| assembler-mips.h | 607 void bgeuc(Register rs, Register rt, int16_t offset);
608 inline void bgeuc(Register rs, Register rt, Label* L) {
609 bgeuc(rs, rt, shifted_branch_offset(L));
[all...] |
| constants-mips.h | 388 POP06 = BLEZ, // bgeuc/bleuc, blezalc, bgezalc
[all...] |
| /external/v8/src/mips64/ |
| constants-mips64.cc | 136 case BLEZ: // POP06 bgeuc/bleuc, blezalc, bgezalc
|
| assembler-mips64.h | 611 void bgeuc(Register rs, Register rt, int16_t offset);
612 inline void bgeuc(Register rs, Register rt, Label* L) {
613 bgeuc(rs, rt, shifted_branch_offset(L));
[all...] |
| /art/compiler/utils/mips64/ |
| assembler_mips64.h | 228 void Bgeuc(GpuRegister rs, GpuRegister rt, uint16_t imm16);
346 void Bgeuc(GpuRegister rs, GpuRegister rt, Mips64Label* label);
|
| assembler_mips64.cc | 595 void Mips64Assembler::Bgeuc(GpuRegister rs, GpuRegister rt, uint16_t imm16) {
685 Bgeuc(rs, rt, imm16_21);
[all...] |
| assembler_mips64_test.cc | 730 TEST_F(AssemblerMIPS64Test, Bgeuc) {
731 BranchCondTwoRegsHelper(&mips64::Mips64Assembler::Bgeuc, "Bgeuc");
[all...] |
| /external/llvm/test/MC/Disassembler/Mips/mips32r6/ |
| valid-mips32r6-el.txt | 26 0x40 0x00 0x43 0x18 # CHECK: bgeuc $2, $3, 256
|
| valid-mips32r6.txt | 40 0x18 0x43 0x00 0x40 # CHECK: bgeuc $2, $3, 256
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| valid.s | 46 bgeuc $2, $3, 256 # CHECK: bgeuc $2, $3, 256 # encoding: [0x18,0x43,0x00,0x40]
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| valid.s | 44 bgeuc $2, $3, 256 # CHECK: bgeuc $2, $3, 256 # encoding: [0x18,0x43,0x00,0x40]
|
| /external/llvm/lib/Target/Mips/ |
| Mips32r6InstrInfo.td | 342 class BGEUC_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR32Opnd>;
672 def BGEUC : BGEUC_ENC, BGEUC_DESC, ISA_MIPS32R6;
[all...] |
| /art/disassembler/ |
| disassembler_mips.cc | 202 { kITypeMask, 6 << kOpcodeShift, "bgeuc", "STB" },
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r6/ |
| valid-mips64r6-el.txt | 24 0x40 0x00 0x43 0x18 # CHECK: bgeuc $2, $3, 256
|
| valid-mips64r6.txt | 57 0x18 0x43 0x00 0x40 # CHECK: bgeuc $2, $3, 256
|
| /external/llvm/lib/Target/Mips/Disassembler/ |
| MipsDisassembler.cpp | 777 // BGEUC if rs != rt && rs != 0 && rt != 0
792 MI.setOpcode(Mips::BGEUC);
[all...] |
| /art/compiler/utils/mips/ |
| assembler_mips.h | 237 void Bgeuc(Register rs, Register rt, uint16_t imm16); // R6
[all...] |
| /art/compiler/optimizing/ |
| code_generator_mips64.cc | [all...] |
