| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| r6.s | 208 bltzalc $2, ext
209 bltzalc $2, . + 4 + (-32768 << 2)
210 bltzalc $2, . + 4 + (32767 << 2)
211 bltzalc $2, 1f
|
| r6-n32.d | 400 0+0490 <[^>]*> 1c420000 bltzalc v0,00000494 <[^>]*>
403 0+0498 <[^>]*> 1c420000 bltzalc v0,0000049c <[^>]*>
406 0+04a0 <[^>]*> 1c420000 bltzalc v0,000004a4 <[^>]*>
409 0+04a8 <[^>]*> 1c420000 bltzalc v0,000004ac <[^>]*>
|
| r6.d | 399 0+0490 <[^>]*> 1c42ffff bltzalc v0,00000490 <[^>]*>
402 0+0498 <[^>]*> 1c428000 bltzalc v0,fffe049c <[^>]*>
405 0+04a0 <[^>]*> 1c427fff bltzalc v0,000204a0 <[^>]*>
408 0+04a8 <[^>]*> 1c42ffff bltzalc v0,000004a8 <[^>]*>
|
| r6-n64.d | 594 0+0490 <[^>]*> 1c420000 bltzalc v0,0+0494 <[^>]*>
599 0+0498 <[^>]*> 1c420000 bltzalc v0,0+049c <[^>]*>
604 0+04a0 <[^>]*> 1c420000 bltzalc v0,0+04a4 <[^>]*>
609 0+04a8 <[^>]*> 1c420000 bltzalc v0,0+04ac <[^>]*>
|
| /external/v8/test/cctest/ |
| test-disasm-mips.cc | 344 COMPARE_PC_REL_COMPACT(bltzalc(a0, -32768),
345 "1c848000 bltzalc a0, -32768", -32768);
346 COMPARE_PC_REL_COMPACT(bltzalc(a0, -1), "1c84ffff bltzalc a0, -1",
348 COMPARE_PC_REL_COMPACT(bltzalc(a0, 1), "1c840001 bltzalc a0, 1", 1);
349 COMPARE_PC_REL_COMPACT(bltzalc(a0, 32767),
350 "1c847fff bltzalc a0, 32767", 32767);
[all...] |
| test-disasm-mips64.cc | [all...] |
| /external/v8/src/mips/ |
| constants-mips.cc | 137 case BGTZ: // POP07 bltuc/bgtuc, bgtzalc, bltzalc
|
| assembler-mips.h | 652 void bltzalc(Register rt, int16_t offset);
653 inline void bltzalc(Register rt, Label* L) {
654 bltzalc(rt, shifted_branch_offset(L));
[all...] |
| constants-mips.h | 389 POP07 = BGTZ, // bltuc/bgtuc, bgtzalc, bltzalc
[all...] |
| disasm-mips.cc | [all...] |
| /external/v8/src/mips64/ |
| constants-mips64.cc | 137 case BGTZ: // POP07 bltuc/bgtuc, bgtzalc, bltzalc
|
| assembler-mips64.h | 656 void bltzalc(Register rt, int16_t offset);
657 inline void bltzalc(Register rt, Label* L) {
658 bltzalc(rt, shifted_branch_offset(L));
[all...] |
| constants-mips64.h | 385 POP07 = BGTZ, // bltuc/bgtuc, bgtzalc, bltzalc
[all...] |
| /external/llvm/test/MC/Disassembler/Mips/mips32r6/ |
| valid-mips32r6-el.txt | 33 0x4d 0x01 0x42 0x1c # CHECK: bltzalc $2, 1332
|
| valid-mips32r6.txt | 44 0x1c 0x42 0x01 0x4d # CHECK: bltzalc $2, 1332
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| valid.s | 53 bltzalc $2, 1332 # CHECK: bltzalc $2, 1332 # encoding: [0x1c,0x42,0x01,0x4d]
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| valid.s | 54 bltzalc $2, 1332 # CHECK: bltzalc $2, 1332 # encoding: [0x1c,0x42,0x01,0x4d]
|
| /external/llvm/lib/Target/Mips/ |
| Mips32r6InstrInfo.td | 454 class BLTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzalc", brtarget, GPR32Opnd> {
682 def BLTZALC : R6MMR6Rel, BLTZALC_ENC, BLTZALC_DESC, ISA_MIPS32R6;
[all...] |
| Mips32r6InstrFormats.td | 393 // BLTZC/BGTZC/BLTZALC/BGEZALC require that rs == rt && rt != 0
|
| MicroMips32r6InstrInfo.td | 201 class BLTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bltzalc", brtarget_mm,
[all...] |
| /external/llvm/test/MC/Mips/micromips32r6/ |
| valid.s | 27 bltzalc $2, 1332 # CHECK: bltzalc $2, 1332 # encoding: [0xe0,0x42,0x02,0x9a]
|
| /external/llvm/test/MC/Disassembler/Mips/micromips32r6/ |
| valid.txt | 45 0xe0 0x42 0x02 0x9a # CHECK: bltzalc $2, 1332
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r6/ |
| valid-mips64r6-el.txt | 34 0x4d 0x01 0x42 0x1c # CHECK: bltzalc $2, 1332
|
| valid-mips64r6.txt | 61 0x1c 0x42 0x01 0x4d # CHECK: bltzalc $2, 1332
|
| /external/llvm/lib/Target/Mips/Disassembler/ |
| MipsDisassembler.cpp | 727 // BLTZALC if rs != 0 && rs == rt
743 MI.setOpcode(Mips::BLTZALC);
[all...] |
