| /external/llvm/test/Transforms/CodeGenPrepare/X86/ |
| cttz-ctlz.ll | 19 ; SLOW: %cmpz = icmp eq i64 %A, 0
20 ; SLOW: br i1 %cmpz, label %cond.end, label %cond.false
40 ; SLOW: %cmpz = icmp eq i64 %A, 0
41 ; SLOW: br i1 %cmpz, label %cond.end, label %cond.false
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/m32r/ |
| m32rx.s | 15 .global cmpz
16 cmpz: label
17 cmpz fp
202 ld fp, @fp || cmpz r1
203 cmpz r1
419 cmpz fp || sadd
420 cmpz fp
|
| m32rx.d | 15 0+0008 <cmpz>:
16 8: 00 7d f0 00 cmpz fp \|\| nop
132 a8: 2d cd 80 71 ld fp,@fp \|\| cmpz r1
133 ac: 2d cd 80 71 ld fp,@fp \|\| cmpz r1
257 1a4: 00 7d d0 e4 cmpz fp \|\| sadd
258 1a8: 00 7d d0 e4 cmpz fp \|\| sadd
|
| /toolchain/binutils/binutils-2.25/opcodes/ |
| m32r-desc.c | 630 /* cmpz $src2 */
632 M32R_INSN_CMPZ, "cmpz", "cmpz", 16,
[all...] |
| m32r-opc.c | 444 /* cmpz $src2 */
[all...] |
| score-dis.c | 229 {0x0030001b, 0x3ff07fff, "cmpz.c\t\t%15-19r"},
[all...] |
| score-opc.h | 208 {0x0030001b, 0x3ff07fff, "cmpz.c\t\t%15-19r"},
|
| score7-dis.c | 261 {0x0030001b, 0x3ff07fff, "cmpz.c\t\t%15-19r"},
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.h | 57 CMPZ, // ARM compare that sets only Z flag.
|
| ARMISelLowering.cpp | [all...] |
| ARMInstrInfo.td | 148 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
[all...] |
| /toolchain/binutils/binutils-2.25/cpu/ |
| m32r.cpu | [all...] |
| /external/llvm/lib/CodeGen/ |
| CodeGenPrepare.cpp | [all...] |
| /toolchain/binutils/binutils-2.25/gas/config/ |
| tc-score.c | [all...] |
| tc-score7.c | [all...] |
