1 ; Renesas M32R CPU description. -*- Scheme -*- 2 ; 3 ; Copyright 1998, 1999, 2000, 2001, 2003, 2007, 2009 4 ; Free Software Foundation, Inc. 5 ; 6 ; Contributed by Red Hat Inc; developed under contract from Mitsubishi 7 ; Electric Corporation. 8 ; 9 ; This file is part of the GNU Binutils. 10 ; 11 ; This program is free software; you can redistribute it and/or modify 12 ; it under the terms of the GNU General Public License as published by 13 ; the Free Software Foundation; either version 3 of the License, or 14 ; (at your option) any later version. 15 ; 16 ; This program is distributed in the hope that it will be useful, 17 ; but WITHOUT ANY WARRANTY; without even the implied warranty of 18 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 ; GNU General Public License for more details. 20 ; 21 ; You should have received a copy of the GNU General Public License 22 ; along with this program; if not, write to the Free Software 23 ; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 24 ; MA 02110-1301, USA. 25 26 (include "simplify.inc") 27 28 ; FIXME: Delete sign extension of accumulator results. 29 ; Sign extension is done when accumulator is read. 30 31 ; define-arch must appear first 32 33 (define-arch 34 (name m32r) ; name of cpu family 35 (comment "Renesas M32R") 36 (default-alignment aligned) 37 (insn-lsb0? #f) 38 (machs m32r m32rx m32r2) 39 (isas m32r) 40 ) 41 42 ; Attributes. 43 44 ; An attribute to describe which pipeline an insn runs in. 45 ; O_OS is a special attribute for sll, sra, sla, slli, srai, slai. 46 ; These instructions have O attribute for m32rx and OS attribute for m32r2. 47 48 (define-attr 49 (for insn) 50 (type enum) 51 (name PIPE) 52 (comment "parallel execution pipeline selection") 53 (values NONE O S OS O_OS) 54 ) 55 56 ; A derived attribute that says which insns can be executed in parallel 57 ; with others. This is a required attribute for architectures with 58 ; parallel execution. 59 60 (define-attr 61 (for insn) 62 (type enum) 63 (name PARALLEL) 64 (attrs META) ; do not define in any generated file for now 65 (values NO YES) 66 (default (if (eq-attr (current-insn) PIPE NONE) (symbol NO) (symbol YES))) 67 ) 68 69 ; Instruction set parameters. 70 71 (define-isa 72 (name m32r) 73 74 ; This is 32 because 16 bit insns always appear as pairs. 75 ; ??? See if this can go away. It's only used by the disassembler (right?) 76 ; to decide how long an unknown insn is. One value isn't sufficient (e.g. if 77 ; on a 16 bit (and not 32 bit) boundary, will only want to advance pc by 16.) 78 (default-insn-bitsize 32) 79 80 ; Number of bytes of insn we can initially fetch. 81 ; The M32R is tricky in that insns are either two 16-bit insns 82 ; (executed sequentially or in parallel) or one 32-bit insn. 83 ; So on one hand the base insn size is 16 bits, but on another it's 32. 84 ; 32 is chosen because: 85 ; - if the chip were ever bi-endian it is believed that the byte order would 86 ; be based on 32 bit quantities 87 ; - 32 bit insns are always aligned on 32 bit boundaries 88 ; - the pc will never stop on a 16 bit (and not 32 bit) boundary 89 ; [well actually it can, but there are no branches to such places] 90 (base-insn-bitsize 32) 91 92 ; Used in computing bit numbers. 93 (default-insn-word-bitsize 32) 94 95 ; The m32r fetches 2 insns at a time. 96 (liw-insns 2) 97 98 ; While the m32r can execute insns in parallel, the base mach can't 99 ; (other than nop). The base mach is greatly handicapped by this, but 100 ; we still need to cleanly handle it. 101 (parallel-insns 2) 102 103 ; Initial bitnumbers to decode insns by. 104 (decode-assist (0 1 2 3 8 9 10 11)) 105 106 ; Classification of instructions that fit in the various frames. 107 ; wip, not currently used 108 (insn-types (long ; name 109 31 ; length 110 (eq-attr (current-insn) LENGTH 31) ; matching insns 111 (0 1 2 7 8 9 10) ; decode-assist 112 ) 113 (short 114 15 115 (eq-attr (current-insn) LENGTH 15) ; matching insns 116 (0 1 2 7 8 9 10) 117 ) 118 ) 119 120 ; Instruction framing. 121 ; Each m32r insn is either one 32 bit insn, two 16 bit insns executed 122 ; serially (left->right), or two 16 bit insns executed parallelly. 123 ; wip, not currently used 124 (frame long32 ; name 125 ((long)) ; list of insns in frame, plus constraint 126 "$0" ; assembler 127 (+ (1 1) (31 $0)) ; value 128 (sequence () (execute $0)) ; action 129 ) 130 (frame serial2x16 131 ((short) 132 (short)) 133 "$0 -> $1" 134 (+ (1 0) (15 $0) (1 0) (15 $1)) 135 (sequence () 136 (execute $0) 137 (execute $1)) 138 ) 139 (frame parallel2x16 140 ((short (eq-attr (current-insn) PIPE "O,BOTH")) 141 (short (eq-attr (current-insn) PIPE "S,BOTH"))) 142 "$0 || $1" 143 (+ (1 0) (15 $0) (1 1) (15 $1)) 144 (parallel () 145 (execute $0) 146 (execute $1)) 147 ) 148 ) 149 151 ; Cpu family definitions. 152 153 ; ??? define-cpu-family [and in general "cpu-family"] might be clearer than 154 ; define-cpu. 155 ; ??? Have define-arch provide defaults for architecture that define-cpu can 156 ; then override [reduces duplication in define-cpu]. 157 ; ??? Another way to go is to delete cpu-families entirely and have one mach 158 ; able to inherit things from another mach (would also need the ability to 159 ; not only override specific inherited things but also disable some, 160 ; e.g. if an insn wasn't supported). 161 162 (define-cpu 163 ; cpu names must be distinct from the architecture name and machine names. 164 ; The "b" suffix stands for "base" and is the convention. 165 ; The "f" suffix stands for "family" and is the convention. 166 (name m32rbf) 167 (comment "Renesas M32R base family") 168 (endian either) 169 (word-bitsize 32) 170 ; Override isa spec (??? keeps things simpler, though it was more true 171 ; in the early days and not so much now). 172 (parallel-insns 1) 173 ) 174 175 (define-cpu 176 (name m32rxf) 177 (comment "Renesas M32Rx family") 178 (endian either) 179 (word-bitsize 32) 180 ; Generated files have an "x" suffix. 181 (file-transform "x") 182 ) 183 184 (define-cpu 185 (name m32r2f) 186 (comment "Renesas M32R2 family") 187 (endian either) 188 (word-bitsize 32) 189 ; Generated files have an "2" suffix. 190 (file-transform "2") 191 ) 192 193 (define-mach 194 (name m32r) 195 (comment "Generic M32R cpu") 196 (cpu m32rbf) 197 ) 198 199 (define-mach 200 (name m32rx) 201 (comment "M32RX cpu") 202 (cpu m32rxf) 203 ) 204 205 (define-mach 206 (name m32r2) 207 (comment "M32R2 cpu") 208 (cpu m32r2f) 209 ) 210 212 ; Model descriptions. 213 214 ; The meaning of this value is wip but at the moment it's intended to describe 215 ; the implementation (i.e. what -mtune=foo does in sparc gcc). 216 ; 217 ; Notes while wip: 218 ; - format of pipeline entry: 219 ; (pipeline name (stage1-name ...) (stage2-name ...) ...) 220 ; The contents of a stage description is wip. 221 ; - each mach must have at least one model 222 ; - the default model must be the first one 223 ;- maybe have `retire' support update total cycle count to handle current 224 ; parallel insn cycle counting problems 225 226 (define-model 227 (name m32r/d) (comment "m32r/d") (attrs) 228 (mach m32r) 229 230 ;(prefetch) 231 ;(retire) 232 233 (pipeline p-non-mem "" () ((fetch) (decode) (execute) (writeback))) 234 (pipeline p-mem "" () ((fetch) (decode) (execute) (memory) (writeback))) 235 236 ; `state' is a list of variables for recording model state 237 (state 238 ; bit mask of h-gr registers, =1 means value being loaded from memory 239 (h-gr UINT) 240 ) 241 242 (unit u-exec "Execution Unit" () 243 1 1 ; issue done 244 () ; state 245 ((sr INT -1) (dr INT -1)) ; inputs 246 ((dr INT -1)) ; outputs 247 () ; profile action (default) 248 ) 249 (unit u-cmp "Compare Unit" () 250 1 1 ; issue done 251 () ; state 252 ((src1 INT -1) (src2 INT -1)) ; inputs 253 () ; outputs 254 () ; profile action (default) 255 ) 256 (unit u-mac "Multiply/Accumulate Unit" () 257 1 1 ; issue done 258 () ; state 259 ((src1 INT -1) (src2 INT -1)) ; inputs 260 () ; outputs 261 () ; profile action (default) 262 ) 263 (unit u-cti "Branch Unit" () 264 1 1 ; issue done 265 () ; state 266 ((sr INT -1)) ; inputs 267 ((pc)) ; outputs 268 () ; profile action (default) 269 ) 270 (unit u-load "Memory Load Unit" () 271 1 1 ; issue done 272 () ; state 273 ((sr INT) 274 ;(ld-mem AI) 275 ) ; inputs 276 ((dr INT)) ; outputs 277 () ; profile action (default) 278 ) 279 (unit u-store "Memory Store Unit" () 280 1 1 ; issue done 281 () ; state 282 ((src1 INT) (src2 INT)) ; inputs 283 () ; ((st-mem AI)) ; outputs 284 () ; profile action (default) 285 ) 286 ) 287 288 (define-model 289 (name test) (comment "test") (attrs) 290 (mach m32r) 291 (pipeline all "" () ((fetch) (decode) (execute) (writeback))) 292 (unit u-exec "Execution Unit" () 293 1 1 ; issue done 294 () () () ()) 295 ) 296 297 ; Each mach must have at least one model. 298 299 (define-model 300 (name m32rx) (comment "m32rx") (attrs) 301 (mach m32rx) 302 303 ; ??? It's 6 stages but I forget the details right now. 304 (pipeline p-o "" () ((fetch) (decode) (execute) (writeback))) 305 (pipeline p-s "" () ((fetch) (decode) (execute) (writeback))) 306 (pipeline p-o-mem "" () ((fetch) (decode) (execute) (memory) (writeback))) 307 308 (unit u-exec "Execution Unit" () 309 1 1 ; issue done 310 () ; state 311 ((sr INT -1) (dr INT -1)) ; inputs 312 ((dr INT -1)) ; outputs 313 () ; profile action (default) 314 ) 315 (unit u-cmp "Compare Unit" () 316 1 1 ; issue done 317 () ; state 318 ((src1 INT -1) (src2 INT -1)) ; inputs 319 () ; outputs 320 () ; profile action (default) 321 ) 322 (unit u-mac "Multiply/Accumulate Unit" () 323 1 1 ; issue done 324 () ; state 325 ((src1 INT -1) (src2 INT -1)) ; inputs 326 () ; outputs 327 () ; profile action (default) 328 ) 329 (unit u-cti "Branch Unit" () 330 1 1 ; issue done 331 () ; state 332 ((sr INT -1)) ; inputs 333 ((pc)) ; outputs 334 () ; profile action (default) 335 ) 336 (unit u-load "Memory Load Unit" () 337 1 1 ; issue done 338 () ; state 339 ((sr INT)) ; inputs 340 ((dr INT)) ; outputs 341 () ; profile action (default) 342 ) 343 (unit u-store "Memory Store Unit" () 344 1 1 ; issue done 345 () ; state 346 ((src1 INT) (src2 INT)) ; inputs 347 () ; outputs 348 () ; profile action (default) 349 ) 350 ) 351 352 (define-model 353 (name m32r2) (comment "m32r2") (attrs) 354 (mach m32r2) 355 356 ; ??? It's 6 stages but I forget the details right now. 357 (pipeline p-o "" () ((fetch) (decode) (execute) (writeback))) 358 (pipeline p-s "" () ((fetch) (decode) (execute) (writeback))) 359 (pipeline p-o-mem "" () ((fetch) (decode) (execute) (memory) (writeback))) 360 361 (unit u-exec "Execution Unit" () 362 1 1 ; issue done 363 () ; state 364 ((sr INT -1) (dr INT -1)) ; inputs 365 ((dr INT -1)) ; outputs 366 () ; profile action (default) 367 ) 368 (unit u-cmp "Compare Unit" () 369 1 1 ; issue done 370 () ; state 371 ((src1 INT -1) (src2 INT -1)) ; inputs 372 () ; outputs 373 () ; profile action (default) 374 ) 375 (unit u-mac "Multiply/Accumulate Unit" () 376 1 1 ; issue done 377 () ; state 378 ((src1 INT -1) (src2 INT -1)) ; inputs 379 () ; outputs 380 () ; profile action (default) 381 ) 382 (unit u-cti "Branch Unit" () 383 1 1 ; issue done 384 () ; state 385 ((sr INT -1)) ; inputs 386 ((pc)) ; outputs 387 () ; profile action (default) 388 ) 389 (unit u-load "Memory Load Unit" () 390 1 1 ; issue done 391 () ; state 392 ((sr INT)) ; inputs 393 ((dr INT)) ; outputs 394 () ; profile action (default) 395 ) 396 (unit u-store "Memory Store Unit" () 397 1 1 ; issue done 398 () ; state 399 ((src1 INT) (src2 INT)) ; inputs 400 () ; outputs 401 () ; profile action (default) 402 ) 403 ) 404 406 ; The instruction fetch/execute cycle. 407 ; This is split into two parts as sometimes more than one instruction is 408 ; decoded at once. 409 ; The `const SI' argument to decode/execute is used to distinguish 410 ; multiple instructions processed at the same time (e.g. m32r). 411 ; 412 ; ??? This is wip, and not currently used. 413 ; ??? Needs to be moved to define-isa. 414 415 ; This is how to fetch and decode an instruction. 416 417 ;(define-extract 418 ; (sequence VOID 419 ; (if VOID (ne AI (and AI pc (const AI 3)) (const AI 0)) 420 ; (sequence VOID 421 ; (set-quiet USI (scratch UHI insn1) (ifetch UHI pc)) 422 ; (decode VOID pc (and UHI insn1 (const UHI #x7fff)) 423 ; (const SI 0))) 424 ; (sequence VOID 425 ; (set-quiet USI (scratch USI insn) (ifetch USI pc)) 426 ; (if VOID (ne USI (and USI insn (const USI #x80000000)) 427 ; (const USI 0)) 428 ; (decode VOID pc (srl USI insn (const WI 16)) (const SI 0)) 429 ; (sequence VOID 430 ; ; ??? parallel support 431 ; (decode VOID pc (srl USI insn (const WI 16)) 432 ; (const SI 0)) 433 ; (decode VOID (add AI pc (const AI 2)) 434 ; (and USI insn (const WI #x7fff)) 435 ; (const SI 1)))))) 436 ; ) 437 ;) 438 439 ; This is how to execute a decoded instruction. 440 441 ;(define-execute 442 ; (sequence VOID () ; () is empty option list 443 ; ((AI new_pc)) 444 ; (set AI new_pc (execute: AI (const 0)) #:quiet) 445 ; (set AI pc new_pc #:direct) 446 ; ) 447 ;) 448 449 ; FIXME: It might simplify things to separate the execute process from the 450 ; one that updates the PC. 451 453 ; Instruction fields. 454 ; 455 ; Attributes: 456 ; PCREL-ADDR: pc relative value (for reloc and disassembly purposes) 457 ; ABS-ADDR: absolute address (for reloc and disassembly purposes?) 458 ; RESERVED: bits are not used to decode insn, must be all 0 459 ; RELOC: there is a relocation associated with this field (experiment) 460 461 (define-attr 462 (for ifield operand) 463 (type boolean) 464 (name RELOC) 465 (comment "there is a reloc associated with this field (experiment)") 466 ) 467 468 (dnf f-op1 "op1" () 0 4) 469 (dnf f-op2 "op2" () 8 4) 470 (dnf f-cond "cond" () 4 4) 471 (dnf f-r1 "r1" () 4 4) 472 (dnf f-r2 "r2" () 12 4) 473 (df f-simm8 "simm8" () 8 8 INT #f #f) 474 (df f-simm16 "simm16" () 16 16 INT #f #f) 475 (dnf f-shift-op2 "shift op2" () 8 3) 476 (dnf f-uimm3 "uimm3" () 5 3) 477 (dnf f-uimm4 "uimm4" () 12 4) 478 (dnf f-uimm5 "uimm5" () 11 5) 479 (dnf f-uimm8 "uimm8" () 8 8) 480 (dnf f-uimm16 "uimm16" () 16 16) 481 (dnf f-uimm24 "uimm24" (ABS-ADDR RELOC) 8 24) 482 (dnf f-hi16 "high 16 bits" (SIGN-OPT) 16 16) 483 (df f-disp8 "disp8, slot unknown" (PCREL-ADDR RELOC) 8 8 INT 484 ((value pc) (sra WI (sub WI value (and WI pc (const -4))) (const 2))) 485 ((value pc) (add WI (sll WI value (const 2)) (and WI pc (const -4))))) 486 (df f-disp16 "disp16" (PCREL-ADDR RELOC) 16 16 INT 487 ((value pc) (sra WI (sub WI value pc) (const 2))) 488 ((value pc) (add WI (sll WI value (const 2)) pc))) 489 (df f-disp24 "disp24" (PCREL-ADDR RELOC) 8 24 INT 490 ((value pc) (sra WI (sub WI value pc) (const 2))) 491 ((value pc) (add WI (sll WI value (const 2)) pc))) 492 493 (dnf f-op23 "op2.3" () 9 3) 494 (dnf f-op3 "op3" () 14 2) 495 (dnf f-acc "acc" () 8 1) 496 (dnf f-accs "accs" () 12 2) 497 (dnf f-accd "accd" () 4 2) 498 (dnf f-bits67 "bits67" () 6 2) 499 (dnf f-bit4 "bit4" () 4 1) 500 (dnf f-bit14 "bit14" () 14 1) 501 502 (define-ifield (name f-imm1) (comment "1 bit immediate, 0->1 1->2") 503 (attrs) 504 (start 15) (length 1) 505 (encode (value pc) (sub WI value (const WI 1))) 506 (decode (value pc) (add WI value (const WI 1))) 507 ) 508 510 ; Enums. 511 512 ; insn-op1: bits 0-3 513 ; FIXME: should use die macro or some such 514 (define-normal-insn-enum insn-op1 "insn format enums" () OP1_ f-op1 515 ("0" "1" "2" "3" "4" "5" "6" "7" 516 "8" "9" "10" "11" "12" "13" "14" "15") 517 ) 518 519 ; insn-op2: bits 8-11 520 ; FIXME: should use die macro or some such 521 (define-normal-insn-enum insn-op2 "op2 enums" () OP2_ f-op2 522 ("0" "1" "2" "3" "4" "5" "6" "7" 523 "8" "9" "10" "11" "12" "13" "14" "15") 524 ) 525 527 ; Hardware pieces. 528 ; These entries list the elements of the raw hardware. 529 ; They're also used to provide tables and other elements of the assembly 530 ; language. 531 532 (dnh h-pc "program counter" (PC PROFILE) (pc) () () ()) 533 534 (dnh h-hi16 "high 16 bits" () 535 (immediate (UINT 16)) 536 () () () 537 ) 538 539 ; These two aren't technically needed. 540 ; They're here for illustration sake mostly. 541 ; Plus they cause the value to be stored in the extraction buffers to only 542 ; be 16 bits wide (vs 32 or 64). Whoopie ding. But it's fun. 543 (dnh h-slo16 "signed low 16 bits" () 544 (immediate (INT 16)) 545 () () () 546 ) 547 (dnh h-ulo16 "unsigned low 16 bits" () 548 (immediate (UINT 16)) 549 () () () 550 ) 551 552 (define-keyword 553 (name gr-names) 554 (print-name h-gr) 555 (prefix "") 556 (values (fp 13) (lr 14) (sp 15) 557 (r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6) (r7 7) 558 (r8 8) (r9 9) (r10 10) (r11 11) (r12 12) (r13 13) (r14 14) (r15 15)) 559 ) 560 561 (define-hardware 562 (name h-gr) 563 (comment "general registers") 564 (attrs PROFILE CACHE-ADDR) 565 (type register WI (16)) 566 (indices extern-keyword gr-names) 567 ) 568 569 (define-keyword 570 (name cr-names) 571 (print-name h-cr) 572 (prefix "") 573 (values (psw 0) (cbr 1) (spi 2) (spu 3) 574 (bpc 6) (bbpsw 8) (bbpc 14) (evb 5) 575 (cr0 0) (cr1 1) (cr2 2) (cr3 3) 576 (cr4 4) (cr5 5) (cr6 6) (cr7 7) 577 (cr8 8) (cr9 9) (cr10 10) (cr11 11) 578 (cr12 12) (cr13 13) (cr14 14) (cr15 15)) 579 ) 580 581 (define-hardware 582 (name h-cr) 583 (comment "control registers") 584 (type register UWI (16)) 585 (indices extern-keyword cr-names) 586 (get (index) (c-call UWI "@cpu@_h_cr_get_handler" index)) 587 (set (index newval) (c-call VOID "@cpu@_h_cr_set_handler" index newval)) 588 ) 589 590 ; The actual accumulator is only 56 bits. 591 ; The top 8 bits are sign extended from bit 8 (when counting msb = bit 0). 592 ; To simplify the accumulator instructions, no attempt is made to keep the 593 ; top 8 bits properly sign extended (currently there's no point since they 594 ; all ignore them). When the value is read it is properly sign extended 595 ; [in the `get' handler]. 596 (define-hardware 597 (name h-accum) 598 (comment "accumulator") 599 (type register DI) 600 (get () (c-call DI "@cpu@_h_accum_get_handler")) 601 (set (newval) (c-call VOID "@cpu@_h_accum_set_handler" newval)) 602 ) 603 604 ; FIXME: Revisit after sanitization can be removed. Remove h-accum. 605 (define-hardware 606 (name h-accums) 607 (comment "accumulators") 608 (attrs (MACH m32rx,m32r2)) 609 (type register DI (2)) 610 (indices keyword "" ((a0 0) (a1 1))) 611 ; get/set so a0 accesses are redirected to h-accum. 612 ; They're also so reads can properly sign extend the value. 613 ; FIXME: Needn't be a function call. 614 (get (index) (c-call DI "@cpu@_h_accums_get_handler" index)) 615 (set (index newval) (c-call VOID "@cpu@_h_accums_set_handler" index newval)) 616 ) 617 618 ; For condbit operand. FIXME: Need to allow spec of get/set of operands. 619 ; Having this separate from h-psw keeps the parts that use it simpler 620 ; [since they greatly outnumber those that use h-psw]. 621 (dsh h-cond "condition bit" () (register BI)) 622 623 ; The actual values of psw,bpsw,bbpsw are recorded here to allow access 624 ; to them as a unit. 625 (define-hardware 626 (name h-psw) 627 (comment "psw part of psw") 628 (type register UQI) 629 ; get/set to handle cond bit. 630 ; FIXME: missing: use's and clobber's 631 ; FIXME: remove c-call? 632 (get () (c-call UQI "@cpu@_h_psw_get_handler")) 633 (set (newval) (c-call VOID "@cpu@_h_psw_set_handler" newval)) 634 ) 635 (dsh h-bpsw "backup psw" () (register UQI)) 636 (dsh h-bbpsw "backup bpsw" () (register UQI)) 637 638 ; FIXME: Later make add get/set specs and support SMP. 639 (dsh h-lock "lock" () (register BI)) 640 642 ; Instruction Operands. 643 ; These entries provide a layer between the assembler and the raw hardware 644 ; description, and are used to refer to hardware elements in the semantic 645 ; code. Usually there's a bit of over-specification, but in more complicated 646 ; instruction sets there isn't. 647 648 ;; Print some operands take a hash prefix. 649 ;; ??? Why don't we also handle one when parsing? 650 651 (define-pmacro (duhpo x-name x-comment x-attrs x-type x-index) 652 (define-operand (name x-name) (comment x-comment) 653 (.splice attrs (.unsplice x-attrs)) 654 (type x-type) (index x-index) 655 (handlers (print "unsigned_with_hash_prefix"))) 656 ) 657 658 (define-pmacro (dshpo x-name x-comment x-attrs x-type x-index) 659 (define-operand (name x-name) (comment x-comment) 660 (.splice attrs (.unsplice x-attrs)) 661 (type x-type) (index x-index) 662 (handlers (print "signed_with_hash_prefix"))) 663 ) 664 665 ; ??? Convention says this should be o-sr, but then the insn definitions 666 ; should refer to o-sr which is clumsy. The "o-" could be implicit, but 667 ; then it should be implicit for all the symbols here, but then there would 668 ; be confusion between (f-)simm8 and (h-)simm8. 669 ; So for now the rule is exactly as it appears here. 670 671 (dnop sr "source register" () h-gr f-r2) 672 (dnop dr "destination register" () h-gr f-r1) 673 ;; The assembler relies upon the fact that dr and src1 are the same field. 674 ;; FIXME: Revisit. 675 (dnop src1 "source register 1" () h-gr f-r1) 676 (dnop src2 "source register 2" () h-gr f-r2) 677 (dnop scr "source control register" () h-cr f-r2) 678 (dnop dcr "destination control register" () h-cr f-r1) 679 680 (dshpo simm8 "8 bit signed immediate" () h-sint f-simm8) 681 (dshpo simm16 "16 bit signed immediate" () h-sint f-simm16) 682 (duhpo uimm3 "3 bit unsigned number" () h-uint f-uimm3) 683 (duhpo uimm4 "4 bit trap number" () h-uint f-uimm4) 684 (duhpo uimm5 "5 bit shift count" () h-uint f-uimm5) 685 (duhpo uimm8 "8 bit unsigned immediate" () h-uint f-uimm8) 686 (duhpo uimm16 "16 bit unsigned immediate" () h-uint f-uimm16) 687 688 (duhpo imm1 "1 bit immediate" ((MACH m32rx,m32r2)) h-uint f-imm1) 689 690 (dnop accd "accumulator destination register" ((MACH m32rx,m32r2)) h-accums f-accd) 691 (dnop accs "accumulator source register" ((MACH m32rx,m32r2)) h-accums f-accs) 692 (dnop acc "accumulator reg (d)" ((MACH m32rx,m32r2)) h-accums f-acc) 693 694 ; slo16,ulo16 are used in both with-hash-prefix/no-hash-prefix cases. 695 ; e.g. add3 r3,r3,#1 and ld r3,@(4,r4). We could use special handlers on 696 ; the operands themselves. 697 ; Instead we create a fake operand `hash'. The m32r is an illustration port, 698 ; so we often try out various ways of doing things. 699 700 (define-operand (name hash) (comment "# prefix") (attrs) 701 (type h-sint) ; doesn't really matter 702 (index f-nil) 703 (handlers (parse "hash") (print "hash")) 704 ) 705 706 ; For high(foo),shigh(foo). 707 (define-operand 708 (name hi16) 709 (comment "high 16 bit immediate, sign optional") 710 (attrs) 711 (type h-hi16) 712 (index f-hi16) 713 (handlers (parse "hi16")) 714 ) 715 716 ; For low(foo),sda(foo). 717 (define-operand 718 (name slo16) 719 (comment "16 bit signed immediate, for low()") 720 (attrs) 721 (type h-slo16) 722 (index f-simm16) 723 (handlers (parse "slo16")) 724 ) 725 726 ; For low(foo). 727 (define-operand 728 (name ulo16) 729 (comment "16 bit unsigned immediate, for low()") 730 (attrs) 731 (type h-ulo16) 732 (index f-uimm16) 733 (handlers (parse "ulo16")) 734 ) 735 736 (dnop uimm24 "24 bit address" () h-addr f-uimm24) 737 738 (define-operand 739 (name disp8) 740 (comment "8 bit displacement") 741 (attrs RELAX) 742 (type h-iaddr) 743 (index f-disp8) 744 ; ??? Early experiments had insert/extract fields here. 745 ; Moving these to f-disp8 made things cleaner, but may wish to re-introduce 746 ; fields here to handle more complicated cases. 747 ) 748 749 (dnop disp16 "16 bit displacement" () h-iaddr f-disp16) 750 (dnop disp24 "24 bit displacement" (RELAX) h-iaddr f-disp24) 751 752 ; These hardware elements are refered to frequently. 753 754 (dnop condbit "condition bit" (SEM-ONLY) h-cond f-nil) 755 (dnop accum "accumulator" (SEM-ONLY) h-accum f-nil) 756 758 ; Instruction definitions. 759 ; 760 ; Notes while wip: 761 ; - dni is a cover macro to the real "this is an instruction" keyword. 762 ; The syntax of the real one is yet to be determined. 763 ; At the lowest level (i.e. the "real" one) it will probably take a variable 764 ; list of arguments where each argument [perhaps after the standard three of 765 ; name, comment, attrs] is "(keyword arg-to-keyword)". This syntax is simple 766 ; and yet completely upward extensible. And given the macro facility, one 767 ; needn't code at that low a level so even though it'll be more verbose than 768 ; necessary it won't matter. This same reasoning can be applied to most 769 ; types of entries in this file. 770 771 ; M32R specific instruction attributes: 772 773 ; FILL-SLOT: Need next insn to begin on 32 bit boundary. 774 ; (A "slot" as used here is a 32 bit quantity that can either be filled with 775 ; one 32 bit insn or two 16 bit insns which go in the "left bin" and "right 776 ; bin" where the left bin is the one with a lower address). 777 778 (define-attr 779 (for insn) 780 (type boolean) 781 (name FILL-SLOT) 782 (comment "fill right bin with `nop' if insn is in left bin") 783 ) 784 785 (define-attr 786 (for insn) 787 (type boolean) 788 (name SPECIAL) 789 (comment "non-public m32rx insn") 790 ) 791 792 (define-attr 793 (for insn) 794 (type boolean) 795 (name SPECIAL_M32R) 796 (comment "non-public m32r insn") 797 ) 798 799 (define-attr 800 (for insn) 801 (type boolean) 802 (name SPECIAL_FLOAT) 803 (comment "floating point insn") 804 ) 805 806 ; IDOC attribute for instruction documentation. 807 808 (define-attr 809 (for insn) 810 (type enum) 811 (name IDOC) 812 (comment "insn kind for documentation") 813 (attrs META) 814 (values 815 (MEM - () "Memory") 816 (ALU - () "ALU") 817 (BR - () "Branch") 818 (ACCUM - () "Accumulator") 819 (MAC - () "Multiply/Accumulate") 820 (MISC - () "Miscellaneous") 821 ) 822 ) 823 824 (define-pmacro (bin-op mnemonic op2-op sem-op imm-prefix imm) 825 (begin 826 (dni mnemonic 827 (.str mnemonic " reg/reg") 828 ((PIPE OS) (IDOC ALU)) 829 (.str mnemonic " $dr,$sr") 830 (+ OP1_0 op2-op dr sr) 831 (set dr (sem-op dr sr)) 832 () 833 ) 834 (dni (.sym mnemonic "3") 835 (.str mnemonic " reg/" imm) 836 ((IDOC ALU)) 837 (.str mnemonic "3 $dr,$sr," imm-prefix "$" imm) 838 (+ OP1_8 op2-op dr sr imm) 839 (set dr (sem-op sr imm)) 840 () 841 ) 842 ) 843 ) 844 (bin-op add OP2_10 add "$hash" slo16) 845 ; sub isn't present because sub3 doesn't exist. 846 (bin-op and OP2_12 and "" uimm16) 847 (bin-op or OP2_14 or "$hash" ulo16) 848 (bin-op xor OP2_13 xor "" uimm16) 849 850 (dni addi "addi" 851 ((PIPE OS) (IDOC ALU)) 852 ;#.(string-append "addi " "$dr,$simm8") ; #. experiment 853 "addi $dr,$simm8" 854 (+ OP1_4 dr simm8) 855 (set dr (add dr simm8)) 856 ((m32r/d (unit u-exec)) 857 (m32rx (unit u-exec)) 858 (m32r2 (unit u-exec))) 859 ) 860 861 (dni addv "addv" 862 ((PIPE OS) (IDOC ALU)) 863 "addv $dr,$sr" 864 (+ OP1_0 OP2_8 dr sr) 865 (parallel () 866 (set dr (add dr sr)) 867 (set condbit (add-oflag dr sr (const 0)))) 868 () 869 ) 870 871 (dni addv3 "addv3" 872 ((IDOC ALU)) 873 "addv3 $dr,$sr,$simm16" 874 (+ OP1_8 OP2_8 dr sr simm16) 875 (parallel () 876 (set dr (add sr simm16)) 877 (set condbit (add-oflag sr simm16 (const 0)))) 878 () 879 ) 880 881 (dni addx "addx" 882 ((PIPE OS) (IDOC ALU)) 883 "addx $dr,$sr" 884 (+ OP1_0 OP2_9 dr sr) 885 (parallel () 886 (set dr (addc dr sr condbit)) 887 (set condbit (add-cflag dr sr condbit))) 888 () 889 ) 890 891 (dni bc8 "bc with 8 bit displacement" 892 (COND-CTI (PIPE O) (IDOC BR)) 893 "bc.s $disp8" 894 (+ OP1_7 (f-r1 12) disp8) 895 (if condbit (set pc disp8)) 896 ((m32r/d (unit u-cti)) 897 (m32rx (unit u-cti)) 898 (m32r2 (unit u-cti))) 899 ) 900 901 (dnmi bc8r "relaxable bc8" 902 (COND-CTI RELAXABLE (PIPE O) (IDOC BR)) 903 "bc $disp8" 904 (emit bc8 disp8) 905 ) 906 907 (dni bc24 "bc with 24 bit displacement" 908 (COND-CTI (IDOC BR)) 909 "bc.l $disp24" 910 (+ OP1_15 (f-r1 12) disp24) 911 (if condbit (set pc disp24)) 912 ((m32r/d (unit u-cti)) 913 (m32rx (unit u-cti)) 914 (m32r2 (unit u-cti))) 915 ) 916 917 (dnmi bc24r "relaxable bc24" 918 (COND-CTI RELAXED (IDOC BR)) 919 "bc $disp24" 920 (emit bc24 disp24) 921 ) 922 923 (dni beq "beq" 924 (COND-CTI (IDOC BR)) 925 "beq $src1,$src2,$disp16" 926 (+ OP1_11 OP2_0 src1 src2 disp16) 927 (if (eq src1 src2) (set pc disp16)) 928 ((m32r/d (unit u-cti) (unit u-cmp (cycles 0))) 929 (m32rx (unit u-cti) (unit u-cmp (cycles 0))) 930 (m32r2 (unit u-cti) (unit u-cmp (cycles 0)))) 931 ) 932 933 (define-pmacro (cbranch sym comment op2-op comp-op) 934 (dni sym comment (COND-CTI (IDOC BR)) 935 (.str sym " $src2,$disp16") 936 (+ OP1_11 op2-op (f-r1 0) src2 disp16) 937 (if (comp-op src2 (const WI 0)) (set pc disp16)) 938 ((m32r/d (unit u-cti) (unit u-cmp (cycles 0))) 939 (m32rx (unit u-cti) (unit u-cmp (cycles 0))) 940 (m32r2 (unit u-cti) (unit u-cmp (cycles 0)))) 941 ) 942 ) 943 (cbranch beqz "beqz" OP2_8 eq) 944 (cbranch bgez "bgez" OP2_11 ge) 945 (cbranch bgtz "bgtz" OP2_13 gt) 946 (cbranch blez "blez" OP2_12 le) 947 (cbranch bltz "bltz" OP2_10 lt) 948 (cbranch bnez "bnez" OP2_9 ne) 949 950 (dni bl8 "bl with 8 bit displacement" 951 (UNCOND-CTI FILL-SLOT (PIPE O) (IDOC BR)) 952 "bl.s $disp8" 953 (+ OP1_7 (f-r1 14) disp8) 954 (sequence () 955 (set (reg h-gr 14) 956 (add (and pc (const -4)) (const 4))) 957 (set pc disp8)) 958 ((m32r/d (unit u-cti)) 959 (m32rx (unit u-cti)) 960 (m32r2 (unit u-cti))) 961 ) 962 963 (dnmi bl8r "relaxable bl8" 964 (UNCOND-CTI FILL-SLOT RELAXABLE (PIPE O) (IDOC BR)) 965 "bl $disp8" 966 (emit bl8 disp8) 967 ) 968 969 (dni bl24 "bl with 24 bit displacement" 970 (UNCOND-CTI (IDOC BR)) 971 "bl.l $disp24" 972 (+ OP1_15 (f-r1 14) disp24) 973 (sequence () 974 (set (reg h-gr 14) (add pc (const 4))) 975 (set pc disp24)) 976 ((m32r/d (unit u-cti)) 977 (m32rx (unit u-cti)) 978 (m32r2 (unit u-cti))) 979 ) 980 981 (dnmi bl24r "relaxable bl24" 982 (UNCOND-CTI RELAXED (IDOC BR)) 983 "bl $disp24" 984 (emit bl24 disp24) 985 ) 986 987 (dni bcl8 "bcl with 8 bit displacement" 988 (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) (IDOC BR)) 989 "bcl.s $disp8" 990 (+ OP1_7 (f-r1 8) disp8) 991 (if condbit 992 (sequence () 993 (set (reg h-gr 14) 994 (add (and pc (const -4)) 995 (const 4))) 996 (set pc disp8))) 997 ((m32rx (unit u-cti)) 998 (m32r2 (unit u-cti))) 999 ) 1000 1001 (dnmi bcl8r "relaxable bcl8" 1002 (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) RELAXABLE (IDOC BR)) 1003 "bcl $disp8" 1004 (emit bcl8 disp8) 1005 ) 1006 1007 (dni bcl24 "bcl with 24 bit displacement" 1008 (COND-CTI (MACH m32rx,m32r2) (IDOC BR)) 1009 "bcl.l $disp24" 1010 (+ OP1_15 (f-r1 8) disp24) 1011 (if condbit 1012 (sequence () 1013 (set (reg h-gr 14) (add pc (const 4))) 1014 (set pc disp24))) 1015 ((m32rx (unit u-cti)) 1016 (m32r2 (unit u-cti))) 1017 ) 1018 1019 (dnmi bcl24r "relaxable bcl24" 1020 (COND-CTI (MACH m32rx,m32r2) RELAXED (IDOC BR)) 1021 "bcl $disp24" 1022 (emit bcl24 disp24) 1023 ) 1024 1025 (dni bnc8 "bnc with 8 bit displacement" 1026 (COND-CTI (PIPE O) (IDOC BR)) 1027 "bnc.s $disp8" 1028 (+ OP1_7 (f-r1 13) disp8) 1029 (if (not condbit) (set pc disp8)) 1030 ((m32r/d (unit u-cti)) 1031 (m32rx (unit u-cti)) 1032 (m32r2 (unit u-cti))) 1033 ) 1034 1035 (dnmi bnc8r "relaxable bnc8" 1036 (COND-CTI RELAXABLE (PIPE O) (IDOC BR)) 1037 "bnc $disp8" 1038 (emit bnc8 disp8) 1039 ) 1040 1041 (dni bnc24 "bnc with 24 bit displacement" 1042 (COND-CTI (IDOC BR)) 1043 "bnc.l $disp24" 1044 (+ OP1_15 (f-r1 13) disp24) 1045 (if (not condbit) (set pc disp24)) 1046 ((m32r/d (unit u-cti)) 1047 (m32rx (unit u-cti)) 1048 (m32r2 (unit u-cti))) 1049 ) 1050 1051 (dnmi bnc24r "relaxable bnc24" 1052 (COND-CTI RELAXED (IDOC BR)) 1053 "bnc $disp24" 1054 (emit bnc24 disp24) 1055 ) 1056 1057 (dni bne "bne" 1058 (COND-CTI (IDOC BR)) 1059 "bne $src1,$src2,$disp16" 1060 (+ OP1_11 OP2_1 src1 src2 disp16) 1061 (if (ne src1 src2) (set pc disp16)) 1062 ((m32r/d (unit u-cti) (unit u-cmp (cycles 0))) 1063 (m32rx (unit u-cti) (unit u-cmp (cycles 0))) 1064 (m32r2 (unit u-cti) (unit u-cmp (cycles 0)))) 1065 ) 1066 1067 (dni bra8 "bra with 8 bit displacement" 1068 (UNCOND-CTI FILL-SLOT (PIPE O) (IDOC BR)) 1069 "bra.s $disp8" 1070 (+ OP1_7 (f-r1 15) disp8) 1071 (set pc disp8) 1072 ((m32r/d (unit u-cti)) 1073 (m32rx (unit u-cti)) 1074 (m32r2 (unit u-cti))) 1075 ) 1076 1077 (dnmi bra8r "relaxable bra8" 1078 (UNCOND-CTI FILL-SLOT RELAXABLE (PIPE O) (IDOC BR)) 1079 "bra $disp8" 1080 (emit bra8 disp8) 1081 ) 1082 1083 (dni bra24 "bra with 24 displacement" 1084 (UNCOND-CTI (IDOC BR)) 1085 "bra.l $disp24" 1086 (+ OP1_15 (f-r1 15) disp24) 1087 (set pc disp24) 1088 ((m32r/d (unit u-cti)) 1089 (m32rx (unit u-cti)) 1090 (m32r2 (unit u-cti))) 1091 ) 1092 1093 (dnmi bra24r "relaxable bra24" 1094 (UNCOND-CTI RELAXED (IDOC BR)) 1095 "bra $disp24" 1096 (emit bra24 disp24) 1097 ) 1098 1099 (dni bncl8 "bncl with 8 bit displacement" 1100 (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) (IDOC BR)) 1101 "bncl.s $disp8" 1102 (+ OP1_7 (f-r1 9) disp8) 1103 (if (not condbit) 1104 (sequence () 1105 (set (reg h-gr 14) 1106 (add (and pc (const -4)) 1107 (const 4))) 1108 (set pc disp8))) 1109 ((m32rx (unit u-cti)) 1110 (m32r2 (unit u-cti))) 1111 ) 1112 1113 (dnmi bncl8r "relaxable bncl8" 1114 (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) RELAXABLE (IDOC BR)) 1115 "bncl $disp8" 1116 (emit bncl8 disp8) 1117 ) 1118 1119 (dni bncl24 "bncl with 24 bit displacement" 1120 (COND-CTI (MACH m32rx,m32r2) (IDOC BR)) 1121 "bncl.l $disp24" 1122 (+ OP1_15 (f-r1 9) disp24) 1123 (if (not condbit) 1124 (sequence () 1125 (set (reg h-gr 14) (add pc (const 4))) 1126 (set pc disp24))) 1127 ((m32rx (unit u-cti)) 1128 (m32r2 (unit u-cti))) 1129 ) 1130 1131 (dnmi bncl24r "relaxable bncl24" 1132 (COND-CTI (MACH m32rx,m32r2) RELAXED (IDOC BR)) 1133 "bncl $disp24" 1134 (emit bncl24 disp24) 1135 ) 1136 1137 (dni cmp "cmp" 1138 ((PIPE OS) (IDOC ALU)) 1139 "cmp $src1,$src2" 1140 (+ OP1_0 OP2_4 src1 src2) 1141 (set condbit (lt src1 src2)) 1142 ((m32r/d (unit u-cmp)) 1143 (m32rx (unit u-cmp)) 1144 (m32r2 (unit u-cmp))) 1145 ) 1146 1147 (dni cmpi "cmpi" 1148 ((IDOC ALU)) 1149 "cmpi $src2,$simm16" 1150 (+ OP1_8 (f-r1 0) OP2_4 src2 simm16) 1151 (set condbit (lt src2 simm16)) 1152 ((m32r/d (unit u-cmp)) 1153 (m32rx (unit u-cmp)) 1154 (m32r2 (unit u-cmp))) 1155 ) 1156 1157 (dni cmpu "cmpu" 1158 ((PIPE OS) (IDOC ALU)) 1159 "cmpu $src1,$src2" 1160 (+ OP1_0 OP2_5 src1 src2) 1161 (set condbit (ltu src1 src2)) 1162 ((m32r/d (unit u-cmp)) 1163 (m32rx (unit u-cmp)) 1164 (m32r2 (unit u-cmp))) 1165 ) 1166 1167 (dni cmpui "cmpui" 1168 ((IDOC ALU)) 1169 "cmpui $src2,$simm16" 1170 (+ OP1_8 (f-r1 0) OP2_5 src2 simm16) 1171 (set condbit (ltu src2 simm16)) 1172 ((m32r/d (unit u-cmp)) 1173 (m32rx (unit u-cmp)) 1174 (m32r2 (unit u-cmp))) 1175 ) 1176 1177 (dni cmpeq "cmpeq" 1178 ((MACH m32rx,m32r2) (PIPE OS) (IDOC ALU)) 1179 "cmpeq $src1,$src2" 1180 (+ OP1_0 OP2_6 src1 src2) 1181 (set condbit (eq src1 src2)) 1182 ((m32rx (unit u-cmp)) 1183 (m32r2 (unit u-cmp))) 1184 ) 1185 1186 (dni cmpz "cmpz" 1187 ((MACH m32rx,m32r2) (PIPE OS) (IDOC ALU)) 1188 "cmpz $src2" 1189 (+ OP1_0 OP2_7 (f-r1 0) src2) 1190 (set condbit (eq src2 (const 0))) 1191 ((m32rx (unit u-cmp)) 1192 (m32r2 (unit u-cmp))) 1193 ) 1194 1195 (dni div "div" 1196 ((IDOC ALU)) 1197 "div $dr,$sr" 1198 (+ OP1_9 OP2_0 dr sr (f-simm16 0)) 1199 (if (ne sr (const 0)) (set dr (div dr sr))) 1200 ((m32r/d (unit u-exec (cycles 37))) 1201 (m32rx (unit u-exec (cycles 37))) 1202 (m32r2 (unit u-exec (cycles 37)))) 1203 ) 1204 1205 (dni divu "divu" 1206 ((IDOC ALU)) 1207 "divu $dr,$sr" 1208 (+ OP1_9 OP2_1 dr sr (f-simm16 0)) 1209 (if (ne sr (const 0)) (set dr (udiv dr sr))) 1210 ((m32r/d (unit u-exec (cycles 37))) 1211 (m32rx (unit u-exec (cycles 37))) 1212 (m32r2 (unit u-exec (cycles 37)))) 1213 ) 1214 1215 (dni rem "rem" 1216 ((IDOC ALU)) 1217 "rem $dr,$sr" 1218 (+ OP1_9 OP2_2 dr sr (f-simm16 0)) 1219 ; FIXME: Check rounding direction. 1220 (if (ne sr (const 0)) (set dr (mod dr sr))) 1221 ((m32r/d (unit u-exec (cycles 37))) 1222 (m32rx (unit u-exec (cycles 37))) 1223 (m32r2 (unit u-exec (cycles 37)))) 1224 ) 1225 1226 (dni remu "remu" 1227 ((IDOC ALU)) 1228 "remu $dr,$sr" 1229 (+ OP1_9 OP2_3 dr sr (f-simm16 0)) 1230 ; FIXME: Check rounding direction. 1231 (if (ne sr (const 0)) (set dr (umod dr sr))) 1232 ((m32r/d (unit u-exec (cycles 37))) 1233 (m32rx (unit u-exec (cycles 37))) 1234 (m32r2 (unit u-exec (cycles 37)))) 1235 ) 1236 1237 (dni remh "remh" 1238 ((MACH m32r2)) 1239 "remh $dr,$sr" 1240 (+ OP1_9 OP2_2 dr sr (f-simm16 #x10)) 1241 ; FIXME: Check rounding direction. 1242 (if (ne sr (const 0)) (set dr (mod (ext WI (trunc HI dr)) sr))) 1243 ((m32r2 (unit u-exec (cycles 21)))) 1244 ) 1245 1246 (dni remuh "remuh" 1247 ((MACH m32r2)) 1248 "remuh $dr,$sr" 1249 (+ OP1_9 OP2_3 dr sr (f-simm16 #x10)) 1250 ; FIXME: Check rounding direction. 1251 (if (ne sr (const 0)) (set dr (umod dr sr))) 1252 ((m32r2 (unit u-exec (cycles 21)))) 1253 ) 1254 1255 (dni remb "remb" 1256 ((MACH m32r2)) 1257 "remb $dr,$sr" 1258 (+ OP1_9 OP2_2 dr sr (f-simm16 #x18)) 1259 ; FIXME: Check rounding direction. 1260 (if (ne sr (const 0)) (set dr (mod (ext WI (trunc BI dr)) sr))) 1261 ((m32r2 (unit u-exec (cycles 21)))) 1262 ) 1263 1264 (dni remub "remub" 1265 ((MACH m32r2)) 1266 "remub $dr,$sr" 1267 (+ OP1_9 OP2_3 dr sr (f-simm16 #x18)) 1268 ; FIXME: Check rounding direction. 1269 (if (ne sr (const 0)) (set dr (umod dr sr))) 1270 ((m32r2 (unit u-exec (cycles 21)))) 1271 ) 1272 1273 (dni divuh "divuh" 1274 ((MACH m32r2)) 1275 "divuh $dr,$sr" 1276 (+ OP1_9 OP2_1 dr sr (f-simm16 #x10)) 1277 (if (ne sr (const 0)) (set dr (udiv dr sr))) 1278 ((m32r2 (unit u-exec (cycles 21)))) 1279 ) 1280 1281 (dni divb "divb" 1282 ((MACH m32r2)) 1283 "divb $dr,$sr" 1284 (+ OP1_9 OP2_0 dr sr (f-simm16 #x18)) 1285 (if (ne sr (const 0)) (set dr (div (ext WI (trunc BI dr)) sr))) 1286 ((m32r2 (unit u-exec (cycles 21)))) 1287 ) 1288 1289 (dni divub "divub" 1290 ((MACH m32r2)) 1291 "divub $dr,$sr" 1292 (+ OP1_9 OP2_1 dr sr (f-simm16 #x18)) 1293 (if (ne sr (const 0)) (set dr (udiv dr sr))) 1294 ((m32r2 (unit u-exec (cycles 21)))) 1295 ) 1296 1297 (dni divh "divh" 1298 ((MACH m32rx,m32r2) (IDOC ALU)) 1299 "divh $dr,$sr" 1300 (+ OP1_9 OP2_0 dr sr (f-simm16 #x10)) 1301 (if (ne sr (const 0)) (set dr (div (ext WI (trunc HI dr)) sr))) 1302 ((m32rx (unit u-exec (cycles 21))) 1303 (m32r2 (unit u-exec (cycles 21)))) 1304 ) 1305 1306 (dni jc "jc" 1307 (COND-CTI (MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR)) 1308 "jc $sr" 1309 (+ OP1_1 (f-r1 12) OP2_12 sr) 1310 (if condbit (set pc (and sr (const -4)))) 1311 ((m32rx (unit u-cti)) 1312 (m32r2 (unit u-cti))) 1313 ) 1314 1315 (dni jnc "jnc" 1316 (COND-CTI (MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR)) 1317 "jnc $sr" 1318 (+ OP1_1 (f-r1 13) OP2_12 sr) 1319 (if (not condbit) (set pc (and sr (const -4)))) 1320 ((m32rx (unit u-cti)) 1321 (m32r2 (unit u-cti))) 1322 ) 1323 1324 (dni jl "jl" 1325 (UNCOND-CTI FILL-SLOT (PIPE O) (IDOC BR)) 1326 "jl $sr" 1327 (+ OP1_1 (f-r1 14) OP2_12 sr) 1328 (parallel () 1329 (set (reg h-gr 14) 1330 (add (and pc (const -4)) (const 4))) 1331 (set pc (and sr (const -4)))) 1332 ((m32r/d (unit u-cti)) 1333 (m32rx (unit u-cti)) 1334 (m32r2 (unit u-cti))) 1335 ) 1336 1337 (dni jmp "jmp" 1338 (UNCOND-CTI (PIPE O) (IDOC BR)) 1339 "jmp $sr" 1340 (+ OP1_1 (f-r1 15) OP2_12 sr) 1341 (set pc (and sr (const -4))) 1342 ; The above works now so this kludge has been commented out. 1343 ; It's kept around because the f-r1 reference in the semantic part 1344 ; should work. 1345 ; FIXME: kludge, instruction decoding not finished. 1346 ; But this should work, so that's another FIXME. 1347 ;(sequence VOID (if VOID (eq SI f-r1 (const SI 14)) 1348 ; FIXME: abuf->insn should be a macro of some sort. 1349 ;(sequence VOID 1350 ; (if VOID (eq SI (c-code SI "((abuf->insn >> 8) & 15)") 1351 ; (const SI 14)) 1352 ; (set WI (reg WI h-gr 14) 1353 ; (add WI (and WI pc (const WI -4)) (const WI 4)))) 1354 ; (set WI pc sr)) 1355 ((m32r/d (unit u-cti)) 1356 (m32rx (unit u-cti)) 1357 (m32r2 (unit u-cti))) 1358 ) 1359 1360 (define-pmacro (no-ext-expr mode expr) expr) 1361 (define-pmacro (ext-expr mode expr) (ext mode expr)) 1362 (define-pmacro (zext-expr mode expr) (zext mode expr)) 1363 1364 (define-pmacro (load-op suffix op2-op mode ext-op) 1365 (begin 1366 (dni (.sym ld suffix) (.str "ld" suffix) 1367 ((PIPE O) (IDOC MEM)) 1368 (.str "ld" suffix " $dr,@$sr") 1369 (+ OP1_2 op2-op dr sr) 1370 (set dr (ext-op WI (mem mode sr))) 1371 ((m32r/d (unit u-load)) 1372 (m32rx (unit u-load)) 1373 (m32r2 (unit u-load))) 1374 ) 1375 (dnmi (.sym ld suffix "-2") (.str "ld" suffix "-2") 1376 (NO-DIS (PIPE O) (IDOC MEM)) 1377 (.str "ld" suffix " $dr,@($sr)") 1378 (emit (.sym ld suffix) dr sr)) 1379 (dni (.sym ld suffix -d) (.str "ld" suffix "-d") 1380 ((IDOC MEM)) 1381 (.str "ld" suffix " $dr,@($slo16,$sr)") 1382 (+ OP1_10 op2-op dr sr slo16) 1383 (set dr (ext-op WI (mem mode (add sr slo16)))) 1384 ((m32r/d (unit u-load (cycles 2))) 1385 (m32rx (unit u-load (cycles 2))) 1386 (m32r2 (unit u-load (cycles 2)))) 1387 ) 1388 (dnmi (.sym ld suffix -d2) (.str "ld" suffix "-d2") 1389 (NO-DIS (IDOC MEM)) 1390 (.str "ld" suffix " $dr,@($sr,$slo16)") 1391 (emit (.sym ld suffix -d) dr sr slo16)) 1392 ) 1393 ) 1394 (load-op "" OP2_12 WI no-ext-expr) 1395 (load-op b OP2_8 QI ext-expr) 1396 (load-op h OP2_10 HI ext-expr) 1397 (load-op ub OP2_9 QI zext-expr) 1398 (load-op uh OP2_11 HI zext-expr) 1399 1400 (dni ld-plus "ld+" 1401 ((PIPE O) (IDOC MEM)) 1402 "ld $dr,@$sr+" 1403 (+ OP1_2 dr OP2_14 sr) 1404 (parallel () 1405 ; wip: memory addresses in profiling support 1406 ;(set dr (name ld-mem (mem WI sr))) 1407 (set dr (mem WI sr)) 1408 (set sr (add sr (const 4)))) 1409 ; Note: `pred' is the constraint. Also useful here is (ref name) 1410 ; and returns true if operand <name> was referenced 1411 ; (where "referenced" means _read_ if input operand and _written_ if 1412 ; output operand). 1413 ; args to unit are "unit-name (name1 value1) ..." 1414 ; - cycles(done),issue,pred are also specified this way 1415 ; - if unspecified, default is used 1416 ; - for ins/outs, extra arg is passed that says what was specified 1417 ; - this is AND'd with `written' for outs 1418 ((m32r/d (unit u-load (pred (const 1))) 1419 (unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1)))) 1420 (m32rx (unit u-load) 1421 (unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1)))) 1422 (m32r2 (unit u-load) 1423 (unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1)))) 1424 ) 1425 ) 1426 1427 (dnmi pop "pop" 1428 ((PIPE O) (IDOC MEM)) 1429 "pop $dr" 1430 (emit ld-plus dr (sr 15)) ; "ld %0,@sp+" 1431 ) 1432 1433 (dni ld24 "ld24" 1434 ((IDOC MEM)) 1435 "ld24 $dr,$uimm24" 1436 (+ OP1_14 dr uimm24) 1437 (set dr uimm24) 1438 () 1439 ) 1440 1441 ; ldi8 appears before ldi16 so we try the shorter version first 1442 1443 (dni ldi8 "ldi8" 1444 ((PIPE OS) (IDOC ALU)) 1445 "ldi8 $dr,$simm8" 1446 (+ OP1_6 dr simm8) 1447 (set dr simm8) 1448 () 1449 ) 1450 1451 (dnmi ldi8a "ldi8 alias" 1452 ((PIPE OS) (IDOC ALU)) 1453 "ldi $dr,$simm8" 1454 (emit ldi8 dr simm8) 1455 ) 1456 1457 (dni ldi16 "ldi16" 1458 ((IDOC ALU)) 1459 "ldi16 $dr,$hash$slo16" 1460 (+ OP1_9 OP2_15 (f-r2 0) dr slo16) 1461 (set dr slo16) 1462 () 1463 ) 1464 1465 (dnmi ldi16a "ldi16 alias" 1466 ((IDOC ALU)) 1467 "ldi $dr,$hash$slo16" 1468 (emit ldi16 dr slo16) 1469 ) 1470 1471 (dni lock "lock" 1472 ((PIPE O) (IDOC MISC)) 1473 "lock $dr,@$sr" 1474 (+ OP1_2 OP2_13 dr sr) 1475 (sequence () 1476 (set (reg h-lock) (const BI 1)) 1477 (set dr (mem WI sr))) 1478 ((m32r/d (unit u-load)) 1479 (m32rx (unit u-load)) 1480 (m32r2 (unit u-load))) 1481 ) 1482 1483 (dni machi "machi" 1484 ( 1485 ; (MACH m32r) is a temporary hack. This insn collides with machi-a 1486 ; in the simulator so disable it for m32rx. 1487 (MACH m32r) (PIPE S) (IDOC MAC) 1488 ) 1489 "machi $src1,$src2" 1490 (+ OP1_3 OP2_4 src1 src2) 1491 ; FIXME: TRACE_RESULT will print the wrong thing since we 1492 ; alter one of the arguments. 1493 (set accum 1494 (sra DI 1495 (sll DI 1496 (add DI 1497 accum 1498 (mul DI 1499 (ext DI (and WI src1 (const #xffff0000))) 1500 (ext DI (trunc HI (sra WI src2 (const 16)))))) 1501 (const 8)) 1502 (const 8))) 1503 ((m32r/d (unit u-mac))) 1504 ) 1505 1506 (dni machi-a "machi-a" 1507 ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) 1508 "machi $src1,$src2,$acc" 1509 (+ OP1_3 src1 acc (f-op23 4) src2) 1510 (set acc 1511 (sra DI 1512 (sll DI 1513 (add DI 1514 acc 1515 (mul DI 1516 (ext DI (and WI src1 (const #xffff0000))) 1517 (ext DI (trunc HI (sra WI src2 (const 16)))))) 1518 (const 8)) 1519 (const 8))) 1520 ((m32rx (unit u-mac)) 1521 (m32r2 (unit u-mac))) 1522 ) 1523 1524 (dni maclo "maclo" 1525 ((MACH m32r) (PIPE S) (IDOC MAC)) 1526 "maclo $src1,$src2" 1527 (+ OP1_3 OP2_5 src1 src2) 1528 (set accum 1529 (sra DI 1530 (sll DI 1531 (add DI 1532 accum 1533 (mul DI 1534 (ext DI (sll WI src1 (const 16))) 1535 (ext DI (trunc HI src2)))) 1536 (const 8)) 1537 (const 8))) 1538 ((m32r/d (unit u-mac))) 1539 ) 1540 1541 (dni maclo-a "maclo-a" 1542 ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) 1543 "maclo $src1,$src2,$acc" 1544 (+ OP1_3 src1 acc (f-op23 5) src2) 1545 (set acc 1546 (sra DI 1547 (sll DI 1548 (add DI 1549 acc 1550 (mul DI 1551 (ext DI (sll WI src1 (const 16))) 1552 (ext DI (trunc HI src2)))) 1553 (const 8)) 1554 (const 8))) 1555 ((m32rx (unit u-mac)) 1556 (m32r2 (unit u-mac))) 1557 ) 1558 1559 (dni macwhi "macwhi" 1560 ((MACH m32r) (PIPE S) (IDOC MAC)) 1561 "macwhi $src1,$src2" 1562 (+ OP1_3 OP2_6 src1 src2) 1563 (set accum 1564 (sra DI 1565 (sll DI 1566 (add DI 1567 accum 1568 (mul DI 1569 (ext DI src1) 1570 (ext DI (trunc HI (sra WI src2 (const 16)))))) 1571 (const 8)) 1572 (const 8))) 1573 ((m32r/d (unit u-mac))) 1574 ) 1575 1576 (dni macwhi-a "macwhi-a" 1577 ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC MAC)) 1578 "macwhi $src1,$src2,$acc" 1579 (+ OP1_3 src1 acc (f-op23 6) src2) 1580 ; Note that this doesn't do the sign extension, which is correct. 1581 (set acc 1582 (add acc 1583 (mul (ext DI src1) 1584 (ext DI (trunc HI (sra src2 (const 16))))))) 1585 ((m32rx (unit u-mac)) 1586 (m32r2 (unit u-mac))) 1587 ) 1588 1589 (dni macwlo "macwlo" 1590 ((MACH m32r) (PIPE S) (IDOC MAC)) 1591 "macwlo $src1,$src2" 1592 (+ OP1_3 OP2_7 src1 src2) 1593 (set accum 1594 (sra DI 1595 (sll DI 1596 (add DI 1597 accum 1598 (mul DI 1599 (ext DI src1) 1600 (ext DI (trunc HI src2)))) 1601 (const 8)) 1602 (const 8))) 1603 ((m32r/d (unit u-mac))) 1604 ) 1605 1606 (dni macwlo-a "macwlo-a" 1607 ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC MAC)) 1608 "macwlo $src1,$src2,$acc" 1609 (+ OP1_3 src1 acc (f-op23 7) src2) 1610 ; Note that this doesn't do the sign extension, which is correct. 1611 (set acc 1612 (add acc 1613 (mul (ext DI src1) 1614 (ext DI (trunc HI src2))))) 1615 ((m32rx (unit u-mac)) 1616 (m32r2 (unit u-mac))) 1617 ) 1618 1619 (dni mul "mul" 1620 ((PIPE S) (IDOC ALU)) 1621 "mul $dr,$sr" 1622 (+ OP1_1 OP2_6 dr sr) 1623 (set dr (mul dr sr)) 1624 ((m32r/d (unit u-exec (cycles 4))) 1625 (m32rx (unit u-exec (cycles 4))) 1626 (m32r2 (unit u-exec (cycles 4)))) 1627 ) 1628 1629 (dni mulhi "mulhi" 1630 ((MACH m32r) (PIPE S) (IDOC ACCUM)) 1631 "mulhi $src1,$src2" 1632 (+ OP1_3 OP2_0 src1 src2) 1633 (set accum 1634 (sra DI 1635 (sll DI 1636 (mul DI 1637 (ext DI (and WI src1 (const #xffff0000))) 1638 (ext DI (trunc HI (sra WI src2 (const 16))))) 1639 (const 16)) 1640 (const 16))) 1641 ((m32r/d (unit u-mac))) 1642 ) 1643 1644 (dni mulhi-a "mulhi-a" 1645 ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM)) 1646 "mulhi $src1,$src2,$acc" 1647 (+ OP1_3 (f-op23 0) src1 acc src2) 1648 (set acc 1649 (sra DI 1650 (sll DI 1651 (mul DI 1652 (ext DI (and WI src1 (const #xffff0000))) 1653 (ext DI (trunc HI (sra WI src2 (const 16))))) 1654 (const 16)) 1655 (const 16))) 1656 ((m32rx (unit u-mac)) 1657 (m32r2 (unit u-mac))) 1658 ) 1659 1660 (dni mullo "mullo" 1661 ((MACH m32r) (PIPE S) (IDOC ACCUM)) 1662 "mullo $src1,$src2" 1663 (+ OP1_3 OP2_1 src1 src2) 1664 (set accum 1665 (sra DI 1666 (sll DI 1667 (mul DI 1668 (ext DI (sll WI src1 (const 16))) 1669 (ext DI (trunc HI src2))) 1670 (const 16)) 1671 (const 16))) 1672 ((m32r/d (unit u-mac))) 1673 ) 1674 1675 (dni mullo-a "mullo-a" 1676 ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM)) 1677 "mullo $src1,$src2,$acc" 1678 (+ OP1_3 src1 acc (f-op23 1) src2) 1679 (set acc 1680 (sra DI 1681 (sll DI 1682 (mul DI 1683 (ext DI (sll WI src1 (const 16))) 1684 (ext DI (trunc HI src2))) 1685 (const 16)) 1686 (const 16))) 1687 ((m32rx (unit u-mac)) 1688 (m32r2 (unit u-mac))) 1689 ) 1690 1691 (dni mulwhi "mulwhi" 1692 ((MACH m32r) (PIPE S) (IDOC ACCUM)) 1693 "mulwhi $src1,$src2" 1694 (+ OP1_3 OP2_2 src1 src2) 1695 (set accum 1696 (sra DI 1697 (sll DI 1698 (mul DI 1699 (ext DI src1) 1700 (ext DI (trunc HI (sra WI src2 (const 16))))) 1701 (const 8)) 1702 (const 8))) 1703 ((m32r/d (unit u-mac))) 1704 ) 1705 1706 (dni mulwhi-a "mulwhi-a" 1707 ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC ACCUM)) 1708 "mulwhi $src1,$src2,$acc" 1709 (+ OP1_3 src1 acc (f-op23 2) src2) 1710 ; Note that this doesn't do the sign extension, which is correct. 1711 (set acc 1712 (mul (ext DI src1) 1713 (ext DI (trunc HI (sra src2 (const 16)))))) 1714 ((m32rx (unit u-mac)) 1715 (m32r2 (unit u-mac))) 1716 ) 1717 1718 (dni mulwlo "mulwlo" 1719 ((MACH m32r) (PIPE S) (IDOC ACCUM)) 1720 "mulwlo $src1,$src2" 1721 (+ OP1_3 OP2_3 src1 src2) 1722 (set accum 1723 (sra DI 1724 (sll DI 1725 (mul DI 1726 (ext DI src1) 1727 (ext DI (trunc HI src2))) 1728 (const 8)) 1729 (const 8))) 1730 ((m32r/d (unit u-mac))) 1731 ) 1732 1733 (dni mulwlo-a "mulwlo-a" 1734 ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC ACCUM)) 1735 "mulwlo $src1,$src2,$acc" 1736 (+ OP1_3 src1 acc (f-op23 3) src2) 1737 ; Note that this doesn't do the sign extension, which is correct. 1738 (set acc 1739 (mul (ext DI src1) 1740 (ext DI (trunc HI src2)))) 1741 ((m32rx (unit u-mac)) 1742 (m32r2 (unit u-mac))) 1743 ) 1744 1745 (dni mv "mv" 1746 ((PIPE OS) (IDOC ALU)) 1747 "mv $dr,$sr" 1748 (+ OP1_1 OP2_8 dr sr) 1749 (set dr sr) 1750 () 1751 ) 1752 1753 (dni mvfachi "mvfachi" 1754 ((MACH m32r) (PIPE S) (IDOC ACCUM)) 1755 "mvfachi $dr" 1756 (+ OP1_5 OP2_15 (f-r2 0) dr) 1757 (set dr (trunc WI (sra DI accum (const 32)))) 1758 ((m32r/d (unit u-exec (cycles 2)))) 1759 ) 1760 1761 (dni mvfachi-a "mvfachi-a" 1762 ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM)) 1763 "mvfachi $dr,$accs" 1764 (+ OP1_5 dr OP2_15 accs (f-op3 0)) 1765 (set dr (trunc WI (sra DI accs (const 32)))) 1766 ((m32rx (unit u-exec (cycles 2))) 1767 (m32r2 (unit u-exec (cycles 2)))) 1768 ) 1769 1770 (dni mvfaclo "mvfaclo" 1771 ((MACH m32r) (PIPE S) (IDOC ACCUM)) 1772 "mvfaclo $dr" 1773 (+ OP1_5 OP2_15 (f-r2 1) dr) 1774 (set dr (trunc WI accum)) 1775 ((m32r/d (unit u-exec (cycles 2)))) 1776 ) 1777 1778 (dni mvfaclo-a "mvfaclo-a" 1779 ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM)) 1780 "mvfaclo $dr,$accs" 1781 (+ OP1_5 dr OP2_15 accs (f-op3 1)) 1782 (set dr (trunc WI accs)) 1783 ((m32rx (unit u-exec (cycles 2))) 1784 (m32r2 (unit u-exec (cycles 2)))) 1785 ) 1786 1787 (dni mvfacmi "mvfacmi" 1788 ((MACH m32r) (PIPE S) (IDOC ACCUM)) 1789 "mvfacmi $dr" 1790 (+ OP1_5 OP2_15 (f-r2 2) dr) 1791 (set dr (trunc WI (sra DI accum (const 16)))) 1792 ((m32r/d (unit u-exec (cycles 2)))) 1793 ) 1794 1795 (dni mvfacmi-a "mvfacmi-a" 1796 ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM)) 1797 "mvfacmi $dr,$accs" 1798 (+ OP1_5 dr OP2_15 accs (f-op3 2)) 1799 (set dr (trunc WI (sra DI accs (const 16)))) 1800 ((m32rx (unit u-exec (cycles 2))) 1801 (m32r2 (unit u-exec (cycles 2)))) 1802 ) 1803 1804 (dni mvfc "mvfc" 1805 ((PIPE O) (IDOC MISC)) 1806 "mvfc $dr,$scr" 1807 (+ OP1_1 OP2_9 dr scr) 1808 (set dr scr) 1809 () 1810 ) 1811 1812 (dni mvtachi "mvtachi" 1813 ((MACH m32r) (PIPE S) (IDOC ACCUM)) 1814 "mvtachi $src1" 1815 (+ OP1_5 OP2_7 (f-r2 0) src1) 1816 (set accum 1817 (or DI 1818 (and DI accum (const DI #xffffffff)) 1819 (sll DI (ext DI src1) (const 32)))) 1820 ((m32r/d (unit u-exec (in sr src1)))) 1821 ) 1822 1823 (dni mvtachi-a "mvtachi-a" 1824 ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM)) 1825 "mvtachi $src1,$accs" 1826 (+ OP1_5 src1 OP2_7 accs (f-op3 0)) 1827 (set accs 1828 (or DI 1829 (and DI accs (const DI #xffffffff)) 1830 (sll DI (ext DI src1) (const 32)))) 1831 ((m32rx (unit u-exec (in sr src1))) 1832 (m32r2 (unit u-exec (in sr src1)))) 1833 ) 1834 1835 (dni mvtaclo "mvtaclo" 1836 ((MACH m32r) (PIPE S) (IDOC ACCUM)) 1837 "mvtaclo $src1" 1838 (+ OP1_5 OP2_7 (f-r2 1) src1) 1839 (set accum 1840 (or DI 1841 (and DI accum (const DI #xffffffff00000000)) 1842 (zext DI src1))) 1843 ((m32r/d (unit u-exec (in sr src1)))) 1844 ) 1845 1846 (dni mvtaclo-a "mvtaclo-a" 1847 ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM)) 1848 "mvtaclo $src1,$accs" 1849 (+ OP1_5 src1 OP2_7 accs (f-op3 1)) 1850 (set accs 1851 (or DI 1852 (and DI accs (const DI #xffffffff00000000)) 1853 (zext DI src1))) 1854 ((m32rx (unit u-exec (in sr src1))) 1855 (m32r2 (unit u-exec (in sr src1)))) 1856 ) 1857 1858 (dni mvtc "mvtc" 1859 ((PIPE O) (IDOC MISC)) 1860 "mvtc $sr,$dcr" 1861 (+ OP1_1 OP2_10 dcr sr) 1862 (set dcr sr) 1863 () 1864 ) 1865 1866 (dni neg "neg" 1867 ((PIPE OS) (IDOC ALU)) 1868 "neg $dr,$sr" 1869 (+ OP1_0 OP2_3 dr sr) 1870 (set dr (neg sr)) 1871 () 1872 ) 1873 1874 (dni nop "nop" 1875 ((PIPE OS) (IDOC MISC)) 1876 "nop" 1877 (+ OP1_7 OP2_0 (f-r1 0) (f-r2 0)) 1878 (c-code VOID "PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);\n") 1879 ; FIXME: quick hack: parallel nops don't contribute to cycle count. 1880 ; Other kinds of nops do however (which we currently ignore). 1881 ((m32r/d (unit u-exec (cycles 0))) 1882 (m32rx (unit u-exec (cycles 0))) 1883 (m32r2 (unit u-exec (cycles 0)))) 1884 ) 1885 1886 (dni not "not" 1887 ((PIPE OS) (IDOC ALU)) 1888 "not $dr,$sr" 1889 (+ OP1_0 OP2_11 dr sr) 1890 (set dr (inv sr)) 1891 () 1892 ) 1893 1894 (dni rac "rac" 1895 ((MACH m32r) (PIPE S) (IDOC MAC)) 1896 "rac" 1897 (+ OP1_5 OP2_9 (f-r1 0) (f-r2 0)) 1898 (sequence ((DI tmp1)) 1899 (set tmp1 (sll DI accum (const 1))) 1900 (set tmp1 (add DI tmp1 (const DI #x8000))) 1901 (set accum 1902 (cond DI 1903 ((gt tmp1 (const DI #x00007fffffff0000)) 1904 (const DI #x00007fffffff0000)) 1905 ((lt tmp1 (const DI #xffff800000000000)) 1906 (const DI #xffff800000000000)) 1907 (else (and tmp1 (const DI #xffffffffffff0000))))) 1908 ) 1909 ((m32r/d (unit u-mac))) 1910 ) 1911 1912 (dni rac-dsi "rac-dsi" 1913 ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) 1914 "rac $accd,$accs,$imm1" 1915 (+ OP1_5 accd (f-bits67 0) OP2_9 accs (f-bit14 0) imm1) 1916 (sequence ((DI tmp1)) 1917 (set tmp1 (sll accs imm1)) 1918 (set tmp1 (add tmp1 (const DI #x8000))) 1919 (set accd 1920 (cond DI 1921 ((gt tmp1 (const DI #x00007fffffff0000)) 1922 (const DI #x00007fffffff0000)) 1923 ((lt tmp1 (const DI #xffff800000000000)) 1924 (const DI #xffff800000000000)) 1925 (else (and tmp1 (const DI #xffffffffffff0000))))) 1926 ) 1927 ((m32rx (unit u-mac)) 1928 (m32r2 (unit u-mac))) 1929 ) 1930 1931 (dnmi rac-d "rac-d" 1932 ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) 1933 "rac $accd" 1934 (emit rac-dsi accd (f-accs 0) (f-imm1 0)) 1935 ) 1936 1937 (dnmi rac-ds "rac-ds" 1938 ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) 1939 "rac $accd,$accs" 1940 (emit rac-dsi accd accs (f-imm1 0)) 1941 ) 1942 1943 1944 (dni rach "rach" 1945 ((MACH m32r) (PIPE S) (IDOC MAC)) 1946 "rach" 1947 (+ OP1_5 OP2_8 (f-r1 0) (f-r2 0)) 1948 (sequence ((DI tmp1)) 1949 ; Lop off top 8 bits. 1950 ; The sign bit we want to use is bit 55 so the 64 bit value 1951 ; isn't properly signed which we deal with in the if's below. 1952 (set tmp1 (and accum (const DI #xffffffffffffff))) 1953 (if (andif (ge tmp1 (const DI #x003fff80000000)) 1954 (le tmp1 (const DI #x7fffffffffffff))) 1955 (set tmp1 (const DI #x003fff80000000)) 1956 ; else part 1957 (if (andif (ge tmp1 (const DI #x80000000000000)) 1958 (le tmp1 (const DI #xffc00000000000))) 1959 (set tmp1 (const DI #xffc00000000000)) 1960 (set tmp1 (and (add accum (const DI #x40000000)) 1961 (const DI #xffffffff80000000))))) 1962 (set tmp1 (sll tmp1 (const 1))) 1963 ; Sign extend top 8 bits. 1964 (set accum 1965 ; FIXME: 7? 1966 (sra DI (sll DI tmp1 (const 7)) (const 7))) 1967 ) 1968 ((m32r/d (unit u-mac))) 1969 ) 1970 1971 (dni rach-dsi "rach-dsi" 1972 ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) 1973 "rach $accd,$accs,$imm1" 1974 (+ OP1_5 accd (f-bits67 0) OP2_8 accs (f-bit14 0) imm1) 1975 (sequence ((DI tmp1)) 1976 (set tmp1 (sll accs imm1)) 1977 (set tmp1 (add tmp1 (const DI #x80000000))) 1978 (set accd 1979 (cond DI 1980 ((gt tmp1 (const DI #x00007fff00000000)) 1981 (const DI #x00007fff00000000)) 1982 ((lt tmp1 (const DI #xffff800000000000)) 1983 (const DI #xffff800000000000)) 1984 (else (and tmp1 (const DI #xffffffff00000000))))) 1985 ) 1986 ((m32rx (unit u-mac)) 1987 (m32r2 (unit u-mac))) 1988 ) 1989 1990 (dnmi rach-d "rach-d" 1991 ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) 1992 "rach $accd" 1993 (emit rach-dsi accd (f-accs 0) (f-imm1 0)) 1994 ) 1995 1996 (dnmi rach-ds "rach-ds" 1997 ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) 1998 "rach $accd,$accs" 1999 (emit rach-dsi accd accs (f-imm1 0)) 2000 ) 2001 2002 (dni rte "rte" 2003 (UNCOND-CTI (PIPE O) (IDOC BR)) 2004 "rte" 2005 (+ OP1_1 OP2_13 (f-r1 0) (f-r2 6)) 2006 (sequence () 2007 ; pc = bpc & -4 2008 (set pc (and (reg h-cr 6) (const -4))) 2009 ; bpc = bbpc 2010 (set (reg h-cr 6) (reg h-cr 14)) 2011 ; psw = bpsw 2012 (set (reg h-psw) (reg h-bpsw)) 2013 ; bpsw = bbpsw 2014 (set (reg h-bpsw) (reg h-bbpsw)) 2015 ) 2016 () 2017 ) 2018 2019 (dni seth "seth" 2020 ((IDOC ALU)) 2021 "seth $dr,$hash$hi16" 2022 (+ OP1_13 OP2_12 dr (f-r2 0) hi16) 2023 (set dr (sll WI hi16 (const 16))) 2024 () 2025 ) 2026 2027 (define-pmacro (shift-op sym op2-r-op op2-3-op op2-i-op sem-op) 2028 (begin 2029 (dni sym sym ((PIPE O_OS) (IDOC ALU)) 2030 (.str sym " $dr,$sr") 2031 (+ OP1_1 op2-r-op dr sr) 2032 (set dr (sem-op dr (and sr (const 31)))) 2033 () 2034 ) 2035 (dni (.sym sym "3") sym ((IDOC ALU)) 2036 (.str sym "3 $dr,$sr,$simm16") 2037 (+ OP1_9 op2-3-op dr sr simm16) 2038 (set dr (sem-op sr (and WI simm16 (const 31)))) 2039 () 2040 ) 2041 (dni (.sym sym "i") sym ((PIPE O_OS) (IDOC ALU)) 2042 (.str sym "i $dr,$uimm5") 2043 (+ OP1_5 (f-shift-op2 op2-i-op) dr uimm5) 2044 (set dr (sem-op dr uimm5)) 2045 () 2046 ) 2047 ) 2048 ) 2049 (shift-op sll OP2_4 OP2_12 2 sll) 2050 (shift-op sra OP2_2 OP2_10 1 sra) 2051 (shift-op srl OP2_0 OP2_8 0 srl) 2052 2053 (define-pmacro (store-op suffix op2-op mode) 2054 (begin 2055 (dni (.sym st suffix) (.str "st" suffix) 2056 ((PIPE O) (IDOC MEM)) 2057 (.str "st" suffix " $src1,@$src2") 2058 (+ OP1_2 op2-op src1 src2) 2059 (set mode (mem mode src2) src1) 2060 ((m32r/d (unit u-store (cycles 1))) 2061 (m32rx (unit u-store (cycles 1))) 2062 (m32r2 (unit u-store (cycles 1)))) 2063 ) 2064 (dnmi (.sym st suffix "-2") (.str "st" suffix "-2") 2065 (NO-DIS (PIPE O) (IDOC MEM)) 2066 (.str "st" suffix " $src1,@($src2)") 2067 (emit (.sym st suffix) src1 src2)) 2068 (dni (.sym st suffix -d) (.str "st" suffix "-d") 2069 ((IDOC MEM)) 2070 (.str "st" suffix " $src1,@($slo16,$src2)") 2071 (+ OP1_10 op2-op src1 src2 slo16) 2072 (set mode (mem mode (add src2 slo16)) src1) 2073 ((m32r/d (unit u-store (cycles 2))) 2074 (m32rx (unit u-store (cycles 2))) 2075 (m32r2 (unit u-store (cycles 2)))) 2076 ) 2077 (dnmi (.sym st suffix -d2) (.str "st" suffix "-d2") 2078 (NO-DIS (IDOC MEM)) 2079 (.str "st" suffix " $src1,@($src2,$slo16)") 2080 (emit (.sym st suffix -d) src1 src2 slo16)) 2081 ) 2082 ) 2083 (store-op "" OP2_4 WI) 2084 (store-op b OP2_0 QI) 2085 (store-op h OP2_2 HI) 2086 2087 (dni st-plus "st+" 2088 ((PIPE O) (IDOC MEM)) 2089 "st $src1,@+$src2" 2090 (+ OP1_2 OP2_6 src1 src2) 2091 ; This has to be coded carefully to avoid an "earlyclobber" of src2. 2092 (sequence ((WI new-src2)) 2093 (set new-src2 (add WI src2 (const WI 4))) 2094 (set (mem WI new-src2) src1) 2095 (set src2 new-src2)) 2096 ((m32r/d (unit u-store) 2097 (unit u-exec (in dr src2) (out dr src2) (cycles 0))) 2098 (m32rx (unit u-store) 2099 (unit u-exec (in dr src2) (out dr src2) (cycles 0))) 2100 (m32r2 (unit u-store) 2101 (unit u-exec (in dr src2) (out dr src2) (cycles 0))) 2102 ) 2103 ) 2104 2105 (dni sth-plus "sth+" 2106 ((MACH m32rx,m32r2) (PIPE O) SPECIAL) 2107 "sth $src1,@$src2+" 2108 (+ OP1_2 OP2_3 src1 src2) 2109 ; This has to be coded carefully to avoid an "earlyclobber" of src2. 2110 (sequence ((WI new-src2)) 2111 (set new-src2 src2) 2112 (set (mem HI new-src2) src1) 2113 (set src2 (add new-src2 (const 2)))) 2114 ((m32rx (unit u-store) 2115 (unit u-exec (in dr src2) (out dr src2) (cycles 0))) 2116 (m32r2 (unit u-store) 2117 (unit u-exec (in dr src2) (out dr src2) (cycles 0))) 2118 ) 2119 ) 2120 2121 (dni stb-plus "stb+" 2122 ((MACH m32rx,m32r2) (PIPE O) SPECIAL) 2123 "stb $src1,@$src2+" 2124 (+ OP1_2 OP2_1 src1 src2) 2125 ; This has to be coded carefully to avoid an "earlyclobber" of src2. 2126 (sequence ((WI new-src2)) 2127 (set new-src2 src2) 2128 (set (mem QI new-src2) src1) 2129 (set src2 (add new-src2 (const 1)))) 2130 ((m32rx (unit u-store) 2131 (unit u-exec (in dr src2) (out dr src2) (cycles 0))) 2132 (m32r2 (unit u-store) 2133 (unit u-exec (in dr src2) (out dr src2) (cycles 0))) 2134 ) 2135 ) 2136 2137 (dni st-minus "st-" 2138 ((PIPE O) (IDOC MEM)) 2139 "st $src1,@-$src2" 2140 (+ OP1_2 OP2_7 src1 src2) 2141 ; This is the original way. It doesn't work for parallel execution 2142 ; because of the earlyclobber of src2. 2143 ;(sequence () 2144 ; (set src2 (sub src2 (const 4))) 2145 ; (set (mem WI src2) src1)) 2146 (sequence ((WI new-src2)) 2147 (set new-src2 (sub src2 (const 4))) 2148 (set (mem WI new-src2) src1) 2149 (set src2 new-src2)) 2150 ((m32r/d (unit u-store) 2151 (unit u-exec (in dr src2) (out dr src2) (cycles 0))) 2152 (m32rx (unit u-store) 2153 (unit u-exec (in dr src2) (out dr src2) (cycles 0))) 2154 (m32r2 (unit u-store) 2155 (unit u-exec (in dr src2) (out dr src2) (cycles 0))) 2156 ) 2157 ) 2158 2159 (dnmi push "push" ((PIPE O) (IDOC MEM)) 2160 "push $src1" 2161 (emit st-minus src1 (src2 15)) ; "st %0,@-sp" 2162 ) 2163 2164 (dni sub "sub" 2165 ((PIPE OS) (IDOC ALU)) 2166 "sub $dr,$sr" 2167 (+ OP1_0 OP2_2 dr sr) 2168 (set dr (sub dr sr)) 2169 () 2170 ) 2171 2172 (dni subv "sub:rv" 2173 ((PIPE OS) (IDOC ALU)) 2174 "subv $dr,$sr" 2175 (+ OP1_0 OP2_0 dr sr) 2176 (parallel () 2177 (set dr (sub dr sr)) 2178 (set condbit (sub-oflag dr sr (const 0)))) 2179 () 2180 ) 2181 2182 (dni subx "sub:rx" 2183 ((PIPE OS) (IDOC ALU)) 2184 "subx $dr,$sr" 2185 (+ OP1_0 OP2_1 dr sr) 2186 (parallel () 2187 (set dr (subc dr sr condbit)) 2188 (set condbit (sub-cflag dr sr condbit))) 2189 () 2190 ) 2191 2192 (dni trap "trap" 2193 (UNCOND-CTI FILL-SLOT (PIPE O) (IDOC MISC)) 2194 "trap $uimm4" 2195 (+ OP1_1 OP2_15 (f-r1 0) uimm4) 2196 (sequence () 2197 ; bbpc = bpc 2198 (set (reg h-cr 14) (reg h-cr 6)) 2199 ; Set bpc to the return address. Actually it's not quite the 2200 ; return address as RTE rounds the address down to a word 2201 ; boundary. 2202 (set (reg h-cr 6) (add pc (const 4))) 2203 ; bbpsw = bpsw 2204 (set (reg h-bbpsw) (reg h-bpsw)) 2205 ; bpsw = psw 2206 (set (reg h-bpsw) (reg h-psw)) 2207 ; sm is unchanged, ie,c are set to zero. 2208 (set (reg h-psw) (and (reg h-psw) (const #x80))) 2209 ; m32r_trap handles operating vs user mode 2210 (set WI pc (c-call WI "m32r_trap" pc uimm4)) 2211 ) 2212 () 2213 ) 2214 2215 (dni unlock "unlock" 2216 ((PIPE O) (IDOC MISC)) 2217 "unlock $src1,@$src2" 2218 (+ OP1_2 OP2_5 src1 src2) 2219 (sequence () 2220 (if (reg h-lock) 2221 (set (mem WI src2) src1)) 2222 (set (reg h-lock) (const BI 0))) 2223 ((m32r/d (unit u-load)) 2224 (m32rx (unit u-load)) 2225 (m32r2 (unit u-load))) 2226 ) 2227 2228 ; Saturate into byte. 2229 (dni satb "satb" 2230 ((MACH m32rx,m32r2) (IDOC ALU)) 2231 "satb $dr,$sr" 2232 (+ OP1_8 dr OP2_6 sr (f-uimm16 #x0300)) 2233 (set dr 2234 ; FIXME: min/max would simplify this nicely of course. 2235 (cond WI 2236 ((ge sr (const 127)) (const 127)) 2237 ((le sr (const -128)) (const -128)) 2238 (else sr))) 2239 () 2240 ) 2241 2242 ; Saturate into half word. 2243 (dni sath "sath" 2244 ((MACH m32rx,m32r2) (IDOC ALU)) 2245 "sath $dr,$sr" 2246 (+ OP1_8 dr OP2_6 sr (f-uimm16 #x0200)) 2247 (set dr 2248 (cond WI 2249 ((ge sr (const 32767)) (const 32767)) 2250 ((le sr (const -32768)) (const -32768)) 2251 (else sr))) 2252 () 2253 ) 2254 2255 ; Saturate word. 2256 (dni sat "sat" 2257 ((MACH m32rx,m32r2) SPECIAL (IDOC ALU)) 2258 "sat $dr,$sr" 2259 (+ OP1_8 dr OP2_6 sr (f-uimm16 0)) 2260 (set dr 2261 (if WI condbit 2262 (if WI (lt sr (const 0)) 2263 (const #x7fffffff) 2264 (const #x80000000)) 2265 sr)) 2266 () 2267 ) 2268 2269 ; Parallel compare byte zeros. 2270 ; Set C bit in condition register if any byte in source register is zero. 2271 (dni pcmpbz "pcmpbz" 2272 ((MACH m32rx,m32r2) (PIPE OS) SPECIAL (IDOC ALU)) 2273 "pcmpbz $src2" 2274 (+ OP1_0 (f-r1 3) OP2_7 src2) 2275 (set condbit 2276 (cond BI 2277 ((eq (and src2 (const #xff)) (const 0)) (const BI 1)) 2278 ((eq (and src2 (const #xff00)) (const 0)) (const BI 1)) 2279 ((eq (and src2 (const #xff0000)) (const 0)) (const BI 1)) 2280 ((eq (and src2 (const #xff000000)) (const 0)) (const BI 1)) 2281 (else (const BI 0)))) 2282 ((m32rx (unit u-cmp)) 2283 (m32r2 (unit u-cmp))) 2284 ) 2285 2286 ; Add accumulators 2287 (dni sadd "sadd" 2288 ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM)) 2289 "sadd" 2290 (+ OP1_5 (f-r1 0) OP2_14 (f-r2 4)) 2291 (set (reg h-accums 0) 2292 (add (sra (reg h-accums 1) (const 16)) 2293 (reg h-accums 0))) 2294 ((m32rx (unit u-mac)) 2295 (m32r2 (unit u-mac))) 2296 ) 2297 2298 ; Multiply and add into accumulator 1 2299 (dni macwu1 "macwu1" 2300 ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) 2301 "macwu1 $src1,$src2" 2302 (+ OP1_5 src1 OP2_11 src2) 2303 (set (reg h-accums 1) 2304 (sra DI 2305 (sll DI 2306 (add DI 2307 (reg h-accums 1) 2308 (mul DI 2309 (ext DI src1) 2310 (ext DI (and src2 (const #xffff))))) 2311 (const 8)) 2312 (const 8))) 2313 ((m32rx (unit u-mac)) 2314 (m32r2 (unit u-mac))) 2315 ) 2316 2317 ; Multiply and subtract from accumulator 0 2318 (dni msblo "msblo" 2319 ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) 2320 "msblo $src1,$src2" 2321 (+ OP1_5 src1 OP2_13 src2) 2322 (set accum 2323 (sra DI 2324 (sll DI 2325 (sub accum 2326 (sra DI 2327 (sll DI 2328 (mul DI 2329 (ext DI (trunc HI src1)) 2330 (ext DI (trunc HI src2))) 2331 (const 32)) 2332 (const 16))) 2333 (const 8)) 2334 (const 8))) 2335 ((m32rx (unit u-mac)) 2336 (m32r2 (unit u-mac))) 2337 ) 2338 2339 ; Multiply into accumulator 1 2340 (dni mulwu1 "mulwu1" 2341 ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) 2342 "mulwu1 $src1,$src2" 2343 (+ OP1_5 src1 OP2_10 src2) 2344 (set (reg h-accums 1) 2345 (sra DI 2346 (sll DI 2347 (mul DI 2348 (ext DI src1) 2349 (ext DI (and src2 (const #xffff)))) 2350 (const 16)) 2351 (const 16))) 2352 ((m32rx (unit u-mac)) 2353 (m32r2 (unit u-mac))) 2354 ) 2355 2356 ; Multiply and add into accumulator 1 2357 (dni maclh1 "maclh1" 2358 ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) 2359 "maclh1 $src1,$src2" 2360 (+ OP1_5 src1 OP2_12 src2) 2361 (set (reg h-accums 1) 2362 (sra DI 2363 (sll DI 2364 (add DI 2365 (reg h-accums 1) 2366 (sll DI 2367 (ext DI 2368 (mul SI 2369 (ext SI (trunc HI src1)) 2370 (sra SI src2 (const SI 16)))) 2371 (const 16))) 2372 (const 8)) 2373 (const 8))) 2374 ((m32rx (unit u-mac)) 2375 (m32r2 (unit u-mac))) 2376 ) 2377 2378 ; skip instruction if C 2379 (dni sc "sc" 2380 ((MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR)) 2381 "sc" 2382 (+ OP1_7 (f-r1 4) OP2_0 (f-r2 1)) 2383 (skip (zext INT condbit)) 2384 () 2385 ) 2386 2387 ; skip instruction if not C 2388 (dni snc "snc" 2389 ((MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR)) 2390 "snc" 2391 (+ OP1_7 (f-r1 5) OP2_0 (f-r2 1)) 2392 (skip (zext INT (not condbit))) 2393 () 2394 ) 2395 2396 ; PSW &= ((~ uimm8) | 0xff00) 2397 (dni clrpsw "clrpsw" 2398 ((PIPE O) SPECIAL_M32R) 2399 "clrpsw $uimm8" 2400 (+ OP1_7 (f-r1 2) uimm8) 2401 (set USI (reg h-cr 0) 2402 (and USI (reg h-cr 0) 2403 (or USI (zext SI (inv QI uimm8)) (const #xff00)))) 2404 () 2405 ) 2406 2407 ; PSW |= (unsigned char) uimm8 2408 (dni setpsw "setpsw" 2409 ((PIPE O) SPECIAL_M32R) 2410 "setpsw $uimm8" 2411 (+ OP1_7 (f-r1 1) uimm8) 2412 (set USI (reg h-cr 0) uimm8) 2413 () 2414 ) 2415 2416 ; bset 2417 (dni bset "bset" 2418 (SPECIAL_M32R) 2419 "bset $uimm3,@($slo16,$sr)" 2420 (+ OP1_10 (f-bit4 0) uimm3 OP2_6 sr slo16) 2421 (set QI (mem QI (add sr slo16)) 2422 (or QI (mem QI (add sr slo16)) 2423 (sll QI (const 1) (sub (const 7) uimm3)))) 2424 () 2425 ) 2426 2427 ; bclr 2428 (dni bclr "bclr" 2429 (SPECIAL_M32R) 2430 "bclr $uimm3,@($slo16,$sr)" 2431 (+ OP1_10 (f-bit4 0) uimm3 OP2_7 sr slo16) 2432 (set QI (mem QI (add sr slo16)) 2433 (and QI (mem QI (add sr slo16)) 2434 (inv QI (sll QI (const 1) (sub (const 7) uimm3))))) 2435 () 2436 ) 2437 2438 ; btst 2439 (dni btst "btst" 2440 (SPECIAL_M32R (PIPE O)) 2441 "btst $uimm3,$sr" 2442 (+ OP1_0 (f-bit4 0) uimm3 OP2_15 sr) 2443 (set condbit (and QI (srl QI sr (sub (const 7) uimm3)) (const 1))) 2444 () 2445 ) 2446