| /external/strace/linux/powerpc/ |
| get_syscall_args.c | 6 tcp->u_arg[1] = ppc_regs.gpr[4];
7 tcp->u_arg[2] = ppc_regs.gpr[5];
8 tcp->u_arg[3] = ppc_regs.gpr[6];
9 tcp->u_arg[4] = ppc_regs.gpr[7];
10 tcp->u_arg[5] = ppc_regs.gpr[8];
|
| get_error.c | 6 tcp->u_error = ppc_regs.gpr[3];
8 tcp->u_rval = ppc_regs.gpr[3];
|
| get_scno.c | 5 tcp->scno = ppc_regs.gpr[0];
|
| /external/strace/linux/or1k/ |
| get_syscall_args.c | 5 tcp->u_arg[0] = or1k_regs.gpr[3 + 0];
6 tcp->u_arg[1] = or1k_regs.gpr[3 + 1];
7 tcp->u_arg[2] = or1k_regs.gpr[3 + 2];
8 tcp->u_arg[3] = or1k_regs.gpr[3 + 3];
9 tcp->u_arg[4] = or1k_regs.gpr[3 + 4];
10 tcp->u_arg[5] = or1k_regs.gpr[3 + 5];
|
| get_error.c | 4 if (check_errno && is_negated_errno(or1k_regs.gpr[11])) {
6 tcp->u_error = -or1k_regs.gpr[11];
8 tcp->u_rval = or1k_regs.gpr[11];
|
| get_scno.c | 5 tcp->scno = or1k_regs.gpr[11];
|
| /prebuilts/go/darwin-x86/src/runtime/ |
| signal_linux_ppc64x.go | 18 func (c *sigctxt) r0() uint64 { return c.regs().gpr[0] }
19 func (c *sigctxt) r1() uint64 { return c.regs().gpr[1] }
20 func (c *sigctxt) r2() uint64 { return c.regs().gpr[2] }
21 func (c *sigctxt) r3() uint64 { return c.regs().gpr[3] }
22 func (c *sigctxt) r4() uint64 { return c.regs().gpr[4] }
23 func (c *sigctxt) r5() uint64 { return c.regs().gpr[5] }
24 func (c *sigctxt) r6() uint64 { return c.regs().gpr[6] }
25 func (c *sigctxt) r7() uint64 { return c.regs().gpr[7] }
26 func (c *sigctxt) r8() uint64 { return c.regs().gpr[8] }
27 func (c *sigctxt) r9() uint64 { return c.regs().gpr[9]
[all...] |
| /prebuilts/go/linux-x86/src/runtime/ |
| signal_linux_ppc64x.go | 18 func (c *sigctxt) r0() uint64 { return c.regs().gpr[0] }
19 func (c *sigctxt) r1() uint64 { return c.regs().gpr[1] }
20 func (c *sigctxt) r2() uint64 { return c.regs().gpr[2] }
21 func (c *sigctxt) r3() uint64 { return c.regs().gpr[3] }
22 func (c *sigctxt) r4() uint64 { return c.regs().gpr[4] }
23 func (c *sigctxt) r5() uint64 { return c.regs().gpr[5] }
24 func (c *sigctxt) r6() uint64 { return c.regs().gpr[6] }
25 func (c *sigctxt) r7() uint64 { return c.regs().gpr[7] }
26 func (c *sigctxt) r8() uint64 { return c.regs().gpr[8] }
27 func (c *sigctxt) r9() uint64 { return c.regs().gpr[9]
[all...] |
| /toolchain/binutils/binutils-2.25/ld/emulparams/ |
| elf32ip2k.sh | 11 GRP_MEMORY=gpr
20 OTHER_READWRITE_SECTIONS='.gpr 0x1000080 : { *(.gpr) }'
|
| /external/llvm/test/CodeGen/Mips/ |
| analyzebranch.ll | 3 ; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR -check-prefix=32-GPR
7 ; RUN: llc -march=mips64 -mcpu=mips64r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR -check-prefix=64-GPR
16 ; 32-GPR: mtc1 $zero, $[[Z:f[0-9]]]
17 ; 32-GPR: mthc1 $zero, $[[Z:f[0-9]]]
18 ; 64-GPR: dmtc1 $zero, $[[Z:f[0-9]]]
19 ; GPR: cmp.lt.d $[[FGRCC:f[0-9]+]], $[[Z]], $f12
20 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC]]
21 ; GPR-NOT: not $[[GPRCC]], $[[GPRCC]
[all...] |
| fpbr.ll | 3 ; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL -check-prefix=GPR -check-prefix=32-GPR
6 ; RUN: llc < %s -march=mips64el -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL -check-prefix=GPR -check-prefix=64-GPR
16 ; 32-GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f14
17 ; 64-GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f13
18 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
20 ; GPR: not $[[GPRCC]], $[[GPRCC]]
21 ; GPR: bnez $[[GPRCC]], $BB0_2
50 ; 32-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f14, $f1
[all...] |
| mips64muldiv.ll | 4 ; RUN: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR
9 ; GPR - Targets with register based mul/div (i.e. MIPS32r6)
16 ; GPR: dmul $2, ${{[45]}}, ${{[45]}}
33 ; GPR: dmuh $[[T1:[0-9]+]], $4, $[[T0]]
46 ; GPR: ddivu $2, $4, $5
56 ; GPR: ddiv $2, $4, $5
66 ; GPR: dmodu $2, $4, $5
76 ; GPR: dmod $2, $4, $5
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| vertex-fetch-encoding.ll | 5 ; NI: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0 ; encoding: [0x40,0x01,0x0[[GPR]],0x10,0x0[[GPR]],0xf0,0x5f,0x13,0x00,0x00,0x08,0x00
7 ; CM: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0 ; encoding: [0x40,0x01,0x0[[GPR]],0x00,0x0[[GPR]],0xf0,0x5f,0x13,0x00,0x00,0x00,0x00
|
| literals.ll | 39 ; CHECK: MOV {{\** *}}T[[GPR:[0-9]]].X, 0.0
40 ; CHECK-NEXT: MOV {{\** *}}T[[GPR]].Y, 0.0
41 ; CHECK-NEXT: MOV {{\** *}}T[[GPR]].Z, 0.0
42 ; CHECK-NEXT: MOV {{\** *}}T[[GPR]].W, 0.0
51 ; CHECK: DOT4 T[[GPR:[0-9]]].X, 1.0
52 ; CHECK-NEXT: DOT4 T[[GPR]].Y (MASKED), 1.0
53 ; CHECK-NEXT: DOT4 T[[GPR]].Z (MASKED), 1.0
54 ; CHECK-NEXT: DOT4 * T[[GPR]].W (MASKED), 1.0
|
| /external/llvm/lib/Target/ARM/ |
| ARMInstrInfo.td | 348 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
550 let MIOperandInfo = (ops GPR, i32imm);
561 let MIOperandInfo = (ops GPR, GPR, i32imm);
572 let MIOperandInfo = (ops GPR, i32imm);
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| attr-gnu-4-0.d | 8 GPR size: .*
|
| attr-none-double.d | 13 GPR size: .*
|
| attr-none-soft-float.d | 14 GPR size: .*
|
| elf_ase_micromips.d | 12 GPR size: 32
|
| elf_ase_mips16.d | 12 GPR size: 32
|
| module-check.d | 12 GPR size: 32
|
| module-mfp32.d | 12 GPR size: 32
|
| /toolchain/binutils/binutils-2.25/cpu/ |
| mep-h1.cpu | 28 ((mep (unit u-use-gpr (in usereg rn))
29 (unit u-use-gpr (in usereg rma))
37 ((mep (unit u-use-gpr (in usereg rma))
40 (unit u-ldcb-gpr (out loadreg rn)))))
48 ((mep (unit u-use-gpr (in usereg rma))
|
| /external/elfutils/backends/ |
| ppc_initreg.c | 95 const size_t gprs = sizeof (user_regs.r.gpr) / sizeof (*user_regs.r.gpr);
97 for (unsigned gpr = 0; gpr < gprs; gpr++)
98 dwarf_regs[gpr] = user_regs.r.gpr[gpr];
|
| /external/llvm/test/CodeGen/AArch64/ |
| fpconv-vector-op-scalarize.ll | 10 ; CHECK: sbfx [[GPR:w[0-9]+]], w0, #0, #1
11 ; CHECK-NEXT: scvtf d0, [[GPR]]
20 ; CHECK: and [[GPR:w[0-9]+]], w0, #0x1
21 ; CHECK-NEXT: ucvtf d0, [[GPR]]
|
