| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/ |
| bitfield-bfm.s | 50 .macro op_bfm signed, reg, immr, imms
51 \signed\()bfm \reg\()zr, \reg\()7, #\immr, #\imms // e.g. sbfm xzr, x7, #0, #15
55 op_bfm signed=\signed, reg=\reg, immr=0, imms=\imms
60 op_bfm signed=\signed, reg=\reg, immr=\shift, imms=\imms
66 op_bfm signed=\signed, reg=\reg, immr="((32-\shift)&31)", imms="(31-\shift)"
68 op_bfm signed=\signed, reg=\reg, immr="((64-\shift)&63)", imms="(63-\shift)"
75 op_bfm signed=\signed, reg=\reg, immr="((32-\lsb)&31)", imms="(\width-1)"
77 op_bfm signed=\signed, reg=\reg, immr="((64-\lsb)&63)", imms="(\width-1)"
83 op_bfm signed=\signed, reg=\reg, immr=\lsb, imms="(\lsb+\width-1)"
|
| mov.s | 38 // 4 bits in the 'immr' field is non-zero. The top bits are ignored
|
| /external/llvm/test/CodeGen/AArch64/ |
| bitfield-insert-0.ll | 3 ; The encoding of lsb -> immr in the CGed bitfield instructions was wrong at one
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| arm64-basic-a64-undefined.txt | 20 # UBFM is undefined when s == 0 and imms<5> or immr<5> is 1.
|
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AddressingModes.h | 212 /// the form N:immr:imms.
251 // Encode in Immr the number of RORs it would take to get *from* 0^m 1^n
255 unsigned Immr = (Size - I) & (Size - 1);
268 Encoding = (N << 12) | (Immr << 6) | (NImms & 0x3f);
290 /// "N:immr:imms" (where the immr and imms fields are each 6 bits) into the
293 // Extract the N, imms, and immr fields.
295 unsigned immr = (val >> 6) & 0x3f; local
302 unsigned R = immr & (size - 1);
318 /// in the form "N:immr:imms" (where the immr and imms fields are each 6 bits
[all...] |
| /external/v8/src/arm64/ |
| assembler-arm64-inl.h | 1067 Instr Assembler::ImmR(unsigned immr, unsigned reg_size) {
1068 DCHECK(((reg_size == kXRegSizeInBits) && is_uint6(immr)) ||
1069 ((reg_size == kWRegSizeInBits) && is_uint5(immr)));
1071 DCHECK(is_uint6(immr));
1072 return immr << ImmR_offset;
1085 Instr Assembler::ImmRotate(unsigned immr, unsigned reg_size) {
1087 DCHECK(((reg_size == kXRegSizeInBits) && is_uint6(immr)) ||
1088 ((reg_size == kWRegSizeInBits) && is_uint5(immr)));
1090 return immr << ImmRotate_offset
[all...] |
| instructions-arm64.cc | 101 // N imms immr size S R
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| assembler-arm64.cc | [all...] |
| assembler-arm64.h | [all...] |
| /external/valgrind/VEX/priv/ |
| host_mips_defs.c | 683 const HChar *showMIPSAluOp(MIPSAluOp op, Bool immR)
688 ret = immR ? "addiu" : "addu";
694 ret = immR ? "andi" : "and";
697 ret = immR ? "ori" : "or";
700 vassert(immR == False); /*there's no nor with an immediate operand!? */
704 ret = immR ? "xori" : "xor";
707 ret = immR ? "daddi" : "dadd";
710 ret = immR ? "dsubi" : "dsub";
713 ret = immR ? "slti" : "slt";
722 const HChar *showMIPSShftOp(MIPSShftOp op, Bool immR, Bool sz32
[all...] |
| host_tilegx_defs.c | [all...] |
| host_ppc_defs.c | 506 const HChar* showPPCAluOp ( PPCAluOp op, Bool immR ) {
508 case Palu_ADD: return immR ? "addi" : "add";
509 case Palu_SUB: return immR ? "subi" : "sub";
510 case Palu_AND: return immR ? "andi." : "and";
511 case Palu_OR: return immR ? "ori" : "or";
512 case Palu_XOR: return immR ? "xori" : "xor";
517 const HChar* showPPCShftOp ( PPCShftOp op, Bool immR, Bool sz32 ) {
519 case Pshft_SHL: return sz32 ? (immR ? "slwi" : "slw") :
520 (immR ? "sldi" : "sld");
521 case Pshft_SHR: return sz32 ? (immR ? "srwi" : "srw")
[all...] |
| host_arm64_defs.h | 193 UChar immR; /* 0 .. 63 */
203 extern ARM64RIL* ARM64RIL_I13 ( UChar bitN, UChar immR, UChar immS );
[all...] |
| guest_arm64_toIR.c | [all...] |
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | 112 int64_t immr = Op2.getImm(); local
114 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) {
118 ((imms + 1 == immr))) {
123 shift = immr;
126 shift = immr;
129 shift = immr;
132 shift = immr;
162 int ImmR = MI->getOperand(3).getImm();
166 (ImmR == 0 || ImmS < ImmR)) {
[all...] |
| /system/core/libpixelflinger/codeflinger/ |
| Arm64Assembler.h | 236 uint32_t immr, uint32_t imms);
238 uint32_t immr, uint32_t imms);
240 uint32_t immr, uint32_t imms);
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| Arm64Assembler.cpp | [all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| aarch64-dis.c | 565 /* Decode imm for e.g. BFM <Wd>, <Wn>, #<immr>, #<imms>.
728 /* value is N:immr:imms. */
1557 int64_t immr, imms; local
1584 int64_t immr, imms, val; local
1611 int64_t immr = inst->operands[2].imm.value; local
[all...] |
| aarch64-opc-2.c | 74 {AARCH64_OPND_CLASS_IMMEDIATE, "IMMR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_immr}, "the right rotate amount"},
|
| aarch64-asm.c | 314 BFM <Wd>, <Wn>, #<immr>, #<imms>. */
999 /* When <imms> >= <immr>, the instruction written:
1016 /* When <imms> < <immr>, the instruction written:
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 1612 int immr = Srl_imm - Shl_imm; local
[all...] |
| /external/vixl/src/vixl/a64/ |
| assembler-a64.h | [all...] |
| instructions-a64.cc | 141 // N imms immr size S R
|
| macro-assembler-a64.h | [all...] |
| assembler-a64.cc | 1089 unsigned immr,
1094 ImmR(immr, rd.size()) | ImmS(imms, rn.size()) | Rn(rn) | Rd(rd));
1100 unsigned immr,
1105 ImmR(immr, rd.size()) | ImmS(imms, rn.size()) | Rn(rn) | Rd(rd));
1111 unsigned immr,
1116 ImmR(immr, rd.size()) | ImmS(imms, rn.size()) | Rn(rn) | Rd(rd));
[all...] |
