1 //==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This class prints an AArch64 MCInst to a .s file. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "AArch64InstPrinter.h" 15 #include "MCTargetDesc/AArch64AddressingModes.h" 16 #include "Utils/AArch64BaseInfo.h" 17 #include "llvm/ADT/STLExtras.h" 18 #include "llvm/ADT/StringExtras.h" 19 #include "llvm/MC/MCExpr.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCRegisterInfo.h" 22 #include "llvm/Support/Format.h" 23 #include "llvm/Support/raw_ostream.h" 24 using namespace llvm; 25 26 #define DEBUG_TYPE "asm-printer" 27 28 #define GET_INSTRUCTION_NAME 29 #define PRINT_ALIAS_INSTR 30 #include "AArch64GenAsmWriter.inc" 31 #define GET_INSTRUCTION_NAME 32 #define PRINT_ALIAS_INSTR 33 #include "AArch64GenAsmWriter1.inc" 34 35 AArch64InstPrinter::AArch64InstPrinter(const MCAsmInfo &MAI, 36 const MCInstrInfo &MII, 37 const MCRegisterInfo &MRI) 38 : MCInstPrinter(MAI, MII, MRI) {} 39 40 AArch64AppleInstPrinter::AArch64AppleInstPrinter(const MCAsmInfo &MAI, 41 const MCInstrInfo &MII, 42 const MCRegisterInfo &MRI) 43 : AArch64InstPrinter(MAI, MII, MRI) {} 44 45 void AArch64InstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { 46 // This is for .cfi directives. 47 OS << getRegisterName(RegNo); 48 } 49 50 void AArch64InstPrinter::printInst(const MCInst *MI, raw_ostream &O, 51 StringRef Annot, 52 const MCSubtargetInfo &STI) { 53 // Check for special encodings and print the canonical alias instead. 54 55 unsigned Opcode = MI->getOpcode(); 56 57 if (Opcode == AArch64::SYSxt) 58 if (printSysAlias(MI, STI, O)) { 59 printAnnotation(O, Annot); 60 return; 61 } 62 63 // SBFM/UBFM should print to a nicer aliased form if possible. 64 if (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri || 65 Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) { 66 const MCOperand &Op0 = MI->getOperand(0); 67 const MCOperand &Op1 = MI->getOperand(1); 68 const MCOperand &Op2 = MI->getOperand(2); 69 const MCOperand &Op3 = MI->getOperand(3); 70 71 bool IsSigned = (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri); 72 bool Is64Bit = (Opcode == AArch64::SBFMXri || Opcode == AArch64::UBFMXri); 73 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) { 74 const char *AsmMnemonic = nullptr; 75 76 switch (Op3.getImm()) { 77 default: 78 break; 79 case 7: 80 if (IsSigned) 81 AsmMnemonic = "sxtb"; 82 else if (!Is64Bit) 83 AsmMnemonic = "uxtb"; 84 break; 85 case 15: 86 if (IsSigned) 87 AsmMnemonic = "sxth"; 88 else if (!Is64Bit) 89 AsmMnemonic = "uxth"; 90 break; 91 case 31: 92 // *xtw is only valid for signed 64-bit operations. 93 if (Is64Bit && IsSigned) 94 AsmMnemonic = "sxtw"; 95 break; 96 } 97 98 if (AsmMnemonic) { 99 O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg()) 100 << ", " << getRegisterName(getWRegFromXReg(Op1.getReg())); 101 printAnnotation(O, Annot); 102 return; 103 } 104 } 105 106 // All immediate shifts are aliases, implemented using the Bitfield 107 // instruction. In all cases the immediate shift amount shift must be in 108 // the range 0 to (reg.size -1). 109 if (Op2.isImm() && Op3.isImm()) { 110 const char *AsmMnemonic = nullptr; 111 int shift = 0; 112 int64_t immr = Op2.getImm(); 113 int64_t imms = Op3.getImm(); 114 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) { 115 AsmMnemonic = "lsl"; 116 shift = 31 - imms; 117 } else if (Opcode == AArch64::UBFMXri && imms != 0x3f && 118 ((imms + 1 == immr))) { 119 AsmMnemonic = "lsl"; 120 shift = 63 - imms; 121 } else if (Opcode == AArch64::UBFMWri && imms == 0x1f) { 122 AsmMnemonic = "lsr"; 123 shift = immr; 124 } else if (Opcode == AArch64::UBFMXri && imms == 0x3f) { 125 AsmMnemonic = "lsr"; 126 shift = immr; 127 } else if (Opcode == AArch64::SBFMWri && imms == 0x1f) { 128 AsmMnemonic = "asr"; 129 shift = immr; 130 } else if (Opcode == AArch64::SBFMXri && imms == 0x3f) { 131 AsmMnemonic = "asr"; 132 shift = immr; 133 } 134 if (AsmMnemonic) { 135 O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg()) 136 << ", " << getRegisterName(Op1.getReg()) << ", #" << shift; 137 printAnnotation(O, Annot); 138 return; 139 } 140 } 141 142 // SBFIZ/UBFIZ aliases 143 if (Op2.getImm() > Op3.getImm()) { 144 O << '\t' << (IsSigned ? "sbfiz" : "ubfiz") << '\t' 145 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg()) 146 << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1; 147 printAnnotation(O, Annot); 148 return; 149 } 150 151 // Otherwise SBFX/UBFX is the preferred form 152 O << '\t' << (IsSigned ? "sbfx" : "ubfx") << '\t' 153 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg()) 154 << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1; 155 printAnnotation(O, Annot); 156 return; 157 } 158 159 if (Opcode == AArch64::BFMXri || Opcode == AArch64::BFMWri) { 160 const MCOperand &Op0 = MI->getOperand(0); // Op1 == Op0 161 const MCOperand &Op2 = MI->getOperand(2); 162 int ImmR = MI->getOperand(3).getImm(); 163 int ImmS = MI->getOperand(4).getImm(); 164 165 if ((Op2.getReg() == AArch64::WZR || Op2.getReg() == AArch64::XZR) && 166 (ImmR == 0 || ImmS < ImmR)) { 167 // BFC takes precedence over its entire range, sligtly differently to BFI. 168 int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32; 169 int LSB = (BitWidth - ImmR) % BitWidth; 170 int Width = ImmS + 1; 171 172 O << "\tbfc\t" << getRegisterName(Op0.getReg()) 173 << ", #" << LSB << ", #" << Width; 174 printAnnotation(O, Annot); 175 return; 176 } else if (ImmS < ImmR) { 177 // BFI alias 178 int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32; 179 int LSB = (BitWidth - ImmR) % BitWidth; 180 int Width = ImmS + 1; 181 182 O << "\tbfi\t" << getRegisterName(Op0.getReg()) << ", " 183 << getRegisterName(Op2.getReg()) << ", #" << LSB << ", #" << Width; 184 printAnnotation(O, Annot); 185 return; 186 } 187 188 int LSB = ImmR; 189 int Width = ImmS - ImmR + 1; 190 // Otherwise BFXIL the preferred form 191 O << "\tbfxil\t" 192 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op2.getReg()) 193 << ", #" << LSB << ", #" << Width; 194 printAnnotation(O, Annot); 195 return; 196 } 197 198 // Symbolic operands for MOVZ, MOVN and MOVK already imply a shift 199 // (e.g. :gottprel_g1: is always going to be "lsl #16") so it should not be 200 // printed. 201 if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi || 202 Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) && 203 MI->getOperand(1).isExpr()) { 204 if (Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi) 205 O << "\tmovz\t"; 206 else 207 O << "\tmovn\t"; 208 209 O << getRegisterName(MI->getOperand(0).getReg()) << ", #"; 210 MI->getOperand(1).getExpr()->print(O, &MAI); 211 return; 212 } 213 214 if ((Opcode == AArch64::MOVKXi || Opcode == AArch64::MOVKWi) && 215 MI->getOperand(2).isExpr()) { 216 O << "\tmovk\t" << getRegisterName(MI->getOperand(0).getReg()) << ", #"; 217 MI->getOperand(2).getExpr()->print(O, &MAI); 218 return; 219 } 220 221 if (!printAliasInstr(MI, STI, O)) 222 printInstruction(MI, STI, O); 223 224 printAnnotation(O, Annot); 225 } 226 227 static bool isTblTbxInstruction(unsigned Opcode, StringRef &Layout, 228 bool &IsTbx) { 229 switch (Opcode) { 230 case AArch64::TBXv8i8One: 231 case AArch64::TBXv8i8Two: 232 case AArch64::TBXv8i8Three: 233 case AArch64::TBXv8i8Four: 234 IsTbx = true; 235 Layout = ".8b"; 236 return true; 237 case AArch64::TBLv8i8One: 238 case AArch64::TBLv8i8Two: 239 case AArch64::TBLv8i8Three: 240 case AArch64::TBLv8i8Four: 241 IsTbx = false; 242 Layout = ".8b"; 243 return true; 244 case AArch64::TBXv16i8One: 245 case AArch64::TBXv16i8Two: 246 case AArch64::TBXv16i8Three: 247 case AArch64::TBXv16i8Four: 248 IsTbx = true; 249 Layout = ".16b"; 250 return true; 251 case AArch64::TBLv16i8One: 252 case AArch64::TBLv16i8Two: 253 case AArch64::TBLv16i8Three: 254 case AArch64::TBLv16i8Four: 255 IsTbx = false; 256 Layout = ".16b"; 257 return true; 258 default: 259 return false; 260 } 261 } 262 263 struct LdStNInstrDesc { 264 unsigned Opcode; 265 const char *Mnemonic; 266 const char *Layout; 267 int ListOperand; 268 bool HasLane; 269 int NaturalOffset; 270 }; 271 272 static const LdStNInstrDesc LdStNInstInfo[] = { 273 { AArch64::LD1i8, "ld1", ".b", 1, true, 0 }, 274 { AArch64::LD1i16, "ld1", ".h", 1, true, 0 }, 275 { AArch64::LD1i32, "ld1", ".s", 1, true, 0 }, 276 { AArch64::LD1i64, "ld1", ".d", 1, true, 0 }, 277 { AArch64::LD1i8_POST, "ld1", ".b", 2, true, 1 }, 278 { AArch64::LD1i16_POST, "ld1", ".h", 2, true, 2 }, 279 { AArch64::LD1i32_POST, "ld1", ".s", 2, true, 4 }, 280 { AArch64::LD1i64_POST, "ld1", ".d", 2, true, 8 }, 281 { AArch64::LD1Rv16b, "ld1r", ".16b", 0, false, 0 }, 282 { AArch64::LD1Rv8h, "ld1r", ".8h", 0, false, 0 }, 283 { AArch64::LD1Rv4s, "ld1r", ".4s", 0, false, 0 }, 284 { AArch64::LD1Rv2d, "ld1r", ".2d", 0, false, 0 }, 285 { AArch64::LD1Rv8b, "ld1r", ".8b", 0, false, 0 }, 286 { AArch64::LD1Rv4h, "ld1r", ".4h", 0, false, 0 }, 287 { AArch64::LD1Rv2s, "ld1r", ".2s", 0, false, 0 }, 288 { AArch64::LD1Rv1d, "ld1r", ".1d", 0, false, 0 }, 289 { AArch64::LD1Rv16b_POST, "ld1r", ".16b", 1, false, 1 }, 290 { AArch64::LD1Rv8h_POST, "ld1r", ".8h", 1, false, 2 }, 291 { AArch64::LD1Rv4s_POST, "ld1r", ".4s", 1, false, 4 }, 292 { AArch64::LD1Rv2d_POST, "ld1r", ".2d", 1, false, 8 }, 293 { AArch64::LD1Rv8b_POST, "ld1r", ".8b", 1, false, 1 }, 294 { AArch64::LD1Rv4h_POST, "ld1r", ".4h", 1, false, 2 }, 295 { AArch64::LD1Rv2s_POST, "ld1r", ".2s", 1, false, 4 }, 296 { AArch64::LD1Rv1d_POST, "ld1r", ".1d", 1, false, 8 }, 297 { AArch64::LD1Onev16b, "ld1", ".16b", 0, false, 0 }, 298 { AArch64::LD1Onev8h, "ld1", ".8h", 0, false, 0 }, 299 { AArch64::LD1Onev4s, "ld1", ".4s", 0, false, 0 }, 300 { AArch64::LD1Onev2d, "ld1", ".2d", 0, false, 0 }, 301 { AArch64::LD1Onev8b, "ld1", ".8b", 0, false, 0 }, 302 { AArch64::LD1Onev4h, "ld1", ".4h", 0, false, 0 }, 303 { AArch64::LD1Onev2s, "ld1", ".2s", 0, false, 0 }, 304 { AArch64::LD1Onev1d, "ld1", ".1d", 0, false, 0 }, 305 { AArch64::LD1Onev16b_POST, "ld1", ".16b", 1, false, 16 }, 306 { AArch64::LD1Onev8h_POST, "ld1", ".8h", 1, false, 16 }, 307 { AArch64::LD1Onev4s_POST, "ld1", ".4s", 1, false, 16 }, 308 { AArch64::LD1Onev2d_POST, "ld1", ".2d", 1, false, 16 }, 309 { AArch64::LD1Onev8b_POST, "ld1", ".8b", 1, false, 8 }, 310 { AArch64::LD1Onev4h_POST, "ld1", ".4h", 1, false, 8 }, 311 { AArch64::LD1Onev2s_POST, "ld1", ".2s", 1, false, 8 }, 312 { AArch64::LD1Onev1d_POST, "ld1", ".1d", 1, false, 8 }, 313 { AArch64::LD1Twov16b, "ld1", ".16b", 0, false, 0 }, 314 { AArch64::LD1Twov8h, "ld1", ".8h", 0, false, 0 }, 315 { AArch64::LD1Twov4s, "ld1", ".4s", 0, false, 0 }, 316 { AArch64::LD1Twov2d, "ld1", ".2d", 0, false, 0 }, 317 { AArch64::LD1Twov8b, "ld1", ".8b", 0, false, 0 }, 318 { AArch64::LD1Twov4h, "ld1", ".4h", 0, false, 0 }, 319 { AArch64::LD1Twov2s, "ld1", ".2s", 0, false, 0 }, 320 { AArch64::LD1Twov1d, "ld1", ".1d", 0, false, 0 }, 321 { AArch64::LD1Twov16b_POST, "ld1", ".16b", 1, false, 32 }, 322 { AArch64::LD1Twov8h_POST, "ld1", ".8h", 1, false, 32 }, 323 { AArch64::LD1Twov4s_POST, "ld1", ".4s", 1, false, 32 }, 324 { AArch64::LD1Twov2d_POST, "ld1", ".2d", 1, false, 32 }, 325 { AArch64::LD1Twov8b_POST, "ld1", ".8b", 1, false, 16 }, 326 { AArch64::LD1Twov4h_POST, "ld1", ".4h", 1, false, 16 }, 327 { AArch64::LD1Twov2s_POST, "ld1", ".2s", 1, false, 16 }, 328 { AArch64::LD1Twov1d_POST, "ld1", ".1d", 1, false, 16 }, 329 { AArch64::LD1Threev16b, "ld1", ".16b", 0, false, 0 }, 330 { AArch64::LD1Threev8h, "ld1", ".8h", 0, false, 0 }, 331 { AArch64::LD1Threev4s, "ld1", ".4s", 0, false, 0 }, 332 { AArch64::LD1Threev2d, "ld1", ".2d", 0, false, 0 }, 333 { AArch64::LD1Threev8b, "ld1", ".8b", 0, false, 0 }, 334 { AArch64::LD1Threev4h, "ld1", ".4h", 0, false, 0 }, 335 { AArch64::LD1Threev2s, "ld1", ".2s", 0, false, 0 }, 336 { AArch64::LD1Threev1d, "ld1", ".1d", 0, false, 0 }, 337 { AArch64::LD1Threev16b_POST, "ld1", ".16b", 1, false, 48 }, 338 { AArch64::LD1Threev8h_POST, "ld1", ".8h", 1, false, 48 }, 339 { AArch64::LD1Threev4s_POST, "ld1", ".4s", 1, false, 48 }, 340 { AArch64::LD1Threev2d_POST, "ld1", ".2d", 1, false, 48 }, 341 { AArch64::LD1Threev8b_POST, "ld1", ".8b", 1, false, 24 }, 342 { AArch64::LD1Threev4h_POST, "ld1", ".4h", 1, false, 24 }, 343 { AArch64::LD1Threev2s_POST, "ld1", ".2s", 1, false, 24 }, 344 { AArch64::LD1Threev1d_POST, "ld1", ".1d", 1, false, 24 }, 345 { AArch64::LD1Fourv16b, "ld1", ".16b", 0, false, 0 }, 346 { AArch64::LD1Fourv8h, "ld1", ".8h", 0, false, 0 }, 347 { AArch64::LD1Fourv4s, "ld1", ".4s", 0, false, 0 }, 348 { AArch64::LD1Fourv2d, "ld1", ".2d", 0, false, 0 }, 349 { AArch64::LD1Fourv8b, "ld1", ".8b", 0, false, 0 }, 350 { AArch64::LD1Fourv4h, "ld1", ".4h", 0, false, 0 }, 351 { AArch64::LD1Fourv2s, "ld1", ".2s", 0, false, 0 }, 352 { AArch64::LD1Fourv1d, "ld1", ".1d", 0, false, 0 }, 353 { AArch64::LD1Fourv16b_POST, "ld1", ".16b", 1, false, 64 }, 354 { AArch64::LD1Fourv8h_POST, "ld1", ".8h", 1, false, 64 }, 355 { AArch64::LD1Fourv4s_POST, "ld1", ".4s", 1, false, 64 }, 356 { AArch64::LD1Fourv2d_POST, "ld1", ".2d", 1, false, 64 }, 357 { AArch64::LD1Fourv8b_POST, "ld1", ".8b", 1, false, 32 }, 358 { AArch64::LD1Fourv4h_POST, "ld1", ".4h", 1, false, 32 }, 359 { AArch64::LD1Fourv2s_POST, "ld1", ".2s", 1, false, 32 }, 360 { AArch64::LD1Fourv1d_POST, "ld1", ".1d", 1, false, 32 }, 361 { AArch64::LD2i8, "ld2", ".b", 1, true, 0 }, 362 { AArch64::LD2i16, "ld2", ".h", 1, true, 0 }, 363 { AArch64::LD2i32, "ld2", ".s", 1, true, 0 }, 364 { AArch64::LD2i64, "ld2", ".d", 1, true, 0 }, 365 { AArch64::LD2i8_POST, "ld2", ".b", 2, true, 2 }, 366 { AArch64::LD2i16_POST, "ld2", ".h", 2, true, 4 }, 367 { AArch64::LD2i32_POST, "ld2", ".s", 2, true, 8 }, 368 { AArch64::LD2i64_POST, "ld2", ".d", 2, true, 16 }, 369 { AArch64::LD2Rv16b, "ld2r", ".16b", 0, false, 0 }, 370 { AArch64::LD2Rv8h, "ld2r", ".8h", 0, false, 0 }, 371 { AArch64::LD2Rv4s, "ld2r", ".4s", 0, false, 0 }, 372 { AArch64::LD2Rv2d, "ld2r", ".2d", 0, false, 0 }, 373 { AArch64::LD2Rv8b, "ld2r", ".8b", 0, false, 0 }, 374 { AArch64::LD2Rv4h, "ld2r", ".4h", 0, false, 0 }, 375 { AArch64::LD2Rv2s, "ld2r", ".2s", 0, false, 0 }, 376 { AArch64::LD2Rv1d, "ld2r", ".1d", 0, false, 0 }, 377 { AArch64::LD2Rv16b_POST, "ld2r", ".16b", 1, false, 2 }, 378 { AArch64::LD2Rv8h_POST, "ld2r", ".8h", 1, false, 4 }, 379 { AArch64::LD2Rv4s_POST, "ld2r", ".4s", 1, false, 8 }, 380 { AArch64::LD2Rv2d_POST, "ld2r", ".2d", 1, false, 16 }, 381 { AArch64::LD2Rv8b_POST, "ld2r", ".8b", 1, false, 2 }, 382 { AArch64::LD2Rv4h_POST, "ld2r", ".4h", 1, false, 4 }, 383 { AArch64::LD2Rv2s_POST, "ld2r", ".2s", 1, false, 8 }, 384 { AArch64::LD2Rv1d_POST, "ld2r", ".1d", 1, false, 16 }, 385 { AArch64::LD2Twov16b, "ld2", ".16b", 0, false, 0 }, 386 { AArch64::LD2Twov8h, "ld2", ".8h", 0, false, 0 }, 387 { AArch64::LD2Twov4s, "ld2", ".4s", 0, false, 0 }, 388 { AArch64::LD2Twov2d, "ld2", ".2d", 0, false, 0 }, 389 { AArch64::LD2Twov8b, "ld2", ".8b", 0, false, 0 }, 390 { AArch64::LD2Twov4h, "ld2", ".4h", 0, false, 0 }, 391 { AArch64::LD2Twov2s, "ld2", ".2s", 0, false, 0 }, 392 { AArch64::LD2Twov16b_POST, "ld2", ".16b", 1, false, 32 }, 393 { AArch64::LD2Twov8h_POST, "ld2", ".8h", 1, false, 32 }, 394 { AArch64::LD2Twov4s_POST, "ld2", ".4s", 1, false, 32 }, 395 { AArch64::LD2Twov2d_POST, "ld2", ".2d", 1, false, 32 }, 396 { AArch64::LD2Twov8b_POST, "ld2", ".8b", 1, false, 16 }, 397 { AArch64::LD2Twov4h_POST, "ld2", ".4h", 1, false, 16 }, 398 { AArch64::LD2Twov2s_POST, "ld2", ".2s", 1, false, 16 }, 399 { AArch64::LD3i8, "ld3", ".b", 1, true, 0 }, 400 { AArch64::LD3i16, "ld3", ".h", 1, true, 0 }, 401 { AArch64::LD3i32, "ld3", ".s", 1, true, 0 }, 402 { AArch64::LD3i64, "ld3", ".d", 1, true, 0 }, 403 { AArch64::LD3i8_POST, "ld3", ".b", 2, true, 3 }, 404 { AArch64::LD3i16_POST, "ld3", ".h", 2, true, 6 }, 405 { AArch64::LD3i32_POST, "ld3", ".s", 2, true, 12 }, 406 { AArch64::LD3i64_POST, "ld3", ".d", 2, true, 24 }, 407 { AArch64::LD3Rv16b, "ld3r", ".16b", 0, false, 0 }, 408 { AArch64::LD3Rv8h, "ld3r", ".8h", 0, false, 0 }, 409 { AArch64::LD3Rv4s, "ld3r", ".4s", 0, false, 0 }, 410 { AArch64::LD3Rv2d, "ld3r", ".2d", 0, false, 0 }, 411 { AArch64::LD3Rv8b, "ld3r", ".8b", 0, false, 0 }, 412 { AArch64::LD3Rv4h, "ld3r", ".4h", 0, false, 0 }, 413 { AArch64::LD3Rv2s, "ld3r", ".2s", 0, false, 0 }, 414 { AArch64::LD3Rv1d, "ld3r", ".1d", 0, false, 0 }, 415 { AArch64::LD3Rv16b_POST, "ld3r", ".16b", 1, false, 3 }, 416 { AArch64::LD3Rv8h_POST, "ld3r", ".8h", 1, false, 6 }, 417 { AArch64::LD3Rv4s_POST, "ld3r", ".4s", 1, false, 12 }, 418 { AArch64::LD3Rv2d_POST, "ld3r", ".2d", 1, false, 24 }, 419 { AArch64::LD3Rv8b_POST, "ld3r", ".8b", 1, false, 3 }, 420 { AArch64::LD3Rv4h_POST, "ld3r", ".4h", 1, false, 6 }, 421 { AArch64::LD3Rv2s_POST, "ld3r", ".2s", 1, false, 12 }, 422 { AArch64::LD3Rv1d_POST, "ld3r", ".1d", 1, false, 24 }, 423 { AArch64::LD3Threev16b, "ld3", ".16b", 0, false, 0 }, 424 { AArch64::LD3Threev8h, "ld3", ".8h", 0, false, 0 }, 425 { AArch64::LD3Threev4s, "ld3", ".4s", 0, false, 0 }, 426 { AArch64::LD3Threev2d, "ld3", ".2d", 0, false, 0 }, 427 { AArch64::LD3Threev8b, "ld3", ".8b", 0, false, 0 }, 428 { AArch64::LD3Threev4h, "ld3", ".4h", 0, false, 0 }, 429 { AArch64::LD3Threev2s, "ld3", ".2s", 0, false, 0 }, 430 { AArch64::LD3Threev16b_POST, "ld3", ".16b", 1, false, 48 }, 431 { AArch64::LD3Threev8h_POST, "ld3", ".8h", 1, false, 48 }, 432 { AArch64::LD3Threev4s_POST, "ld3", ".4s", 1, false, 48 }, 433 { AArch64::LD3Threev2d_POST, "ld3", ".2d", 1, false, 48 }, 434 { AArch64::LD3Threev8b_POST, "ld3", ".8b", 1, false, 24 }, 435 { AArch64::LD3Threev4h_POST, "ld3", ".4h", 1, false, 24 }, 436 { AArch64::LD3Threev2s_POST, "ld3", ".2s", 1, false, 24 }, 437 { AArch64::LD4i8, "ld4", ".b", 1, true, 0 }, 438 { AArch64::LD4i16, "ld4", ".h", 1, true, 0 }, 439 { AArch64::LD4i32, "ld4", ".s", 1, true, 0 }, 440 { AArch64::LD4i64, "ld4", ".d", 1, true, 0 }, 441 { AArch64::LD4i8_POST, "ld4", ".b", 2, true, 4 }, 442 { AArch64::LD4i16_POST, "ld4", ".h", 2, true, 8 }, 443 { AArch64::LD4i32_POST, "ld4", ".s", 2, true, 16 }, 444 { AArch64::LD4i64_POST, "ld4", ".d", 2, true, 32 }, 445 { AArch64::LD4Rv16b, "ld4r", ".16b", 0, false, 0 }, 446 { AArch64::LD4Rv8h, "ld4r", ".8h", 0, false, 0 }, 447 { AArch64::LD4Rv4s, "ld4r", ".4s", 0, false, 0 }, 448 { AArch64::LD4Rv2d, "ld4r", ".2d", 0, false, 0 }, 449 { AArch64::LD4Rv8b, "ld4r", ".8b", 0, false, 0 }, 450 { AArch64::LD4Rv4h, "ld4r", ".4h", 0, false, 0 }, 451 { AArch64::LD4Rv2s, "ld4r", ".2s", 0, false, 0 }, 452 { AArch64::LD4Rv1d, "ld4r", ".1d", 0, false, 0 }, 453 { AArch64::LD4Rv16b_POST, "ld4r", ".16b", 1, false, 4 }, 454 { AArch64::LD4Rv8h_POST, "ld4r", ".8h", 1, false, 8 }, 455 { AArch64::LD4Rv4s_POST, "ld4r", ".4s", 1, false, 16 }, 456 { AArch64::LD4Rv2d_POST, "ld4r", ".2d", 1, false, 32 }, 457 { AArch64::LD4Rv8b_POST, "ld4r", ".8b", 1, false, 4 }, 458 { AArch64::LD4Rv4h_POST, "ld4r", ".4h", 1, false, 8 }, 459 { AArch64::LD4Rv2s_POST, "ld4r", ".2s", 1, false, 16 }, 460 { AArch64::LD4Rv1d_POST, "ld4r", ".1d", 1, false, 32 }, 461 { AArch64::LD4Fourv16b, "ld4", ".16b", 0, false, 0 }, 462 { AArch64::LD4Fourv8h, "ld4", ".8h", 0, false, 0 }, 463 { AArch64::LD4Fourv4s, "ld4", ".4s", 0, false, 0 }, 464 { AArch64::LD4Fourv2d, "ld4", ".2d", 0, false, 0 }, 465 { AArch64::LD4Fourv8b, "ld4", ".8b", 0, false, 0 }, 466 { AArch64::LD4Fourv4h, "ld4", ".4h", 0, false, 0 }, 467 { AArch64::LD4Fourv2s, "ld4", ".2s", 0, false, 0 }, 468 { AArch64::LD4Fourv16b_POST, "ld4", ".16b", 1, false, 64 }, 469 { AArch64::LD4Fourv8h_POST, "ld4", ".8h", 1, false, 64 }, 470 { AArch64::LD4Fourv4s_POST, "ld4", ".4s", 1, false, 64 }, 471 { AArch64::LD4Fourv2d_POST, "ld4", ".2d", 1, false, 64 }, 472 { AArch64::LD4Fourv8b_POST, "ld4", ".8b", 1, false, 32 }, 473 { AArch64::LD4Fourv4h_POST, "ld4", ".4h", 1, false, 32 }, 474 { AArch64::LD4Fourv2s_POST, "ld4", ".2s", 1, false, 32 }, 475 { AArch64::ST1i8, "st1", ".b", 0, true, 0 }, 476 { AArch64::ST1i16, "st1", ".h", 0, true, 0 }, 477 { AArch64::ST1i32, "st1", ".s", 0, true, 0 }, 478 { AArch64::ST1i64, "st1", ".d", 0, true, 0 }, 479 { AArch64::ST1i8_POST, "st1", ".b", 1, true, 1 }, 480 { AArch64::ST1i16_POST, "st1", ".h", 1, true, 2 }, 481 { AArch64::ST1i32_POST, "st1", ".s", 1, true, 4 }, 482 { AArch64::ST1i64_POST, "st1", ".d", 1, true, 8 }, 483 { AArch64::ST1Onev16b, "st1", ".16b", 0, false, 0 }, 484 { AArch64::ST1Onev8h, "st1", ".8h", 0, false, 0 }, 485 { AArch64::ST1Onev4s, "st1", ".4s", 0, false, 0 }, 486 { AArch64::ST1Onev2d, "st1", ".2d", 0, false, 0 }, 487 { AArch64::ST1Onev8b, "st1", ".8b", 0, false, 0 }, 488 { AArch64::ST1Onev4h, "st1", ".4h", 0, false, 0 }, 489 { AArch64::ST1Onev2s, "st1", ".2s", 0, false, 0 }, 490 { AArch64::ST1Onev1d, "st1", ".1d", 0, false, 0 }, 491 { AArch64::ST1Onev16b_POST, "st1", ".16b", 1, false, 16 }, 492 { AArch64::ST1Onev8h_POST, "st1", ".8h", 1, false, 16 }, 493 { AArch64::ST1Onev4s_POST, "st1", ".4s", 1, false, 16 }, 494 { AArch64::ST1Onev2d_POST, "st1", ".2d", 1, false, 16 }, 495 { AArch64::ST1Onev8b_POST, "st1", ".8b", 1, false, 8 }, 496 { AArch64::ST1Onev4h_POST, "st1", ".4h", 1, false, 8 }, 497 { AArch64::ST1Onev2s_POST, "st1", ".2s", 1, false, 8 }, 498 { AArch64::ST1Onev1d_POST, "st1", ".1d", 1, false, 8 }, 499 { AArch64::ST1Twov16b, "st1", ".16b", 0, false, 0 }, 500 { AArch64::ST1Twov8h, "st1", ".8h", 0, false, 0 }, 501 { AArch64::ST1Twov4s, "st1", ".4s", 0, false, 0 }, 502 { AArch64::ST1Twov2d, "st1", ".2d", 0, false, 0 }, 503 { AArch64::ST1Twov8b, "st1", ".8b", 0, false, 0 }, 504 { AArch64::ST1Twov4h, "st1", ".4h", 0, false, 0 }, 505 { AArch64::ST1Twov2s, "st1", ".2s", 0, false, 0 }, 506 { AArch64::ST1Twov1d, "st1", ".1d", 0, false, 0 }, 507 { AArch64::ST1Twov16b_POST, "st1", ".16b", 1, false, 32 }, 508 { AArch64::ST1Twov8h_POST, "st1", ".8h", 1, false, 32 }, 509 { AArch64::ST1Twov4s_POST, "st1", ".4s", 1, false, 32 }, 510 { AArch64::ST1Twov2d_POST, "st1", ".2d", 1, false, 32 }, 511 { AArch64::ST1Twov8b_POST, "st1", ".8b", 1, false, 16 }, 512 { AArch64::ST1Twov4h_POST, "st1", ".4h", 1, false, 16 }, 513 { AArch64::ST1Twov2s_POST, "st1", ".2s", 1, false, 16 }, 514 { AArch64::ST1Twov1d_POST, "st1", ".1d", 1, false, 16 }, 515 { AArch64::ST1Threev16b, "st1", ".16b", 0, false, 0 }, 516 { AArch64::ST1Threev8h, "st1", ".8h", 0, false, 0 }, 517 { AArch64::ST1Threev4s, "st1", ".4s", 0, false, 0 }, 518 { AArch64::ST1Threev2d, "st1", ".2d", 0, false, 0 }, 519 { AArch64::ST1Threev8b, "st1", ".8b", 0, false, 0 }, 520 { AArch64::ST1Threev4h, "st1", ".4h", 0, false, 0 }, 521 { AArch64::ST1Threev2s, "st1", ".2s", 0, false, 0 }, 522 { AArch64::ST1Threev1d, "st1", ".1d", 0, false, 0 }, 523 { AArch64::ST1Threev16b_POST, "st1", ".16b", 1, false, 48 }, 524 { AArch64::ST1Threev8h_POST, "st1", ".8h", 1, false, 48 }, 525 { AArch64::ST1Threev4s_POST, "st1", ".4s", 1, false, 48 }, 526 { AArch64::ST1Threev2d_POST, "st1", ".2d", 1, false, 48 }, 527 { AArch64::ST1Threev8b_POST, "st1", ".8b", 1, false, 24 }, 528 { AArch64::ST1Threev4h_POST, "st1", ".4h", 1, false, 24 }, 529 { AArch64::ST1Threev2s_POST, "st1", ".2s", 1, false, 24 }, 530 { AArch64::ST1Threev1d_POST, "st1", ".1d", 1, false, 24 }, 531 { AArch64::ST1Fourv16b, "st1", ".16b", 0, false, 0 }, 532 { AArch64::ST1Fourv8h, "st1", ".8h", 0, false, 0 }, 533 { AArch64::ST1Fourv4s, "st1", ".4s", 0, false, 0 }, 534 { AArch64::ST1Fourv2d, "st1", ".2d", 0, false, 0 }, 535 { AArch64::ST1Fourv8b, "st1", ".8b", 0, false, 0 }, 536 { AArch64::ST1Fourv4h, "st1", ".4h", 0, false, 0 }, 537 { AArch64::ST1Fourv2s, "st1", ".2s", 0, false, 0 }, 538 { AArch64::ST1Fourv1d, "st1", ".1d", 0, false, 0 }, 539 { AArch64::ST1Fourv16b_POST, "st1", ".16b", 1, false, 64 }, 540 { AArch64::ST1Fourv8h_POST, "st1", ".8h", 1, false, 64 }, 541 { AArch64::ST1Fourv4s_POST, "st1", ".4s", 1, false, 64 }, 542 { AArch64::ST1Fourv2d_POST, "st1", ".2d", 1, false, 64 }, 543 { AArch64::ST1Fourv8b_POST, "st1", ".8b", 1, false, 32 }, 544 { AArch64::ST1Fourv4h_POST, "st1", ".4h", 1, false, 32 }, 545 { AArch64::ST1Fourv2s_POST, "st1", ".2s", 1, false, 32 }, 546 { AArch64::ST1Fourv1d_POST, "st1", ".1d", 1, false, 32 }, 547 { AArch64::ST2i8, "st2", ".b", 0, true, 0 }, 548 { AArch64::ST2i16, "st2", ".h", 0, true, 0 }, 549 { AArch64::ST2i32, "st2", ".s", 0, true, 0 }, 550 { AArch64::ST2i64, "st2", ".d", 0, true, 0 }, 551 { AArch64::ST2i8_POST, "st2", ".b", 1, true, 2 }, 552 { AArch64::ST2i16_POST, "st2", ".h", 1, true, 4 }, 553 { AArch64::ST2i32_POST, "st2", ".s", 1, true, 8 }, 554 { AArch64::ST2i64_POST, "st2", ".d", 1, true, 16 }, 555 { AArch64::ST2Twov16b, "st2", ".16b", 0, false, 0 }, 556 { AArch64::ST2Twov8h, "st2", ".8h", 0, false, 0 }, 557 { AArch64::ST2Twov4s, "st2", ".4s", 0, false, 0 }, 558 { AArch64::ST2Twov2d, "st2", ".2d", 0, false, 0 }, 559 { AArch64::ST2Twov8b, "st2", ".8b", 0, false, 0 }, 560 { AArch64::ST2Twov4h, "st2", ".4h", 0, false, 0 }, 561 { AArch64::ST2Twov2s, "st2", ".2s", 0, false, 0 }, 562 { AArch64::ST2Twov16b_POST, "st2", ".16b", 1, false, 32 }, 563 { AArch64::ST2Twov8h_POST, "st2", ".8h", 1, false, 32 }, 564 { AArch64::ST2Twov4s_POST, "st2", ".4s", 1, false, 32 }, 565 { AArch64::ST2Twov2d_POST, "st2", ".2d", 1, false, 32 }, 566 { AArch64::ST2Twov8b_POST, "st2", ".8b", 1, false, 16 }, 567 { AArch64::ST2Twov4h_POST, "st2", ".4h", 1, false, 16 }, 568 { AArch64::ST2Twov2s_POST, "st2", ".2s", 1, false, 16 }, 569 { AArch64::ST3i8, "st3", ".b", 0, true, 0 }, 570 { AArch64::ST3i16, "st3", ".h", 0, true, 0 }, 571 { AArch64::ST3i32, "st3", ".s", 0, true, 0 }, 572 { AArch64::ST3i64, "st3", ".d", 0, true, 0 }, 573 { AArch64::ST3i8_POST, "st3", ".b", 1, true, 3 }, 574 { AArch64::ST3i16_POST, "st3", ".h", 1, true, 6 }, 575 { AArch64::ST3i32_POST, "st3", ".s", 1, true, 12 }, 576 { AArch64::ST3i64_POST, "st3", ".d", 1, true, 24 }, 577 { AArch64::ST3Threev16b, "st3", ".16b", 0, false, 0 }, 578 { AArch64::ST3Threev8h, "st3", ".8h", 0, false, 0 }, 579 { AArch64::ST3Threev4s, "st3", ".4s", 0, false, 0 }, 580 { AArch64::ST3Threev2d, "st3", ".2d", 0, false, 0 }, 581 { AArch64::ST3Threev8b, "st3", ".8b", 0, false, 0 }, 582 { AArch64::ST3Threev4h, "st3", ".4h", 0, false, 0 }, 583 { AArch64::ST3Threev2s, "st3", ".2s", 0, false, 0 }, 584 { AArch64::ST3Threev16b_POST, "st3", ".16b", 1, false, 48 }, 585 { AArch64::ST3Threev8h_POST, "st3", ".8h", 1, false, 48 }, 586 { AArch64::ST3Threev4s_POST, "st3", ".4s", 1, false, 48 }, 587 { AArch64::ST3Threev2d_POST, "st3", ".2d", 1, false, 48 }, 588 { AArch64::ST3Threev8b_POST, "st3", ".8b", 1, false, 24 }, 589 { AArch64::ST3Threev4h_POST, "st3", ".4h", 1, false, 24 }, 590 { AArch64::ST3Threev2s_POST, "st3", ".2s", 1, false, 24 }, 591 { AArch64::ST4i8, "st4", ".b", 0, true, 0 }, 592 { AArch64::ST4i16, "st4", ".h", 0, true, 0 }, 593 { AArch64::ST4i32, "st4", ".s", 0, true, 0 }, 594 { AArch64::ST4i64, "st4", ".d", 0, true, 0 }, 595 { AArch64::ST4i8_POST, "st4", ".b", 1, true, 4 }, 596 { AArch64::ST4i16_POST, "st4", ".h", 1, true, 8 }, 597 { AArch64::ST4i32_POST, "st4", ".s", 1, true, 16 }, 598 { AArch64::ST4i64_POST, "st4", ".d", 1, true, 32 }, 599 { AArch64::ST4Fourv16b, "st4", ".16b", 0, false, 0 }, 600 { AArch64::ST4Fourv8h, "st4", ".8h", 0, false, 0 }, 601 { AArch64::ST4Fourv4s, "st4", ".4s", 0, false, 0 }, 602 { AArch64::ST4Fourv2d, "st4", ".2d", 0, false, 0 }, 603 { AArch64::ST4Fourv8b, "st4", ".8b", 0, false, 0 }, 604 { AArch64::ST4Fourv4h, "st4", ".4h", 0, false, 0 }, 605 { AArch64::ST4Fourv2s, "st4", ".2s", 0, false, 0 }, 606 { AArch64::ST4Fourv16b_POST, "st4", ".16b", 1, false, 64 }, 607 { AArch64::ST4Fourv8h_POST, "st4", ".8h", 1, false, 64 }, 608 { AArch64::ST4Fourv4s_POST, "st4", ".4s", 1, false, 64 }, 609 { AArch64::ST4Fourv2d_POST, "st4", ".2d", 1, false, 64 }, 610 { AArch64::ST4Fourv8b_POST, "st4", ".8b", 1, false, 32 }, 611 { AArch64::ST4Fourv4h_POST, "st4", ".4h", 1, false, 32 }, 612 { AArch64::ST4Fourv2s_POST, "st4", ".2s", 1, false, 32 }, 613 }; 614 615 static const LdStNInstrDesc *getLdStNInstrDesc(unsigned Opcode) { 616 unsigned Idx; 617 for (Idx = 0; Idx != array_lengthof(LdStNInstInfo); ++Idx) 618 if (LdStNInstInfo[Idx].Opcode == Opcode) 619 return &LdStNInstInfo[Idx]; 620 621 return nullptr; 622 } 623 624 void AArch64AppleInstPrinter::printInst(const MCInst *MI, raw_ostream &O, 625 StringRef Annot, 626 const MCSubtargetInfo &STI) { 627 unsigned Opcode = MI->getOpcode(); 628 StringRef Layout, Mnemonic; 629 630 bool IsTbx; 631 if (isTblTbxInstruction(MI->getOpcode(), Layout, IsTbx)) { 632 O << "\t" << (IsTbx ? "tbx" : "tbl") << Layout << '\t' 633 << getRegisterName(MI->getOperand(0).getReg(), AArch64::vreg) << ", "; 634 635 unsigned ListOpNum = IsTbx ? 2 : 1; 636 printVectorList(MI, ListOpNum, STI, O, ""); 637 638 O << ", " 639 << getRegisterName(MI->getOperand(ListOpNum + 1).getReg(), AArch64::vreg); 640 printAnnotation(O, Annot); 641 return; 642 } 643 644 if (const LdStNInstrDesc *LdStDesc = getLdStNInstrDesc(Opcode)) { 645 O << "\t" << LdStDesc->Mnemonic << LdStDesc->Layout << '\t'; 646 647 // Now onto the operands: first a vector list with possible lane 648 // specifier. E.g. { v0 }[2] 649 int OpNum = LdStDesc->ListOperand; 650 printVectorList(MI, OpNum++, STI, O, ""); 651 652 if (LdStDesc->HasLane) 653 O << '[' << MI->getOperand(OpNum++).getImm() << ']'; 654 655 // Next the address: [xN] 656 unsigned AddrReg = MI->getOperand(OpNum++).getReg(); 657 O << ", [" << getRegisterName(AddrReg) << ']'; 658 659 // Finally, there might be a post-indexed offset. 660 if (LdStDesc->NaturalOffset != 0) { 661 unsigned Reg = MI->getOperand(OpNum++).getReg(); 662 if (Reg != AArch64::XZR) 663 O << ", " << getRegisterName(Reg); 664 else { 665 assert(LdStDesc->NaturalOffset && "no offset on post-inc instruction?"); 666 O << ", #" << LdStDesc->NaturalOffset; 667 } 668 } 669 670 printAnnotation(O, Annot); 671 return; 672 } 673 674 AArch64InstPrinter::printInst(MI, O, Annot, STI); 675 } 676 677 bool AArch64InstPrinter::printSysAlias(const MCInst *MI, 678 const MCSubtargetInfo &STI, 679 raw_ostream &O) { 680 #ifndef NDEBUG 681 unsigned Opcode = MI->getOpcode(); 682 assert(Opcode == AArch64::SYSxt && "Invalid opcode for SYS alias!"); 683 #endif 684 685 const char *Asm = nullptr; 686 const MCOperand &Op1 = MI->getOperand(0); 687 const MCOperand &Cn = MI->getOperand(1); 688 const MCOperand &Cm = MI->getOperand(2); 689 const MCOperand &Op2 = MI->getOperand(3); 690 691 unsigned Op1Val = Op1.getImm(); 692 unsigned CnVal = Cn.getImm(); 693 unsigned CmVal = Cm.getImm(); 694 unsigned Op2Val = Op2.getImm(); 695 696 if (CnVal == 7) { 697 switch (CmVal) { 698 default: 699 break; 700 701 // IC aliases 702 case 1: 703 if (Op1Val == 0 && Op2Val == 0) 704 Asm = "ic\tialluis"; 705 break; 706 case 5: 707 if (Op1Val == 0 && Op2Val == 0) 708 Asm = "ic\tiallu"; 709 else if (Op1Val == 3 && Op2Val == 1) 710 Asm = "ic\tivau"; 711 break; 712 713 // DC aliases 714 case 4: 715 if (Op1Val == 3 && Op2Val == 1) 716 Asm = "dc\tzva"; 717 break; 718 case 6: 719 if (Op1Val == 0 && Op2Val == 1) 720 Asm = "dc\tivac"; 721 if (Op1Val == 0 && Op2Val == 2) 722 Asm = "dc\tisw"; 723 break; 724 case 10: 725 if (Op1Val == 3 && Op2Val == 1) 726 Asm = "dc\tcvac"; 727 else if (Op1Val == 0 && Op2Val == 2) 728 Asm = "dc\tcsw"; 729 break; 730 case 11: 731 if (Op1Val == 3 && Op2Val == 1) 732 Asm = "dc\tcvau"; 733 break; 734 case 12: 735 if (Op1Val == 3 && Op2Val == 1 && 736 (STI.getFeatureBits()[AArch64::HasV8_2aOps])) 737 Asm = "dc\tcvap"; 738 break; 739 case 14: 740 if (Op1Val == 3 && Op2Val == 1) 741 Asm = "dc\tcivac"; 742 else if (Op1Val == 0 && Op2Val == 2) 743 Asm = "dc\tcisw"; 744 break; 745 746 // AT aliases 747 case 8: 748 switch (Op1Val) { 749 default: 750 break; 751 case 0: 752 switch (Op2Val) { 753 default: 754 break; 755 case 0: Asm = "at\ts1e1r"; break; 756 case 1: Asm = "at\ts1e1w"; break; 757 case 2: Asm = "at\ts1e0r"; break; 758 case 3: Asm = "at\ts1e0w"; break; 759 } 760 break; 761 case 4: 762 switch (Op2Val) { 763 default: 764 break; 765 case 0: Asm = "at\ts1e2r"; break; 766 case 1: Asm = "at\ts1e2w"; break; 767 case 4: Asm = "at\ts12e1r"; break; 768 case 5: Asm = "at\ts12e1w"; break; 769 case 6: Asm = "at\ts12e0r"; break; 770 case 7: Asm = "at\ts12e0w"; break; 771 } 772 break; 773 case 6: 774 switch (Op2Val) { 775 default: 776 break; 777 case 0: Asm = "at\ts1e3r"; break; 778 case 1: Asm = "at\ts1e3w"; break; 779 } 780 break; 781 } 782 break; 783 case 9: 784 switch (Op1Val) { 785 default: 786 break; 787 case 0: 788 if (STI.getFeatureBits()[AArch64::HasV8_2aOps]) { 789 switch (Op2Val) { 790 default: 791 break; 792 case 0: Asm = "at\ts1e1rp"; break; 793 case 1: Asm = "at\ts1e1wp"; break; 794 } 795 } 796 break; 797 } 798 } 799 } else if (CnVal == 8) { 800 // TLBI aliases 801 switch (CmVal) { 802 default: 803 break; 804 case 3: 805 switch (Op1Val) { 806 default: 807 break; 808 case 0: 809 switch (Op2Val) { 810 default: 811 break; 812 case 0: Asm = "tlbi\tvmalle1is"; break; 813 case 1: Asm = "tlbi\tvae1is"; break; 814 case 2: Asm = "tlbi\taside1is"; break; 815 case 3: Asm = "tlbi\tvaae1is"; break; 816 case 5: Asm = "tlbi\tvale1is"; break; 817 case 7: Asm = "tlbi\tvaale1is"; break; 818 } 819 break; 820 case 4: 821 switch (Op2Val) { 822 default: 823 break; 824 case 0: Asm = "tlbi\talle2is"; break; 825 case 1: Asm = "tlbi\tvae2is"; break; 826 case 4: Asm = "tlbi\talle1is"; break; 827 case 5: Asm = "tlbi\tvale2is"; break; 828 case 6: Asm = "tlbi\tvmalls12e1is"; break; 829 } 830 break; 831 case 6: 832 switch (Op2Val) { 833 default: 834 break; 835 case 0: Asm = "tlbi\talle3is"; break; 836 case 1: Asm = "tlbi\tvae3is"; break; 837 case 5: Asm = "tlbi\tvale3is"; break; 838 } 839 break; 840 } 841 break; 842 case 0: 843 switch (Op1Val) { 844 default: 845 break; 846 case 4: 847 switch (Op2Val) { 848 default: 849 break; 850 case 1: Asm = "tlbi\tipas2e1is"; break; 851 case 5: Asm = "tlbi\tipas2le1is"; break; 852 } 853 break; 854 } 855 break; 856 case 4: 857 switch (Op1Val) { 858 default: 859 break; 860 case 4: 861 switch (Op2Val) { 862 default: 863 break; 864 case 1: Asm = "tlbi\tipas2e1"; break; 865 case 5: Asm = "tlbi\tipas2le1"; break; 866 } 867 break; 868 } 869 break; 870 case 7: 871 switch (Op1Val) { 872 default: 873 break; 874 case 0: 875 switch (Op2Val) { 876 default: 877 break; 878 case 0: Asm = "tlbi\tvmalle1"; break; 879 case 1: Asm = "tlbi\tvae1"; break; 880 case 2: Asm = "tlbi\taside1"; break; 881 case 3: Asm = "tlbi\tvaae1"; break; 882 case 5: Asm = "tlbi\tvale1"; break; 883 case 7: Asm = "tlbi\tvaale1"; break; 884 } 885 break; 886 case 4: 887 switch (Op2Val) { 888 default: 889 break; 890 case 0: Asm = "tlbi\talle2"; break; 891 case 1: Asm = "tlbi\tvae2"; break; 892 case 4: Asm = "tlbi\talle1"; break; 893 case 5: Asm = "tlbi\tvale2"; break; 894 case 6: Asm = "tlbi\tvmalls12e1"; break; 895 } 896 break; 897 case 6: 898 switch (Op2Val) { 899 default: 900 break; 901 case 0: Asm = "tlbi\talle3"; break; 902 case 1: Asm = "tlbi\tvae3"; break; 903 case 5: Asm = "tlbi\tvale3"; break; 904 } 905 break; 906 } 907 break; 908 } 909 } 910 911 if (Asm) { 912 unsigned Reg = MI->getOperand(4).getReg(); 913 914 O << '\t' << Asm; 915 if (StringRef(Asm).lower().find("all") == StringRef::npos) 916 O << ", " << getRegisterName(Reg); 917 } 918 919 return Asm != nullptr; 920 } 921 922 void AArch64InstPrinter::printOperand(const MCInst *MI, unsigned OpNo, 923 const MCSubtargetInfo &STI, 924 raw_ostream &O) { 925 const MCOperand &Op = MI->getOperand(OpNo); 926 if (Op.isReg()) { 927 unsigned Reg = Op.getReg(); 928 O << getRegisterName(Reg); 929 } else if (Op.isImm()) { 930 O << '#' << Op.getImm(); 931 } else { 932 assert(Op.isExpr() && "unknown operand kind in printOperand"); 933 Op.getExpr()->print(O, &MAI); 934 } 935 } 936 937 void AArch64InstPrinter::printHexImm(const MCInst *MI, unsigned OpNo, 938 const MCSubtargetInfo &STI, 939 raw_ostream &O) { 940 const MCOperand &Op = MI->getOperand(OpNo); 941 O << format("#%#llx", Op.getImm()); 942 } 943 944 void AArch64InstPrinter::printPostIncOperand(const MCInst *MI, unsigned OpNo, 945 unsigned Imm, raw_ostream &O) { 946 const MCOperand &Op = MI->getOperand(OpNo); 947 if (Op.isReg()) { 948 unsigned Reg = Op.getReg(); 949 if (Reg == AArch64::XZR) 950 O << "#" << Imm; 951 else 952 O << getRegisterName(Reg); 953 } else 954 llvm_unreachable("unknown operand kind in printPostIncOperand64"); 955 } 956 957 void AArch64InstPrinter::printVRegOperand(const MCInst *MI, unsigned OpNo, 958 const MCSubtargetInfo &STI, 959 raw_ostream &O) { 960 const MCOperand &Op = MI->getOperand(OpNo); 961 assert(Op.isReg() && "Non-register vreg operand!"); 962 unsigned Reg = Op.getReg(); 963 O << getRegisterName(Reg, AArch64::vreg); 964 } 965 966 void AArch64InstPrinter::printSysCROperand(const MCInst *MI, unsigned OpNo, 967 const MCSubtargetInfo &STI, 968 raw_ostream &O) { 969 const MCOperand &Op = MI->getOperand(OpNo); 970 assert(Op.isImm() && "System instruction C[nm] operands must be immediates!"); 971 O << "c" << Op.getImm(); 972 } 973 974 void AArch64InstPrinter::printAddSubImm(const MCInst *MI, unsigned OpNum, 975 const MCSubtargetInfo &STI, 976 raw_ostream &O) { 977 const MCOperand &MO = MI->getOperand(OpNum); 978 if (MO.isImm()) { 979 unsigned Val = (MO.getImm() & 0xfff); 980 assert(Val == MO.getImm() && "Add/sub immediate out of range!"); 981 unsigned Shift = 982 AArch64_AM::getShiftValue(MI->getOperand(OpNum + 1).getImm()); 983 O << '#' << Val; 984 if (Shift != 0) 985 printShifter(MI, OpNum + 1, STI, O); 986 987 if (CommentStream) 988 *CommentStream << '=' << (Val << Shift) << '\n'; 989 } else { 990 assert(MO.isExpr() && "Unexpected operand type!"); 991 MO.getExpr()->print(O, &MAI); 992 printShifter(MI, OpNum + 1, STI, O); 993 } 994 } 995 996 void AArch64InstPrinter::printLogicalImm32(const MCInst *MI, unsigned OpNum, 997 const MCSubtargetInfo &STI, 998 raw_ostream &O) { 999 uint64_t Val = MI->getOperand(OpNum).getImm(); 1000 O << "#0x"; 1001 O.write_hex(AArch64_AM::decodeLogicalImmediate(Val, 32)); 1002 } 1003 1004 void AArch64InstPrinter::printLogicalImm64(const MCInst *MI, unsigned OpNum, 1005 const MCSubtargetInfo &STI, 1006 raw_ostream &O) { 1007 uint64_t Val = MI->getOperand(OpNum).getImm(); 1008 O << "#0x"; 1009 O.write_hex(AArch64_AM::decodeLogicalImmediate(Val, 64)); 1010 } 1011 1012 void AArch64InstPrinter::printShifter(const MCInst *MI, unsigned OpNum, 1013 const MCSubtargetInfo &STI, 1014 raw_ostream &O) { 1015 unsigned Val = MI->getOperand(OpNum).getImm(); 1016 // LSL #0 should not be printed. 1017 if (AArch64_AM::getShiftType(Val) == AArch64_AM::LSL && 1018 AArch64_AM::getShiftValue(Val) == 0) 1019 return; 1020 O << ", " << AArch64_AM::getShiftExtendName(AArch64_AM::getShiftType(Val)) 1021 << " #" << AArch64_AM::getShiftValue(Val); 1022 } 1023 1024 void AArch64InstPrinter::printShiftedRegister(const MCInst *MI, unsigned OpNum, 1025 const MCSubtargetInfo &STI, 1026 raw_ostream &O) { 1027 O << getRegisterName(MI->getOperand(OpNum).getReg()); 1028 printShifter(MI, OpNum + 1, STI, O); 1029 } 1030 1031 void AArch64InstPrinter::printExtendedRegister(const MCInst *MI, unsigned OpNum, 1032 const MCSubtargetInfo &STI, 1033 raw_ostream &O) { 1034 O << getRegisterName(MI->getOperand(OpNum).getReg()); 1035 printArithExtend(MI, OpNum + 1, STI, O); 1036 } 1037 1038 void AArch64InstPrinter::printArithExtend(const MCInst *MI, unsigned OpNum, 1039 const MCSubtargetInfo &STI, 1040 raw_ostream &O) { 1041 unsigned Val = MI->getOperand(OpNum).getImm(); 1042 AArch64_AM::ShiftExtendType ExtType = AArch64_AM::getArithExtendType(Val); 1043 unsigned ShiftVal = AArch64_AM::getArithShiftValue(Val); 1044 1045 // If the destination or first source register operand is [W]SP, print 1046 // UXTW/UXTX as LSL, and if the shift amount is also zero, print nothing at 1047 // all. 1048 if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) { 1049 unsigned Dest = MI->getOperand(0).getReg(); 1050 unsigned Src1 = MI->getOperand(1).getReg(); 1051 if ( ((Dest == AArch64::SP || Src1 == AArch64::SP) && 1052 ExtType == AArch64_AM::UXTX) || 1053 ((Dest == AArch64::WSP || Src1 == AArch64::WSP) && 1054 ExtType == AArch64_AM::UXTW) ) { 1055 if (ShiftVal != 0) 1056 O << ", lsl #" << ShiftVal; 1057 return; 1058 } 1059 } 1060 O << ", " << AArch64_AM::getShiftExtendName(ExtType); 1061 if (ShiftVal != 0) 1062 O << " #" << ShiftVal; 1063 } 1064 1065 void AArch64InstPrinter::printMemExtend(const MCInst *MI, unsigned OpNum, 1066 raw_ostream &O, char SrcRegKind, 1067 unsigned Width) { 1068 unsigned SignExtend = MI->getOperand(OpNum).getImm(); 1069 unsigned DoShift = MI->getOperand(OpNum + 1).getImm(); 1070 1071 // sxtw, sxtx, uxtw or lsl (== uxtx) 1072 bool IsLSL = !SignExtend && SrcRegKind == 'x'; 1073 if (IsLSL) 1074 O << "lsl"; 1075 else 1076 O << (SignExtend ? 's' : 'u') << "xt" << SrcRegKind; 1077 1078 if (DoShift || IsLSL) 1079 O << " #" << Log2_32(Width / 8); 1080 } 1081 1082 void AArch64InstPrinter::printCondCode(const MCInst *MI, unsigned OpNum, 1083 const MCSubtargetInfo &STI, 1084 raw_ostream &O) { 1085 AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(OpNum).getImm(); 1086 O << AArch64CC::getCondCodeName(CC); 1087 } 1088 1089 void AArch64InstPrinter::printInverseCondCode(const MCInst *MI, unsigned OpNum, 1090 const MCSubtargetInfo &STI, 1091 raw_ostream &O) { 1092 AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(OpNum).getImm(); 1093 O << AArch64CC::getCondCodeName(AArch64CC::getInvertedCondCode(CC)); 1094 } 1095 1096 void AArch64InstPrinter::printAMNoIndex(const MCInst *MI, unsigned OpNum, 1097 const MCSubtargetInfo &STI, 1098 raw_ostream &O) { 1099 O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ']'; 1100 } 1101 1102 template<int Scale> 1103 void AArch64InstPrinter::printImmScale(const MCInst *MI, unsigned OpNum, 1104 const MCSubtargetInfo &STI, 1105 raw_ostream &O) { 1106 O << '#' << Scale * MI->getOperand(OpNum).getImm(); 1107 } 1108 1109 void AArch64InstPrinter::printUImm12Offset(const MCInst *MI, unsigned OpNum, 1110 unsigned Scale, raw_ostream &O) { 1111 const MCOperand MO = MI->getOperand(OpNum); 1112 if (MO.isImm()) { 1113 O << "#" << (MO.getImm() * Scale); 1114 } else { 1115 assert(MO.isExpr() && "Unexpected operand type!"); 1116 MO.getExpr()->print(O, &MAI); 1117 } 1118 } 1119 1120 void AArch64InstPrinter::printAMIndexedWB(const MCInst *MI, unsigned OpNum, 1121 unsigned Scale, raw_ostream &O) { 1122 const MCOperand MO1 = MI->getOperand(OpNum + 1); 1123 O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()); 1124 if (MO1.isImm()) { 1125 O << ", #" << (MO1.getImm() * Scale); 1126 } else { 1127 assert(MO1.isExpr() && "Unexpected operand type!"); 1128 O << ", "; 1129 MO1.getExpr()->print(O, &MAI); 1130 } 1131 O << ']'; 1132 } 1133 1134 void AArch64InstPrinter::printPrefetchOp(const MCInst *MI, unsigned OpNum, 1135 const MCSubtargetInfo &STI, 1136 raw_ostream &O) { 1137 unsigned prfop = MI->getOperand(OpNum).getImm(); 1138 bool Valid; 1139 StringRef Name = 1140 AArch64PRFM::PRFMMapper().toString(prfop, STI.getFeatureBits(), Valid); 1141 if (Valid) 1142 O << Name; 1143 else 1144 O << '#' << prfop; 1145 } 1146 1147 void AArch64InstPrinter::printPSBHintOp(const MCInst *MI, unsigned OpNum, 1148 const MCSubtargetInfo &STI, 1149 raw_ostream &O) { 1150 unsigned psbhintop = MI->getOperand(OpNum).getImm(); 1151 bool Valid; 1152 StringRef Name = 1153 AArch64PSBHint::PSBHintMapper().toString(psbhintop, STI.getFeatureBits(), Valid); 1154 if (Valid) 1155 O << Name; 1156 else 1157 O << '#' << psbhintop; 1158 } 1159 1160 void AArch64InstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum, 1161 const MCSubtargetInfo &STI, 1162 raw_ostream &O) { 1163 const MCOperand &MO = MI->getOperand(OpNum); 1164 float FPImm = 1165 MO.isFPImm() ? MO.getFPImm() : AArch64_AM::getFPImmFloat(MO.getImm()); 1166 1167 // 8 decimal places are enough to perfectly represent permitted floats. 1168 O << format("#%.8f", FPImm); 1169 } 1170 1171 static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride = 1) { 1172 while (Stride--) { 1173 switch (Reg) { 1174 default: 1175 llvm_unreachable("Vector register expected!"); 1176 case AArch64::Q0: Reg = AArch64::Q1; break; 1177 case AArch64::Q1: Reg = AArch64::Q2; break; 1178 case AArch64::Q2: Reg = AArch64::Q3; break; 1179 case AArch64::Q3: Reg = AArch64::Q4; break; 1180 case AArch64::Q4: Reg = AArch64::Q5; break; 1181 case AArch64::Q5: Reg = AArch64::Q6; break; 1182 case AArch64::Q6: Reg = AArch64::Q7; break; 1183 case AArch64::Q7: Reg = AArch64::Q8; break; 1184 case AArch64::Q8: Reg = AArch64::Q9; break; 1185 case AArch64::Q9: Reg = AArch64::Q10; break; 1186 case AArch64::Q10: Reg = AArch64::Q11; break; 1187 case AArch64::Q11: Reg = AArch64::Q12; break; 1188 case AArch64::Q12: Reg = AArch64::Q13; break; 1189 case AArch64::Q13: Reg = AArch64::Q14; break; 1190 case AArch64::Q14: Reg = AArch64::Q15; break; 1191 case AArch64::Q15: Reg = AArch64::Q16; break; 1192 case AArch64::Q16: Reg = AArch64::Q17; break; 1193 case AArch64::Q17: Reg = AArch64::Q18; break; 1194 case AArch64::Q18: Reg = AArch64::Q19; break; 1195 case AArch64::Q19: Reg = AArch64::Q20; break; 1196 case AArch64::Q20: Reg = AArch64::Q21; break; 1197 case AArch64::Q21: Reg = AArch64::Q22; break; 1198 case AArch64::Q22: Reg = AArch64::Q23; break; 1199 case AArch64::Q23: Reg = AArch64::Q24; break; 1200 case AArch64::Q24: Reg = AArch64::Q25; break; 1201 case AArch64::Q25: Reg = AArch64::Q26; break; 1202 case AArch64::Q26: Reg = AArch64::Q27; break; 1203 case AArch64::Q27: Reg = AArch64::Q28; break; 1204 case AArch64::Q28: Reg = AArch64::Q29; break; 1205 case AArch64::Q29: Reg = AArch64::Q30; break; 1206 case AArch64::Q30: Reg = AArch64::Q31; break; 1207 // Vector lists can wrap around. 1208 case AArch64::Q31: 1209 Reg = AArch64::Q0; 1210 break; 1211 } 1212 } 1213 return Reg; 1214 } 1215 1216 template<unsigned size> 1217 void AArch64InstPrinter::printGPRSeqPairsClassOperand(const MCInst *MI, 1218 unsigned OpNum, 1219 const MCSubtargetInfo &STI, 1220 raw_ostream &O) { 1221 static_assert(size == 64 || size == 32, 1222 "Template parameter must be either 32 or 64"); 1223 unsigned Reg = MI->getOperand(OpNum).getReg(); 1224 1225 unsigned Sube = (size == 32) ? AArch64::sube32 : AArch64::sube64; 1226 unsigned Subo = (size == 32) ? AArch64::subo32 : AArch64::subo64; 1227 1228 unsigned Even = MRI.getSubReg(Reg, Sube); 1229 unsigned Odd = MRI.getSubReg(Reg, Subo); 1230 O << getRegisterName(Even) << ", " << getRegisterName(Odd); 1231 } 1232 1233 void AArch64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum, 1234 const MCSubtargetInfo &STI, 1235 raw_ostream &O, 1236 StringRef LayoutSuffix) { 1237 unsigned Reg = MI->getOperand(OpNum).getReg(); 1238 1239 O << "{ "; 1240 1241 // Work out how many registers there are in the list (if there is an actual 1242 // list). 1243 unsigned NumRegs = 1; 1244 if (MRI.getRegClass(AArch64::DDRegClassID).contains(Reg) || 1245 MRI.getRegClass(AArch64::QQRegClassID).contains(Reg)) 1246 NumRegs = 2; 1247 else if (MRI.getRegClass(AArch64::DDDRegClassID).contains(Reg) || 1248 MRI.getRegClass(AArch64::QQQRegClassID).contains(Reg)) 1249 NumRegs = 3; 1250 else if (MRI.getRegClass(AArch64::DDDDRegClassID).contains(Reg) || 1251 MRI.getRegClass(AArch64::QQQQRegClassID).contains(Reg)) 1252 NumRegs = 4; 1253 1254 // Now forget about the list and find out what the first register is. 1255 if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0)) 1256 Reg = FirstReg; 1257 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0)) 1258 Reg = FirstReg; 1259 1260 // If it's a D-reg, we need to promote it to the equivalent Q-reg before 1261 // printing (otherwise getRegisterName fails). 1262 if (MRI.getRegClass(AArch64::FPR64RegClassID).contains(Reg)) { 1263 const MCRegisterClass &FPR128RC = 1264 MRI.getRegClass(AArch64::FPR128RegClassID); 1265 Reg = MRI.getMatchingSuperReg(Reg, AArch64::dsub, &FPR128RC); 1266 } 1267 1268 for (unsigned i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg)) { 1269 O << getRegisterName(Reg, AArch64::vreg) << LayoutSuffix; 1270 if (i + 1 != NumRegs) 1271 O << ", "; 1272 } 1273 1274 O << " }"; 1275 } 1276 1277 void 1278 AArch64InstPrinter::printImplicitlyTypedVectorList(const MCInst *MI, 1279 unsigned OpNum, 1280 const MCSubtargetInfo &STI, 1281 raw_ostream &O) { 1282 printVectorList(MI, OpNum, STI, O, ""); 1283 } 1284 1285 template <unsigned NumLanes, char LaneKind> 1286 void AArch64InstPrinter::printTypedVectorList(const MCInst *MI, unsigned OpNum, 1287 const MCSubtargetInfo &STI, 1288 raw_ostream &O) { 1289 std::string Suffix("."); 1290 if (NumLanes) 1291 Suffix += itostr(NumLanes) + LaneKind; 1292 else 1293 Suffix += LaneKind; 1294 1295 printVectorList(MI, OpNum, STI, O, Suffix); 1296 } 1297 1298 void AArch64InstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum, 1299 const MCSubtargetInfo &STI, 1300 raw_ostream &O) { 1301 O << "[" << MI->getOperand(OpNum).getImm() << "]"; 1302 } 1303 1304 void AArch64InstPrinter::printAlignedLabel(const MCInst *MI, unsigned OpNum, 1305 const MCSubtargetInfo &STI, 1306 raw_ostream &O) { 1307 const MCOperand &Op = MI->getOperand(OpNum); 1308 1309 // If the label has already been resolved to an immediate offset (say, when 1310 // we're running the disassembler), just print the immediate. 1311 if (Op.isImm()) { 1312 O << "#" << (Op.getImm() * 4); 1313 return; 1314 } 1315 1316 // If the branch target is simply an address then print it in hex. 1317 const MCConstantExpr *BranchTarget = 1318 dyn_cast<MCConstantExpr>(MI->getOperand(OpNum).getExpr()); 1319 int64_t Address; 1320 if (BranchTarget && BranchTarget->evaluateAsAbsolute(Address)) { 1321 O << "0x"; 1322 O.write_hex(Address); 1323 } else { 1324 // Otherwise, just print the expression. 1325 MI->getOperand(OpNum).getExpr()->print(O, &MAI); 1326 } 1327 } 1328 1329 void AArch64InstPrinter::printAdrpLabel(const MCInst *MI, unsigned OpNum, 1330 const MCSubtargetInfo &STI, 1331 raw_ostream &O) { 1332 const MCOperand &Op = MI->getOperand(OpNum); 1333 1334 // If the label has already been resolved to an immediate offset (say, when 1335 // we're running the disassembler), just print the immediate. 1336 if (Op.isImm()) { 1337 O << "#" << (Op.getImm() * (1 << 12)); 1338 return; 1339 } 1340 1341 // Otherwise, just print the expression. 1342 MI->getOperand(OpNum).getExpr()->print(O, &MAI); 1343 } 1344 1345 void AArch64InstPrinter::printBarrierOption(const MCInst *MI, unsigned OpNo, 1346 const MCSubtargetInfo &STI, 1347 raw_ostream &O) { 1348 unsigned Val = MI->getOperand(OpNo).getImm(); 1349 unsigned Opcode = MI->getOpcode(); 1350 1351 bool Valid; 1352 StringRef Name; 1353 if (Opcode == AArch64::ISB) 1354 Name = AArch64ISB::ISBMapper().toString(Val, STI.getFeatureBits(), 1355 Valid); 1356 else 1357 Name = AArch64DB::DBarrierMapper().toString(Val, STI.getFeatureBits(), 1358 Valid); 1359 if (Valid) 1360 O << Name; 1361 else 1362 O << "#" << Val; 1363 } 1364 1365 void AArch64InstPrinter::printMRSSystemRegister(const MCInst *MI, unsigned OpNo, 1366 const MCSubtargetInfo &STI, 1367 raw_ostream &O) { 1368 unsigned Val = MI->getOperand(OpNo).getImm(); 1369 1370 auto Mapper = AArch64SysReg::MRSMapper(); 1371 std::string Name = Mapper.toString(Val, STI.getFeatureBits()); 1372 1373 O << StringRef(Name).upper(); 1374 } 1375 1376 void AArch64InstPrinter::printMSRSystemRegister(const MCInst *MI, unsigned OpNo, 1377 const MCSubtargetInfo &STI, 1378 raw_ostream &O) { 1379 unsigned Val = MI->getOperand(OpNo).getImm(); 1380 1381 auto Mapper = AArch64SysReg::MSRMapper(); 1382 std::string Name = Mapper.toString(Val, STI.getFeatureBits()); 1383 1384 O << StringRef(Name).upper(); 1385 } 1386 1387 void AArch64InstPrinter::printSystemPStateField(const MCInst *MI, unsigned OpNo, 1388 const MCSubtargetInfo &STI, 1389 raw_ostream &O) { 1390 unsigned Val = MI->getOperand(OpNo).getImm(); 1391 1392 bool Valid; 1393 StringRef Name = 1394 AArch64PState::PStateMapper().toString(Val, STI.getFeatureBits(), Valid); 1395 if (Valid) 1396 O << Name.upper(); 1397 else 1398 O << "#" << Val; 1399 } 1400 1401 void AArch64InstPrinter::printSIMDType10Operand(const MCInst *MI, unsigned OpNo, 1402 const MCSubtargetInfo &STI, 1403 raw_ostream &O) { 1404 unsigned RawVal = MI->getOperand(OpNo).getImm(); 1405 uint64_t Val = AArch64_AM::decodeAdvSIMDModImmType10(RawVal); 1406 O << format("#%#016llx", Val); 1407 } 1408
