| /external/llvm/lib/Target/X86/Disassembler/ |
| X86Disassembler.h | 94 std::unique_ptr<const MCInstrInfo> MII;
97 std::unique_ptr<const MCInstrInfo> MII);
|
| X86Disassembler.cpp | 47 const void *mii) {
48 const MCInstrInfo *MII = static_cast<const MCInstrInfo *>(mii);
49 return MII->getName(Opcode);
81 std::unique_ptr<const MCInstrInfo> MII)
82 : MCDisassembler(STI, Ctx), MII(std::move(MII)) {
155 (const void *)MII.get(), Address, fMode);
[all...] |
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonInstPrinter.h | 28 explicit HexagonInstPrinter(MCAsmInfo const &MAI, MCInstrInfo const &MII,
77 MCInstrInfo const &getMII() const { return MII; }
84 MCInstrInfo const &MII;
|
| /external/llvm/include/llvm/MC/ |
| MCInstPrinter.h | 45 const MCInstrInfo &MII;
61 MCInstPrinter(const MCAsmInfo &mai, const MCInstrInfo &mii,
63 : CommentStream(nullptr), MAI(mai), MII(mii), MRI(mri), UseMarkup(0),
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonFixupHwLoops.cpp | 66 MachineBasicBlock::iterator &MII);
132 MachineBasicBlock::iterator MII = MBB.begin();
134 while (MII != MIE) {
135 InstOffset += HII->getSize(&*MII);
136 if (MII->isDebugValue()) {
137 ++MII;
140 if (isHardwareLoop(MII)) {
141 assert(MII->getOperand(0).isMBB() &&
143 int diff = InstOffset - BlockToInstOffset[MII->getOperand(0).getMBB()];
145 useExtLoopInstr(MF, MII);
[all...] |
| HexagonSplitConst32AndConst64.cpp | 86 MachineBasicBlock::iterator MII = MBB->begin();
88 while (MII != MIE) {
89 MachineInstr *MI = MII;
96 BuildMI (*MBB, MII, MI->getDebugLoc(),
98 BuildMI (*MBB, MII, MI->getDebugLoc(),
102 MII = MBB->erase (MI);
120 BuildMI(*MBB, MII, MI->getDebugLoc(),
122 MII = MBB->erase (MI);
145 BuildMI(*MBB, MII, MI->getDebugLoc(),
147 BuildMI (*MBB, MII, MI->getDebugLoc()
[all...] |
| HexagonCFGOptimizer.cpp | 108 MachineBasicBlock::iterator MII = MBB->getFirstTerminator();
109 if (MII != MBB->end()) {
110 MachineInstr *MI = MII;
|
| HexagonAsmPrinter.cpp | 574 MachineBasicBlock::const_instr_iterator MII = MI->getIterator();
577 for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
578 if (MII->getOpcode() == TargetOpcode::DBG_VALUE ||
579 MII->getOpcode() == TargetOpcode::IMPLICIT_DEF)
582 HexagonLowerToMC(MCII, &*MII, MCB, *this);
|
| HexagonVLIWPacketizer.cpp | 333 SDep::Kind DepType, MachineBasicBlock::iterator &MII,
364 const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII,
368 if (!HII->isV60VectorInstruction(MII))
386 MachineInstr *MJ = MII;
413 SDep::Kind DepType, MachineBasicBlock::iterator &MII,
693 MachineBasicBlock::iterator &MII) {
720 const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII,
771 if (!canPromoteToNewValue(MI, PacketSU, DepReg, MII))
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| DFAPacketizer.h | 161 MachineBasicBlock::iterator MII = MI;
164 return MII;
|
| MachineInstrBuilder.h | 280 MachineBasicBlock::instr_iterator MII(I);
281 return BuildMI(BB, MII, DL, MCID, DestReg);
284 MachineBasicBlock::iterator MII = I;
285 return BuildMI(BB, MII, DL, MCID, DestReg);
316 MachineBasicBlock::instr_iterator MII(I);
317 return BuildMI(BB, MII, DL, MCID);
320 MachineBasicBlock::iterator MII = I;
321 return BuildMI(BB, MII, DL, MCID);
|
| MachineBasicBlock.h | 165 IterTy MII;
168 bundle_iterator(IterTy MI) : MII(MI) {}
170 bundle_iterator(Ty &MI) : MII(MI) {
174 bundle_iterator(Ty *MI) : MII(MI) {
181 : MII(I.getInstrIterator()) {}
182 bundle_iterator() : MII(nullptr) {}
184 Ty &operator*() const { return *MII; }
187 operator Ty *() const { return MII.getNodePtrUnchecked(); }
190 return MII == X.MII;
[all...] |
| /external/llvm/lib/MC/MCDisassembler/ |
| Disassembler.cpp | 55 const MCInstrInfo *MII = TheTarget->createMCInstrInfo();
56 if (!MII)
86 Triple(TT), AsmPrinterVariant, *MAI, *MII, *MRI);
92 TheTarget, MAI, MRI, STI, MII, Ctx, DisAsm, IP);
308 const MCInstrInfo *MII = DC->getInstrInfo();
313 Triple(DC->getTripleName()), AsmPrinterVariant, *MAI, *MII, *MRI);
|
| Disassembler.h | 68 std::unique_ptr<const llvm::MCInstrInfo> MII;
91 const MCInstrInfo *mII,
101 MII.reset(mII);
116 const MCInstrInfo *getInstrInfo() const { return MII.get(); }
|
| /external/llvm/include/llvm/Target/ |
| TargetMachine.h | 101 const MCInstrInfo *MII;
165 const MCInstrInfo *getMCInstrInfo() const { return MII; }
|
| /external/llvm/lib/CodeGen/ |
| MachineInstrBundle.cpp | 51 for (MachineBasicBlock::instr_iterator MII = MBB->instr_begin(),
52 MIE = MBB->instr_end(); MII != MIE; ) {
53 MachineInstr *MI = &*MII;
58 while (++MII != MIE && MII->isBundledWithPred()) {
59 MII->unbundleFromPred();
60 for (unsigned i = 0, e = MII->getNumOperands(); i != e; ++i) {
61 MachineOperand &MO = MII->getOperand(i);
72 ++MII;
239 MachineBasicBlock::instr_iterator MII = MBB.instr_begin()
[all...] |
| RegAllocFast.cpp | 799 MachineBasicBlock::iterator MII = MBB->begin();
804 definePhysReg(MII, LI.PhysReg, regReserved);
810 while (MII != MBB->end()) {
811 MachineInstr *MI = MII++;
[all...] |
| InlineSpiller.cpp | 736 MachineBasicBlock::iterator MII;
738 MII = MBB->SkipPHIsAndLabels(MBB->begin());
742 MII = DefMI;
743 ++MII;
746 TII.storeRegToStackSlot(*MBB, MII, SVI.SpillReg, false, StackSlot,
748 --MII; // Point to store instruction.
749 LIS.InsertMachineInstrInMaps(MII);
750 DEBUG(dbgs() << "\thoisted: " << SVI.SpillVNI->def << '\t' << *MII);
[all...] |
| LiveIntervalAnalysis.cpp | [all...] |
| RegisterCoalescer.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600Packetizer.cpp | 189 MachineInstr *MII = SUI->getInstr(), *MIJ = SUJ->getInstr();
190 if (getSlot(MII) == getSlot(MIJ))
192 // Does MII and MIJ share the same pred_sel ?
193 int OpI = TII->getOperandIdx(MII->getOpcode(), AMDGPU::OpName::pred_sel),
195 unsigned PredI = (OpI > -1)?MII->getOperand(OpI).getReg():0,
207 if (MII->getOperand(0).getReg() != MIJ->getOperand(0).getReg())
213 bool ARDef = TII->definesAddressRegister(MII) ||
215 bool ARUse = TII->usesAddressRegister(MII) ||
|
| /external/llvm/lib/Target/ARM/ |
| MLxExpansionPass.cpp | 315 MachineBasicBlock::iterator MII = MI;
316 MII = std::prev(MII);
317 MachineInstr &MI2 = *MII;
318 MII = std::prev(MII);
319 MachineInstr &MI1 = *MII;
335 MachineBasicBlock::reverse_iterator MII = MBB.rbegin(), E = MBB.rend();
336 while (MII != E) {
337 MachineInstr *MI = &*MII;
[all...] |
| Thumb2SizeReduction.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | [all...] |
| /external/clang/lib/Lex/ |
| PPDirectives.cpp | [all...] |
