1 //===-- X86Disassembler.cpp - Disassembler for x86 and x86_64 -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the X86 Disassembler. 11 // It contains code to translate the data produced by the decoder into 12 // MCInsts. 13 // Documentation for the disassembler can be found in X86Disassembler.h. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #include "X86Disassembler.h" 18 #include "X86DisassemblerDecoder.h" 19 #include "llvm/MC/MCContext.h" 20 #include "llvm/MC/MCDisassembler.h" 21 #include "llvm/MC/MCExpr.h" 22 #include "llvm/MC/MCInst.h" 23 #include "llvm/MC/MCInstrInfo.h" 24 #include "llvm/MC/MCSubtargetInfo.h" 25 #include "llvm/Support/Debug.h" 26 #include "llvm/Support/TargetRegistry.h" 27 #include "llvm/Support/raw_ostream.h" 28 29 using namespace llvm; 30 using namespace llvm::X86Disassembler; 31 32 #define DEBUG_TYPE "x86-disassembler" 33 34 #define GET_REGINFO_ENUM 35 #include "X86GenRegisterInfo.inc" 36 #define GET_INSTRINFO_ENUM 37 #include "X86GenInstrInfo.inc" 38 #define GET_SUBTARGETINFO_ENUM 39 #include "X86GenSubtargetInfo.inc" 40 41 void llvm::X86Disassembler::Debug(const char *file, unsigned line, 42 const char *s) { 43 dbgs() << file << ":" << line << ": " << s; 44 } 45 46 const char *llvm::X86Disassembler::GetInstrName(unsigned Opcode, 47 const void *mii) { 48 const MCInstrInfo *MII = static_cast<const MCInstrInfo *>(mii); 49 return MII->getName(Opcode); 50 } 51 52 #define debug(s) DEBUG(Debug(__FILE__, __LINE__, s)); 53 54 namespace llvm { 55 56 // Fill-ins to make the compiler happy. These constants are never actually 57 // assigned; they are just filler to make an automatically-generated switch 58 // statement work. 59 namespace X86 { 60 enum { 61 BX_SI = 500, 62 BX_DI = 501, 63 BP_SI = 502, 64 BP_DI = 503, 65 sib = 504, 66 sib64 = 505 67 }; 68 } 69 70 extern Target TheX86_32Target, TheX86_64Target; 71 72 } 73 74 static bool translateInstruction(MCInst &target, 75 InternalInstruction &source, 76 const MCDisassembler *Dis); 77 78 X86GenericDisassembler::X86GenericDisassembler( 79 const MCSubtargetInfo &STI, 80 MCContext &Ctx, 81 std::unique_ptr<const MCInstrInfo> MII) 82 : MCDisassembler(STI, Ctx), MII(std::move(MII)) { 83 const FeatureBitset &FB = STI.getFeatureBits(); 84 if (FB[X86::Mode16Bit]) { 85 fMode = MODE_16BIT; 86 return; 87 } else if (FB[X86::Mode32Bit]) { 88 fMode = MODE_32BIT; 89 return; 90 } else if (FB[X86::Mode64Bit]) { 91 fMode = MODE_64BIT; 92 return; 93 } 94 95 llvm_unreachable("Invalid CPU mode"); 96 } 97 98 namespace { 99 struct Region { 100 ArrayRef<uint8_t> Bytes; 101 uint64_t Base; 102 Region(ArrayRef<uint8_t> Bytes, uint64_t Base) : Bytes(Bytes), Base(Base) {} 103 }; 104 } // end anonymous namespace 105 106 /// A callback function that wraps the readByte method from Region. 107 /// 108 /// @param Arg - The generic callback parameter. In this case, this should 109 /// be a pointer to a Region. 110 /// @param Byte - A pointer to the byte to be read. 111 /// @param Address - The address to be read. 112 static int regionReader(const void *Arg, uint8_t *Byte, uint64_t Address) { 113 auto *R = static_cast<const Region *>(Arg); 114 ArrayRef<uint8_t> Bytes = R->Bytes; 115 unsigned Index = Address - R->Base; 116 if (Bytes.size() <= Index) 117 return -1; 118 *Byte = Bytes[Index]; 119 return 0; 120 } 121 122 /// logger - a callback function that wraps the operator<< method from 123 /// raw_ostream. 124 /// 125 /// @param arg - The generic callback parameter. This should be a pointe 126 /// to a raw_ostream. 127 /// @param log - A string to be logged. logger() adds a newline. 128 static void logger(void* arg, const char* log) { 129 if (!arg) 130 return; 131 132 raw_ostream &vStream = *(static_cast<raw_ostream*>(arg)); 133 vStream << log << "\n"; 134 } 135 136 // 137 // Public interface for the disassembler 138 // 139 140 MCDisassembler::DecodeStatus X86GenericDisassembler::getInstruction( 141 MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, 142 raw_ostream &VStream, raw_ostream &CStream) const { 143 CommentStream = &CStream; 144 145 InternalInstruction InternalInstr; 146 147 dlog_t LoggerFn = logger; 148 if (&VStream == &nulls()) 149 LoggerFn = nullptr; // Disable logging completely if it's going to nulls(). 150 151 Region R(Bytes, Address); 152 153 int Ret = decodeInstruction(&InternalInstr, regionReader, (const void *)&R, 154 LoggerFn, (void *)&VStream, 155 (const void *)MII.get(), Address, fMode); 156 157 if (Ret) { 158 Size = InternalInstr.readerCursor - Address; 159 return Fail; 160 } else { 161 Size = InternalInstr.length; 162 return (!translateInstruction(Instr, InternalInstr, this)) ? Success : Fail; 163 } 164 } 165 166 // 167 // Private code that translates from struct InternalInstructions to MCInsts. 168 // 169 170 /// translateRegister - Translates an internal register to the appropriate LLVM 171 /// register, and appends it as an operand to an MCInst. 172 /// 173 /// @param mcInst - The MCInst to append to. 174 /// @param reg - The Reg to append. 175 static void translateRegister(MCInst &mcInst, Reg reg) { 176 #define ENTRY(x) X86::x, 177 uint8_t llvmRegnums[] = { 178 ALL_REGS 179 0 180 }; 181 #undef ENTRY 182 183 uint8_t llvmRegnum = llvmRegnums[reg]; 184 mcInst.addOperand(MCOperand::createReg(llvmRegnum)); 185 } 186 187 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 188 /// immediate Value in the MCInst. 189 /// 190 /// @param Value - The immediate Value, has had any PC adjustment made by 191 /// the caller. 192 /// @param isBranch - If the instruction is a branch instruction 193 /// @param Address - The starting address of the instruction 194 /// @param Offset - The byte offset to this immediate in the instruction 195 /// @param Width - The byte width of this immediate in the instruction 196 /// 197 /// If the getOpInfo() function was set when setupForSymbolicDisassembly() was 198 /// called then that function is called to get any symbolic information for the 199 /// immediate in the instruction using the Address, Offset and Width. If that 200 /// returns non-zero then the symbolic information it returns is used to create 201 /// an MCExpr and that is added as an operand to the MCInst. If getOpInfo() 202 /// returns zero and isBranch is true then a symbol look up for immediate Value 203 /// is done and if a symbol is found an MCExpr is created with that, else 204 /// an MCExpr with the immediate Value is created. This function returns true 205 /// if it adds an operand to the MCInst and false otherwise. 206 static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, 207 uint64_t Address, uint64_t Offset, 208 uint64_t Width, MCInst &MI, 209 const MCDisassembler *Dis) { 210 return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch, 211 Offset, Width); 212 } 213 214 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 215 /// referenced by a load instruction with the base register that is the rip. 216 /// These can often be addresses in a literal pool. The Address of the 217 /// instruction and its immediate Value are used to determine the address 218 /// being referenced in the literal pool entry. The SymbolLookUp call back will 219 /// return a pointer to a literal 'C' string if the referenced address is an 220 /// address into a section with 'C' string literals. 221 static void tryAddingPcLoadReferenceComment(uint64_t Address, uint64_t Value, 222 const void *Decoder) { 223 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 224 Dis->tryAddingPcLoadReferenceComment(Value, Address); 225 } 226 227 static const uint8_t segmentRegnums[SEG_OVERRIDE_max] = { 228 0, // SEG_OVERRIDE_NONE 229 X86::CS, 230 X86::SS, 231 X86::DS, 232 X86::ES, 233 X86::FS, 234 X86::GS 235 }; 236 237 /// translateSrcIndex - Appends a source index operand to an MCInst. 238 /// 239 /// @param mcInst - The MCInst to append to. 240 /// @param insn - The internal instruction. 241 static bool translateSrcIndex(MCInst &mcInst, InternalInstruction &insn) { 242 unsigned baseRegNo; 243 244 if (insn.mode == MODE_64BIT) 245 baseRegNo = insn.prefixPresent[0x67] ? X86::ESI : X86::RSI; 246 else if (insn.mode == MODE_32BIT) 247 baseRegNo = insn.prefixPresent[0x67] ? X86::SI : X86::ESI; 248 else { 249 assert(insn.mode == MODE_16BIT); 250 baseRegNo = insn.prefixPresent[0x67] ? X86::ESI : X86::SI; 251 } 252 MCOperand baseReg = MCOperand::createReg(baseRegNo); 253 mcInst.addOperand(baseReg); 254 255 MCOperand segmentReg; 256 segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]); 257 mcInst.addOperand(segmentReg); 258 return false; 259 } 260 261 /// translateDstIndex - Appends a destination index operand to an MCInst. 262 /// 263 /// @param mcInst - The MCInst to append to. 264 /// @param insn - The internal instruction. 265 266 static bool translateDstIndex(MCInst &mcInst, InternalInstruction &insn) { 267 unsigned baseRegNo; 268 269 if (insn.mode == MODE_64BIT) 270 baseRegNo = insn.prefixPresent[0x67] ? X86::EDI : X86::RDI; 271 else if (insn.mode == MODE_32BIT) 272 baseRegNo = insn.prefixPresent[0x67] ? X86::DI : X86::EDI; 273 else { 274 assert(insn.mode == MODE_16BIT); 275 baseRegNo = insn.prefixPresent[0x67] ? X86::EDI : X86::DI; 276 } 277 MCOperand baseReg = MCOperand::createReg(baseRegNo); 278 mcInst.addOperand(baseReg); 279 return false; 280 } 281 282 /// translateImmediate - Appends an immediate operand to an MCInst. 283 /// 284 /// @param mcInst - The MCInst to append to. 285 /// @param immediate - The immediate value to append. 286 /// @param operand - The operand, as stored in the descriptor table. 287 /// @param insn - The internal instruction. 288 static void translateImmediate(MCInst &mcInst, uint64_t immediate, 289 const OperandSpecifier &operand, 290 InternalInstruction &insn, 291 const MCDisassembler *Dis) { 292 // Sign-extend the immediate if necessary. 293 294 OperandType type = (OperandType)operand.type; 295 296 bool isBranch = false; 297 uint64_t pcrel = 0; 298 if (type == TYPE_RELv) { 299 isBranch = true; 300 pcrel = insn.startLocation + 301 insn.immediateOffset + insn.immediateSize; 302 switch (insn.displacementSize) { 303 default: 304 break; 305 case 1: 306 if(immediate & 0x80) 307 immediate |= ~(0xffull); 308 break; 309 case 2: 310 if(immediate & 0x8000) 311 immediate |= ~(0xffffull); 312 break; 313 case 4: 314 if(immediate & 0x80000000) 315 immediate |= ~(0xffffffffull); 316 break; 317 case 8: 318 break; 319 } 320 } 321 // By default sign-extend all X86 immediates based on their encoding. 322 else if (type == TYPE_IMM8 || type == TYPE_IMM16 || type == TYPE_IMM32 || 323 type == TYPE_IMM64 || type == TYPE_IMMv) { 324 switch (operand.encoding) { 325 default: 326 break; 327 case ENCODING_IB: 328 if(immediate & 0x80) 329 immediate |= ~(0xffull); 330 break; 331 case ENCODING_IW: 332 if(immediate & 0x8000) 333 immediate |= ~(0xffffull); 334 break; 335 case ENCODING_ID: 336 if(immediate & 0x80000000) 337 immediate |= ~(0xffffffffull); 338 break; 339 case ENCODING_IO: 340 break; 341 } 342 } else if (type == TYPE_IMM3) { 343 // Check for immediates that printSSECC can't handle. 344 if (immediate >= 8) { 345 unsigned NewOpc; 346 switch (mcInst.getOpcode()) { 347 default: llvm_unreachable("unexpected opcode"); 348 case X86::CMPPDrmi: NewOpc = X86::CMPPDrmi_alt; break; 349 case X86::CMPPDrri: NewOpc = X86::CMPPDrri_alt; break; 350 case X86::CMPPSrmi: NewOpc = X86::CMPPSrmi_alt; break; 351 case X86::CMPPSrri: NewOpc = X86::CMPPSrri_alt; break; 352 case X86::CMPSDrm: NewOpc = X86::CMPSDrm_alt; break; 353 case X86::CMPSDrr: NewOpc = X86::CMPSDrr_alt; break; 354 case X86::CMPSSrm: NewOpc = X86::CMPSSrm_alt; break; 355 case X86::CMPSSrr: NewOpc = X86::CMPSSrr_alt; break; 356 case X86::VPCOMBri: NewOpc = X86::VPCOMBri_alt; break; 357 case X86::VPCOMBmi: NewOpc = X86::VPCOMBmi_alt; break; 358 case X86::VPCOMWri: NewOpc = X86::VPCOMWri_alt; break; 359 case X86::VPCOMWmi: NewOpc = X86::VPCOMWmi_alt; break; 360 case X86::VPCOMDri: NewOpc = X86::VPCOMDri_alt; break; 361 case X86::VPCOMDmi: NewOpc = X86::VPCOMDmi_alt; break; 362 case X86::VPCOMQri: NewOpc = X86::VPCOMQri_alt; break; 363 case X86::VPCOMQmi: NewOpc = X86::VPCOMQmi_alt; break; 364 case X86::VPCOMUBri: NewOpc = X86::VPCOMUBri_alt; break; 365 case X86::VPCOMUBmi: NewOpc = X86::VPCOMUBmi_alt; break; 366 case X86::VPCOMUWri: NewOpc = X86::VPCOMUWri_alt; break; 367 case X86::VPCOMUWmi: NewOpc = X86::VPCOMUWmi_alt; break; 368 case X86::VPCOMUDri: NewOpc = X86::VPCOMUDri_alt; break; 369 case X86::VPCOMUDmi: NewOpc = X86::VPCOMUDmi_alt; break; 370 case X86::VPCOMUQri: NewOpc = X86::VPCOMUQri_alt; break; 371 case X86::VPCOMUQmi: NewOpc = X86::VPCOMUQmi_alt; break; 372 } 373 // Switch opcode to the one that doesn't get special printing. 374 mcInst.setOpcode(NewOpc); 375 } 376 } else if (type == TYPE_IMM5) { 377 // Check for immediates that printAVXCC can't handle. 378 if (immediate >= 32) { 379 unsigned NewOpc; 380 switch (mcInst.getOpcode()) { 381 default: llvm_unreachable("unexpected opcode"); 382 case X86::VCMPPDrmi: NewOpc = X86::VCMPPDrmi_alt; break; 383 case X86::VCMPPDrri: NewOpc = X86::VCMPPDrri_alt; break; 384 case X86::VCMPPSrmi: NewOpc = X86::VCMPPSrmi_alt; break; 385 case X86::VCMPPSrri: NewOpc = X86::VCMPPSrri_alt; break; 386 case X86::VCMPSDrm: NewOpc = X86::VCMPSDrm_alt; break; 387 case X86::VCMPSDrr: NewOpc = X86::VCMPSDrr_alt; break; 388 case X86::VCMPSSrm: NewOpc = X86::VCMPSSrm_alt; break; 389 case X86::VCMPSSrr: NewOpc = X86::VCMPSSrr_alt; break; 390 case X86::VCMPPDYrmi: NewOpc = X86::VCMPPDYrmi_alt; break; 391 case X86::VCMPPDYrri: NewOpc = X86::VCMPPDYrri_alt; break; 392 case X86::VCMPPSYrmi: NewOpc = X86::VCMPPSYrmi_alt; break; 393 case X86::VCMPPSYrri: NewOpc = X86::VCMPPSYrri_alt; break; 394 case X86::VCMPPDZrmi: NewOpc = X86::VCMPPDZrmi_alt; break; 395 case X86::VCMPPDZrri: NewOpc = X86::VCMPPDZrri_alt; break; 396 case X86::VCMPPDZrrib: NewOpc = X86::VCMPPDZrrib_alt; break; 397 case X86::VCMPPSZrmi: NewOpc = X86::VCMPPSZrmi_alt; break; 398 case X86::VCMPPSZrri: NewOpc = X86::VCMPPSZrri_alt; break; 399 case X86::VCMPPSZrrib: NewOpc = X86::VCMPPSZrrib_alt; break; 400 case X86::VCMPSDZrm: NewOpc = X86::VCMPSDZrmi_alt; break; 401 case X86::VCMPSDZrr: NewOpc = X86::VCMPSDZrri_alt; break; 402 case X86::VCMPSSZrm: NewOpc = X86::VCMPSSZrmi_alt; break; 403 case X86::VCMPSSZrr: NewOpc = X86::VCMPSSZrri_alt; break; 404 } 405 // Switch opcode to the one that doesn't get special printing. 406 mcInst.setOpcode(NewOpc); 407 } 408 } else if (type == TYPE_AVX512ICC) { 409 if (immediate >= 8 || ((immediate & 0x3) == 3)) { 410 unsigned NewOpc; 411 switch (mcInst.getOpcode()) { 412 default: llvm_unreachable("unexpected opcode"); 413 case X86::VPCMPBZ128rmi: NewOpc = X86::VPCMPBZ128rmi_alt; break; 414 case X86::VPCMPBZ128rmik: NewOpc = X86::VPCMPBZ128rmik_alt; break; 415 case X86::VPCMPBZ128rri: NewOpc = X86::VPCMPBZ128rri_alt; break; 416 case X86::VPCMPBZ128rrik: NewOpc = X86::VPCMPBZ128rrik_alt; break; 417 case X86::VPCMPBZ256rmi: NewOpc = X86::VPCMPBZ256rmi_alt; break; 418 case X86::VPCMPBZ256rmik: NewOpc = X86::VPCMPBZ256rmik_alt; break; 419 case X86::VPCMPBZ256rri: NewOpc = X86::VPCMPBZ256rri_alt; break; 420 case X86::VPCMPBZ256rrik: NewOpc = X86::VPCMPBZ256rrik_alt; break; 421 case X86::VPCMPBZrmi: NewOpc = X86::VPCMPBZrmi_alt; break; 422 case X86::VPCMPBZrmik: NewOpc = X86::VPCMPBZrmik_alt; break; 423 case X86::VPCMPBZrri: NewOpc = X86::VPCMPBZrri_alt; break; 424 case X86::VPCMPBZrrik: NewOpc = X86::VPCMPBZrrik_alt; break; 425 case X86::VPCMPDZ128rmi: NewOpc = X86::VPCMPDZ128rmi_alt; break; 426 case X86::VPCMPDZ128rmib: NewOpc = X86::VPCMPDZ128rmib_alt; break; 427 case X86::VPCMPDZ128rmibk: NewOpc = X86::VPCMPDZ128rmibk_alt; break; 428 case X86::VPCMPDZ128rmik: NewOpc = X86::VPCMPDZ128rmik_alt; break; 429 case X86::VPCMPDZ128rri: NewOpc = X86::VPCMPDZ128rri_alt; break; 430 case X86::VPCMPDZ128rrik: NewOpc = X86::VPCMPDZ128rrik_alt; break; 431 case X86::VPCMPDZ256rmi: NewOpc = X86::VPCMPDZ256rmi_alt; break; 432 case X86::VPCMPDZ256rmib: NewOpc = X86::VPCMPDZ256rmib_alt; break; 433 case X86::VPCMPDZ256rmibk: NewOpc = X86::VPCMPDZ256rmibk_alt; break; 434 case X86::VPCMPDZ256rmik: NewOpc = X86::VPCMPDZ256rmik_alt; break; 435 case X86::VPCMPDZ256rri: NewOpc = X86::VPCMPDZ256rri_alt; break; 436 case X86::VPCMPDZ256rrik: NewOpc = X86::VPCMPDZ256rrik_alt; break; 437 case X86::VPCMPDZrmi: NewOpc = X86::VPCMPDZrmi_alt; break; 438 case X86::VPCMPDZrmib: NewOpc = X86::VPCMPDZrmib_alt; break; 439 case X86::VPCMPDZrmibk: NewOpc = X86::VPCMPDZrmibk_alt; break; 440 case X86::VPCMPDZrmik: NewOpc = X86::VPCMPDZrmik_alt; break; 441 case X86::VPCMPDZrri: NewOpc = X86::VPCMPDZrri_alt; break; 442 case X86::VPCMPDZrrik: NewOpc = X86::VPCMPDZrrik_alt; break; 443 case X86::VPCMPQZ128rmi: NewOpc = X86::VPCMPQZ128rmi_alt; break; 444 case X86::VPCMPQZ128rmib: NewOpc = X86::VPCMPQZ128rmib_alt; break; 445 case X86::VPCMPQZ128rmibk: NewOpc = X86::VPCMPQZ128rmibk_alt; break; 446 case X86::VPCMPQZ128rmik: NewOpc = X86::VPCMPQZ128rmik_alt; break; 447 case X86::VPCMPQZ128rri: NewOpc = X86::VPCMPQZ128rri_alt; break; 448 case X86::VPCMPQZ128rrik: NewOpc = X86::VPCMPQZ128rrik_alt; break; 449 case X86::VPCMPQZ256rmi: NewOpc = X86::VPCMPQZ256rmi_alt; break; 450 case X86::VPCMPQZ256rmib: NewOpc = X86::VPCMPQZ256rmib_alt; break; 451 case X86::VPCMPQZ256rmibk: NewOpc = X86::VPCMPQZ256rmibk_alt; break; 452 case X86::VPCMPQZ256rmik: NewOpc = X86::VPCMPQZ256rmik_alt; break; 453 case X86::VPCMPQZ256rri: NewOpc = X86::VPCMPQZ256rri_alt; break; 454 case X86::VPCMPQZ256rrik: NewOpc = X86::VPCMPQZ256rrik_alt; break; 455 case X86::VPCMPQZrmi: NewOpc = X86::VPCMPQZrmi_alt; break; 456 case X86::VPCMPQZrmib: NewOpc = X86::VPCMPQZrmib_alt; break; 457 case X86::VPCMPQZrmibk: NewOpc = X86::VPCMPQZrmibk_alt; break; 458 case X86::VPCMPQZrmik: NewOpc = X86::VPCMPQZrmik_alt; break; 459 case X86::VPCMPQZrri: NewOpc = X86::VPCMPQZrri_alt; break; 460 case X86::VPCMPQZrrik: NewOpc = X86::VPCMPQZrrik_alt; break; 461 case X86::VPCMPUBZ128rmi: NewOpc = X86::VPCMPUBZ128rmi_alt; break; 462 case X86::VPCMPUBZ128rmik: NewOpc = X86::VPCMPUBZ128rmik_alt; break; 463 case X86::VPCMPUBZ128rri: NewOpc = X86::VPCMPUBZ128rri_alt; break; 464 case X86::VPCMPUBZ128rrik: NewOpc = X86::VPCMPUBZ128rrik_alt; break; 465 case X86::VPCMPUBZ256rmi: NewOpc = X86::VPCMPUBZ256rmi_alt; break; 466 case X86::VPCMPUBZ256rmik: NewOpc = X86::VPCMPUBZ256rmik_alt; break; 467 case X86::VPCMPUBZ256rri: NewOpc = X86::VPCMPUBZ256rri_alt; break; 468 case X86::VPCMPUBZ256rrik: NewOpc = X86::VPCMPUBZ256rrik_alt; break; 469 case X86::VPCMPUBZrmi: NewOpc = X86::VPCMPUBZrmi_alt; break; 470 case X86::VPCMPUBZrmik: NewOpc = X86::VPCMPUBZrmik_alt; break; 471 case X86::VPCMPUBZrri: NewOpc = X86::VPCMPUBZrri_alt; break; 472 case X86::VPCMPUBZrrik: NewOpc = X86::VPCMPUBZrrik_alt; break; 473 case X86::VPCMPUDZ128rmi: NewOpc = X86::VPCMPUDZ128rmi_alt; break; 474 case X86::VPCMPUDZ128rmib: NewOpc = X86::VPCMPUDZ128rmib_alt; break; 475 case X86::VPCMPUDZ128rmibk: NewOpc = X86::VPCMPUDZ128rmibk_alt; break; 476 case X86::VPCMPUDZ128rmik: NewOpc = X86::VPCMPUDZ128rmik_alt; break; 477 case X86::VPCMPUDZ128rri: NewOpc = X86::VPCMPUDZ128rri_alt; break; 478 case X86::VPCMPUDZ128rrik: NewOpc = X86::VPCMPUDZ128rrik_alt; break; 479 case X86::VPCMPUDZ256rmi: NewOpc = X86::VPCMPUDZ256rmi_alt; break; 480 case X86::VPCMPUDZ256rmib: NewOpc = X86::VPCMPUDZ256rmib_alt; break; 481 case X86::VPCMPUDZ256rmibk: NewOpc = X86::VPCMPUDZ256rmibk_alt; break; 482 case X86::VPCMPUDZ256rmik: NewOpc = X86::VPCMPUDZ256rmik_alt; break; 483 case X86::VPCMPUDZ256rri: NewOpc = X86::VPCMPUDZ256rri_alt; break; 484 case X86::VPCMPUDZ256rrik: NewOpc = X86::VPCMPUDZ256rrik_alt; break; 485 case X86::VPCMPUDZrmi: NewOpc = X86::VPCMPUDZrmi_alt; break; 486 case X86::VPCMPUDZrmib: NewOpc = X86::VPCMPUDZrmib_alt; break; 487 case X86::VPCMPUDZrmibk: NewOpc = X86::VPCMPUDZrmibk_alt; break; 488 case X86::VPCMPUDZrmik: NewOpc = X86::VPCMPUDZrmik_alt; break; 489 case X86::VPCMPUDZrri: NewOpc = X86::VPCMPUDZrri_alt; break; 490 case X86::VPCMPUDZrrik: NewOpc = X86::VPCMPUDZrrik_alt; break; 491 case X86::VPCMPUQZ128rmi: NewOpc = X86::VPCMPUQZ128rmi_alt; break; 492 case X86::VPCMPUQZ128rmib: NewOpc = X86::VPCMPUQZ128rmib_alt; break; 493 case X86::VPCMPUQZ128rmibk: NewOpc = X86::VPCMPUQZ128rmibk_alt; break; 494 case X86::VPCMPUQZ128rmik: NewOpc = X86::VPCMPUQZ128rmik_alt; break; 495 case X86::VPCMPUQZ128rri: NewOpc = X86::VPCMPUQZ128rri_alt; break; 496 case X86::VPCMPUQZ128rrik: NewOpc = X86::VPCMPUQZ128rrik_alt; break; 497 case X86::VPCMPUQZ256rmi: NewOpc = X86::VPCMPUQZ256rmi_alt; break; 498 case X86::VPCMPUQZ256rmib: NewOpc = X86::VPCMPUQZ256rmib_alt; break; 499 case X86::VPCMPUQZ256rmibk: NewOpc = X86::VPCMPUQZ256rmibk_alt; break; 500 case X86::VPCMPUQZ256rmik: NewOpc = X86::VPCMPUQZ256rmik_alt; break; 501 case X86::VPCMPUQZ256rri: NewOpc = X86::VPCMPUQZ256rri_alt; break; 502 case X86::VPCMPUQZ256rrik: NewOpc = X86::VPCMPUQZ256rrik_alt; break; 503 case X86::VPCMPUQZrmi: NewOpc = X86::VPCMPUQZrmi_alt; break; 504 case X86::VPCMPUQZrmib: NewOpc = X86::VPCMPUQZrmib_alt; break; 505 case X86::VPCMPUQZrmibk: NewOpc = X86::VPCMPUQZrmibk_alt; break; 506 case X86::VPCMPUQZrmik: NewOpc = X86::VPCMPUQZrmik_alt; break; 507 case X86::VPCMPUQZrri: NewOpc = X86::VPCMPUQZrri_alt; break; 508 case X86::VPCMPUQZrrik: NewOpc = X86::VPCMPUQZrrik_alt; break; 509 case X86::VPCMPUWZ128rmi: NewOpc = X86::VPCMPUWZ128rmi_alt; break; 510 case X86::VPCMPUWZ128rmik: NewOpc = X86::VPCMPUWZ128rmik_alt; break; 511 case X86::VPCMPUWZ128rri: NewOpc = X86::VPCMPUWZ128rri_alt; break; 512 case X86::VPCMPUWZ128rrik: NewOpc = X86::VPCMPUWZ128rrik_alt; break; 513 case X86::VPCMPUWZ256rmi: NewOpc = X86::VPCMPUWZ256rmi_alt; break; 514 case X86::VPCMPUWZ256rmik: NewOpc = X86::VPCMPUWZ256rmik_alt; break; 515 case X86::VPCMPUWZ256rri: NewOpc = X86::VPCMPUWZ256rri_alt; break; 516 case X86::VPCMPUWZ256rrik: NewOpc = X86::VPCMPUWZ256rrik_alt; break; 517 case X86::VPCMPUWZrmi: NewOpc = X86::VPCMPUWZrmi_alt; break; 518 case X86::VPCMPUWZrmik: NewOpc = X86::VPCMPUWZrmik_alt; break; 519 case X86::VPCMPUWZrri: NewOpc = X86::VPCMPUWZrri_alt; break; 520 case X86::VPCMPUWZrrik: NewOpc = X86::VPCMPUWZrrik_alt; break; 521 case X86::VPCMPWZ128rmi: NewOpc = X86::VPCMPWZ128rmi_alt; break; 522 case X86::VPCMPWZ128rmik: NewOpc = X86::VPCMPWZ128rmik_alt; break; 523 case X86::VPCMPWZ128rri: NewOpc = X86::VPCMPWZ128rri_alt; break; 524 case X86::VPCMPWZ128rrik: NewOpc = X86::VPCMPWZ128rrik_alt; break; 525 case X86::VPCMPWZ256rmi: NewOpc = X86::VPCMPWZ256rmi_alt; break; 526 case X86::VPCMPWZ256rmik: NewOpc = X86::VPCMPWZ256rmik_alt; break; 527 case X86::VPCMPWZ256rri: NewOpc = X86::VPCMPWZ256rri_alt; break; 528 case X86::VPCMPWZ256rrik: NewOpc = X86::VPCMPWZ256rrik_alt; break; 529 case X86::VPCMPWZrmi: NewOpc = X86::VPCMPWZrmi_alt; break; 530 case X86::VPCMPWZrmik: NewOpc = X86::VPCMPWZrmik_alt; break; 531 case X86::VPCMPWZrri: NewOpc = X86::VPCMPWZrri_alt; break; 532 case X86::VPCMPWZrrik: NewOpc = X86::VPCMPWZrrik_alt; break; 533 } 534 // Switch opcode to the one that doesn't get special printing. 535 mcInst.setOpcode(NewOpc); 536 } 537 } 538 539 switch (type) { 540 case TYPE_XMM32: 541 case TYPE_XMM64: 542 case TYPE_XMM128: 543 mcInst.addOperand(MCOperand::createReg(X86::XMM0 + (immediate >> 4))); 544 return; 545 case TYPE_XMM256: 546 mcInst.addOperand(MCOperand::createReg(X86::YMM0 + (immediate >> 4))); 547 return; 548 case TYPE_XMM512: 549 mcInst.addOperand(MCOperand::createReg(X86::ZMM0 + (immediate >> 4))); 550 return; 551 case TYPE_BNDR: 552 mcInst.addOperand(MCOperand::createReg(X86::BND0 + (immediate >> 4))); 553 case TYPE_REL8: 554 isBranch = true; 555 pcrel = insn.startLocation + insn.immediateOffset + insn.immediateSize; 556 if (immediate & 0x80) 557 immediate |= ~(0xffull); 558 break; 559 case TYPE_REL16: 560 isBranch = true; 561 pcrel = insn.startLocation + insn.immediateOffset + insn.immediateSize; 562 if (immediate & 0x8000) 563 immediate |= ~(0xffffull); 564 break; 565 case TYPE_REL32: 566 case TYPE_REL64: 567 isBranch = true; 568 pcrel = insn.startLocation + insn.immediateOffset + insn.immediateSize; 569 if(immediate & 0x80000000) 570 immediate |= ~(0xffffffffull); 571 break; 572 default: 573 // operand is 64 bits wide. Do nothing. 574 break; 575 } 576 577 if(!tryAddingSymbolicOperand(immediate + pcrel, isBranch, insn.startLocation, 578 insn.immediateOffset, insn.immediateSize, 579 mcInst, Dis)) 580 mcInst.addOperand(MCOperand::createImm(immediate)); 581 582 if (type == TYPE_MOFFS8 || type == TYPE_MOFFS16 || 583 type == TYPE_MOFFS32 || type == TYPE_MOFFS64) { 584 MCOperand segmentReg; 585 segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]); 586 mcInst.addOperand(segmentReg); 587 } 588 } 589 590 /// translateRMRegister - Translates a register stored in the R/M field of the 591 /// ModR/M byte to its LLVM equivalent and appends it to an MCInst. 592 /// @param mcInst - The MCInst to append to. 593 /// @param insn - The internal instruction to extract the R/M field 594 /// from. 595 /// @return - 0 on success; -1 otherwise 596 static bool translateRMRegister(MCInst &mcInst, 597 InternalInstruction &insn) { 598 if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) { 599 debug("A R/M register operand may not have a SIB byte"); 600 return true; 601 } 602 603 switch (insn.eaBase) { 604 default: 605 debug("Unexpected EA base register"); 606 return true; 607 case EA_BASE_NONE: 608 debug("EA_BASE_NONE for ModR/M base"); 609 return true; 610 #define ENTRY(x) case EA_BASE_##x: 611 ALL_EA_BASES 612 #undef ENTRY 613 debug("A R/M register operand may not have a base; " 614 "the operand must be a register."); 615 return true; 616 #define ENTRY(x) \ 617 case EA_REG_##x: \ 618 mcInst.addOperand(MCOperand::createReg(X86::x)); break; 619 ALL_REGS 620 #undef ENTRY 621 } 622 623 return false; 624 } 625 626 /// translateRMMemory - Translates a memory operand stored in the Mod and R/M 627 /// fields of an internal instruction (and possibly its SIB byte) to a memory 628 /// operand in LLVM's format, and appends it to an MCInst. 629 /// 630 /// @param mcInst - The MCInst to append to. 631 /// @param insn - The instruction to extract Mod, R/M, and SIB fields 632 /// from. 633 /// @return - 0 on success; nonzero otherwise 634 static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn, 635 const MCDisassembler *Dis) { 636 // Addresses in an MCInst are represented as five operands: 637 // 1. basereg (register) The R/M base, or (if there is a SIB) the 638 // SIB base 639 // 2. scaleamount (immediate) 1, or (if there is a SIB) the specified 640 // scale amount 641 // 3. indexreg (register) x86_registerNONE, or (if there is a SIB) 642 // the index (which is multiplied by the 643 // scale amount) 644 // 4. displacement (immediate) 0, or the displacement if there is one 645 // 5. segmentreg (register) x86_registerNONE for now, but could be set 646 // if we have segment overrides 647 648 MCOperand baseReg; 649 MCOperand scaleAmount; 650 MCOperand indexReg; 651 MCOperand displacement; 652 MCOperand segmentReg; 653 uint64_t pcrel = 0; 654 655 if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) { 656 if (insn.sibBase != SIB_BASE_NONE) { 657 switch (insn.sibBase) { 658 default: 659 debug("Unexpected sibBase"); 660 return true; 661 #define ENTRY(x) \ 662 case SIB_BASE_##x: \ 663 baseReg = MCOperand::createReg(X86::x); break; 664 ALL_SIB_BASES 665 #undef ENTRY 666 } 667 } else { 668 baseReg = MCOperand::createReg(0); 669 } 670 671 // Check whether we are handling VSIB addressing mode for GATHER. 672 // If sibIndex was set to SIB_INDEX_NONE, index offset is 4 and 673 // we should use SIB_INDEX_XMM4|YMM4 for VSIB. 674 // I don't see a way to get the correct IndexReg in readSIB: 675 // We can tell whether it is VSIB or SIB after instruction ID is decoded, 676 // but instruction ID may not be decoded yet when calling readSIB. 677 uint32_t Opcode = mcInst.getOpcode(); 678 bool IndexIs128 = (Opcode == X86::VGATHERDPDrm || 679 Opcode == X86::VGATHERDPDYrm || 680 Opcode == X86::VGATHERQPDrm || 681 Opcode == X86::VGATHERDPSrm || 682 Opcode == X86::VGATHERQPSrm || 683 Opcode == X86::VPGATHERDQrm || 684 Opcode == X86::VPGATHERDQYrm || 685 Opcode == X86::VPGATHERQQrm || 686 Opcode == X86::VPGATHERDDrm || 687 Opcode == X86::VPGATHERQDrm); 688 bool IndexIs256 = (Opcode == X86::VGATHERQPDYrm || 689 Opcode == X86::VGATHERDPSYrm || 690 Opcode == X86::VGATHERQPSYrm || 691 Opcode == X86::VGATHERDPDZrm || 692 Opcode == X86::VPGATHERDQZrm || 693 Opcode == X86::VPGATHERQQYrm || 694 Opcode == X86::VPGATHERDDYrm || 695 Opcode == X86::VPGATHERQDYrm); 696 bool IndexIs512 = (Opcode == X86::VGATHERQPDZrm || 697 Opcode == X86::VGATHERDPSZrm || 698 Opcode == X86::VGATHERQPSZrm || 699 Opcode == X86::VPGATHERQQZrm || 700 Opcode == X86::VPGATHERDDZrm || 701 Opcode == X86::VPGATHERQDZrm); 702 if (IndexIs128 || IndexIs256 || IndexIs512) { 703 unsigned IndexOffset = insn.sibIndex - 704 (insn.addressSize == 8 ? SIB_INDEX_RAX:SIB_INDEX_EAX); 705 SIBIndex IndexBase = IndexIs512 ? SIB_INDEX_ZMM0 : 706 IndexIs256 ? SIB_INDEX_YMM0 : SIB_INDEX_XMM0; 707 insn.sibIndex = (SIBIndex)(IndexBase + 708 (insn.sibIndex == SIB_INDEX_NONE ? 4 : IndexOffset)); 709 } 710 711 if (insn.sibIndex != SIB_INDEX_NONE) { 712 switch (insn.sibIndex) { 713 default: 714 debug("Unexpected sibIndex"); 715 return true; 716 #define ENTRY(x) \ 717 case SIB_INDEX_##x: \ 718 indexReg = MCOperand::createReg(X86::x); break; 719 EA_BASES_32BIT 720 EA_BASES_64BIT 721 REGS_XMM 722 REGS_YMM 723 REGS_ZMM 724 #undef ENTRY 725 } 726 } else { 727 indexReg = MCOperand::createReg(0); 728 } 729 730 scaleAmount = MCOperand::createImm(insn.sibScale); 731 } else { 732 switch (insn.eaBase) { 733 case EA_BASE_NONE: 734 if (insn.eaDisplacement == EA_DISP_NONE) { 735 debug("EA_BASE_NONE and EA_DISP_NONE for ModR/M base"); 736 return true; 737 } 738 if (insn.mode == MODE_64BIT){ 739 pcrel = insn.startLocation + 740 insn.displacementOffset + insn.displacementSize; 741 tryAddingPcLoadReferenceComment(insn.startLocation + 742 insn.displacementOffset, 743 insn.displacement + pcrel, Dis); 744 baseReg = MCOperand::createReg(X86::RIP); // Section 2.2.1.6 745 } 746 else 747 baseReg = MCOperand::createReg(0); 748 749 indexReg = MCOperand::createReg(0); 750 break; 751 case EA_BASE_BX_SI: 752 baseReg = MCOperand::createReg(X86::BX); 753 indexReg = MCOperand::createReg(X86::SI); 754 break; 755 case EA_BASE_BX_DI: 756 baseReg = MCOperand::createReg(X86::BX); 757 indexReg = MCOperand::createReg(X86::DI); 758 break; 759 case EA_BASE_BP_SI: 760 baseReg = MCOperand::createReg(X86::BP); 761 indexReg = MCOperand::createReg(X86::SI); 762 break; 763 case EA_BASE_BP_DI: 764 baseReg = MCOperand::createReg(X86::BP); 765 indexReg = MCOperand::createReg(X86::DI); 766 break; 767 default: 768 indexReg = MCOperand::createReg(0); 769 switch (insn.eaBase) { 770 default: 771 debug("Unexpected eaBase"); 772 return true; 773 // Here, we will use the fill-ins defined above. However, 774 // BX_SI, BX_DI, BP_SI, and BP_DI are all handled above and 775 // sib and sib64 were handled in the top-level if, so they're only 776 // placeholders to keep the compiler happy. 777 #define ENTRY(x) \ 778 case EA_BASE_##x: \ 779 baseReg = MCOperand::createReg(X86::x); break; 780 ALL_EA_BASES 781 #undef ENTRY 782 #define ENTRY(x) case EA_REG_##x: 783 ALL_REGS 784 #undef ENTRY 785 debug("A R/M memory operand may not be a register; " 786 "the base field must be a base."); 787 return true; 788 } 789 } 790 791 scaleAmount = MCOperand::createImm(1); 792 } 793 794 displacement = MCOperand::createImm(insn.displacement); 795 796 segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]); 797 798 mcInst.addOperand(baseReg); 799 mcInst.addOperand(scaleAmount); 800 mcInst.addOperand(indexReg); 801 if(!tryAddingSymbolicOperand(insn.displacement + pcrel, false, 802 insn.startLocation, insn.displacementOffset, 803 insn.displacementSize, mcInst, Dis)) 804 mcInst.addOperand(displacement); 805 mcInst.addOperand(segmentReg); 806 return false; 807 } 808 809 /// translateRM - Translates an operand stored in the R/M (and possibly SIB) 810 /// byte of an instruction to LLVM form, and appends it to an MCInst. 811 /// 812 /// @param mcInst - The MCInst to append to. 813 /// @param operand - The operand, as stored in the descriptor table. 814 /// @param insn - The instruction to extract Mod, R/M, and SIB fields 815 /// from. 816 /// @return - 0 on success; nonzero otherwise 817 static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand, 818 InternalInstruction &insn, const MCDisassembler *Dis) { 819 switch (operand.type) { 820 default: 821 debug("Unexpected type for a R/M operand"); 822 return true; 823 case TYPE_R8: 824 case TYPE_R16: 825 case TYPE_R32: 826 case TYPE_R64: 827 case TYPE_Rv: 828 case TYPE_MM64: 829 case TYPE_XMM: 830 case TYPE_XMM32: 831 case TYPE_XMM64: 832 case TYPE_XMM128: 833 case TYPE_XMM256: 834 case TYPE_XMM512: 835 case TYPE_VK1: 836 case TYPE_VK2: 837 case TYPE_VK4: 838 case TYPE_VK8: 839 case TYPE_VK16: 840 case TYPE_VK32: 841 case TYPE_VK64: 842 case TYPE_DEBUGREG: 843 case TYPE_CONTROLREG: 844 case TYPE_BNDR: 845 return translateRMRegister(mcInst, insn); 846 case TYPE_M: 847 case TYPE_M8: 848 case TYPE_M16: 849 case TYPE_M32: 850 case TYPE_M64: 851 case TYPE_M128: 852 case TYPE_M256: 853 case TYPE_M512: 854 case TYPE_Mv: 855 case TYPE_M32FP: 856 case TYPE_M64FP: 857 case TYPE_M80FP: 858 case TYPE_M1616: 859 case TYPE_M1632: 860 case TYPE_M1664: 861 case TYPE_LEA: 862 return translateRMMemory(mcInst, insn, Dis); 863 } 864 } 865 866 /// translateFPRegister - Translates a stack position on the FPU stack to its 867 /// LLVM form, and appends it to an MCInst. 868 /// 869 /// @param mcInst - The MCInst to append to. 870 /// @param stackPos - The stack position to translate. 871 static void translateFPRegister(MCInst &mcInst, 872 uint8_t stackPos) { 873 mcInst.addOperand(MCOperand::createReg(X86::ST0 + stackPos)); 874 } 875 876 /// translateMaskRegister - Translates a 3-bit mask register number to 877 /// LLVM form, and appends it to an MCInst. 878 /// 879 /// @param mcInst - The MCInst to append to. 880 /// @param maskRegNum - Number of mask register from 0 to 7. 881 /// @return - false on success; true otherwise. 882 static bool translateMaskRegister(MCInst &mcInst, 883 uint8_t maskRegNum) { 884 if (maskRegNum >= 8) { 885 debug("Invalid mask register number"); 886 return true; 887 } 888 889 mcInst.addOperand(MCOperand::createReg(X86::K0 + maskRegNum)); 890 return false; 891 } 892 893 /// translateOperand - Translates an operand stored in an internal instruction 894 /// to LLVM's format and appends it to an MCInst. 895 /// 896 /// @param mcInst - The MCInst to append to. 897 /// @param operand - The operand, as stored in the descriptor table. 898 /// @param insn - The internal instruction. 899 /// @return - false on success; true otherwise. 900 static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand, 901 InternalInstruction &insn, 902 const MCDisassembler *Dis) { 903 switch (operand.encoding) { 904 default: 905 debug("Unhandled operand encoding during translation"); 906 return true; 907 case ENCODING_REG: 908 translateRegister(mcInst, insn.reg); 909 return false; 910 case ENCODING_WRITEMASK: 911 return translateMaskRegister(mcInst, insn.writemask); 912 CASE_ENCODING_RM: 913 return translateRM(mcInst, operand, insn, Dis); 914 case ENCODING_CB: 915 case ENCODING_CW: 916 case ENCODING_CD: 917 case ENCODING_CP: 918 case ENCODING_CO: 919 case ENCODING_CT: 920 debug("Translation of code offsets isn't supported."); 921 return true; 922 case ENCODING_IB: 923 case ENCODING_IW: 924 case ENCODING_ID: 925 case ENCODING_IO: 926 case ENCODING_Iv: 927 case ENCODING_Ia: 928 translateImmediate(mcInst, 929 insn.immediates[insn.numImmediatesTranslated++], 930 operand, 931 insn, 932 Dis); 933 return false; 934 case ENCODING_SI: 935 return translateSrcIndex(mcInst, insn); 936 case ENCODING_DI: 937 return translateDstIndex(mcInst, insn); 938 case ENCODING_RB: 939 case ENCODING_RW: 940 case ENCODING_RD: 941 case ENCODING_RO: 942 case ENCODING_Rv: 943 translateRegister(mcInst, insn.opcodeRegister); 944 return false; 945 case ENCODING_FP: 946 translateFPRegister(mcInst, insn.modRM & 7); 947 return false; 948 case ENCODING_VVVV: 949 translateRegister(mcInst, insn.vvvv); 950 return false; 951 case ENCODING_DUP: 952 return translateOperand(mcInst, insn.operands[operand.type - TYPE_DUP0], 953 insn, Dis); 954 } 955 } 956 957 /// translateInstruction - Translates an internal instruction and all its 958 /// operands to an MCInst. 959 /// 960 /// @param mcInst - The MCInst to populate with the instruction's data. 961 /// @param insn - The internal instruction. 962 /// @return - false on success; true otherwise. 963 static bool translateInstruction(MCInst &mcInst, 964 InternalInstruction &insn, 965 const MCDisassembler *Dis) { 966 if (!insn.spec) { 967 debug("Instruction has no specification"); 968 return true; 969 } 970 971 mcInst.clear(); 972 mcInst.setOpcode(insn.instructionID); 973 // If when reading the prefix bytes we determined the overlapping 0xf2 or 0xf3 974 // prefix bytes should be disassembled as xrelease and xacquire then set the 975 // opcode to those instead of the rep and repne opcodes. 976 if (insn.xAcquireRelease) { 977 if(mcInst.getOpcode() == X86::REP_PREFIX) 978 mcInst.setOpcode(X86::XRELEASE_PREFIX); 979 else if(mcInst.getOpcode() == X86::REPNE_PREFIX) 980 mcInst.setOpcode(X86::XACQUIRE_PREFIX); 981 } 982 983 insn.numImmediatesTranslated = 0; 984 985 for (const auto &Op : insn.operands) { 986 if (Op.encoding != ENCODING_NONE) { 987 if (translateOperand(mcInst, Op, insn, Dis)) { 988 return true; 989 } 990 } 991 } 992 993 return false; 994 } 995 996 static MCDisassembler *createX86Disassembler(const Target &T, 997 const MCSubtargetInfo &STI, 998 MCContext &Ctx) { 999 std::unique_ptr<const MCInstrInfo> MII(T.createMCInstrInfo()); 1000 return new X86Disassembler::X86GenericDisassembler(STI, Ctx, std::move(MII)); 1001 } 1002 1003 extern "C" void LLVMInitializeX86Disassembler() { 1004 // Register the disassembler. 1005 TargetRegistry::RegisterMCDisassembler(TheX86_32Target, 1006 createX86Disassembler); 1007 TargetRegistry::RegisterMCDisassembler(TheX86_64Target, 1008 createX86Disassembler); 1009 } 1010
