| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | 1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
15 #include "X86.h"
44 #define DEBUG_TYPE "x86-instr-info"
55 " fuse, but the X86 backend currently can't"),
105 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
106 : X86::ADJCALLSTACKDOWN32),
107 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
108 : X86::ADJCALLSTACKUP32),
109 X86::CATCHRET)
[all...] |
| X86RegisterInfo.cpp | 1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
12 // on X86.
48 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
52 : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP),
55 (TT.isArch64Bit() ? X86::RIP : X86::EIP)) {
71 StackPtr = Use64BitReg ? X86::RSP : X86::ESP
[all...] |
| X86FloatingPoint.cpp | 26 #include "X86.h"
51 #define DEBUG_TYPE "x86-codegen"
79 const char *getPassName() const override { return "X86 FP Stackifier"; }
124 if (LI.PhysReg < X86::FP0 || LI.PhysReg > X86::FP6)
126 Mask |= 1 << (LI.PhysReg - X86::FP0);
182 /// getStackEntry - Return the X86::FP<n> register in register ST(i).
189 /// getSTReg - Return the X86::ST(i) register which contains the specified
192 return StackTop - 1 - getSlot(RegNo) + X86::ST0;
221 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg)
[all...] |
| X86MCInstLower.cpp | 1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
10 // This file contains code to lower X86 MachineInstrs to their corresponding
309 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
327 case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw
328 if (Op0 == X86::AX && Op1 == X86::AL)
329 NewOpcode = X86::CBW
[all...] |
| X86ExpandPseudo.cpp | 16 #include "X86.h"
29 #define DEBUG_TYPE "x86-pseudo"
52 return "X86 pseudo instruction expansion pass";
73 case X86::TCRETURNdi:
74 case X86::TCRETURNri:
75 case X86::TCRETURNmi:
76 case X86::TCRETURNdi64:
77 case X86::TCRETURNri64:
78 case X86::TCRETURNmi64: {
79 bool isMem = Opcode == X86::TCRETURNmi || Opcode == X86::TCRETURNmi64
[all...] |
| X86FixupLEAs.cpp | 16 #include "X86.h"
30 #define DEBUG_TYPE "x86-fixup-LEAs"
43 const char *getPassName() const override { return "X86 LEA Fixup"; }
110 case X86::MOV32rr:
111 case X86::MOV64rr: {
115 TII->get(MI->getOpcode() == X86::MOV32rr ? X86::LEA32r
116 : X86::LEA64r))
126 case X86::ADD64ri32:
127 case X86::ADD64ri8
[all...] |
| X86FastISel.cpp | 1 //===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===//
10 // This file defines the X86-specific support for the FastISel class. Much
16 #include "X86.h"
167 bool foldX86XALUIntrinsic(X86::CondCode &CC, const Instruction *I,
176 static std::pair<X86::CondCode, bool>
178 X86::CondCode CC = X86::COND_INVALID;
183 case CmpInst::FCMP_UEQ: CC = X86::COND_E; break;
185 case CmpInst::FCMP_OGT: CC = X86::COND_A; break;
187 case CmpInst::FCMP_OGE: CC = X86::COND_AE; break
[all...] |
| X86FrameLowering.cpp | 1 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
10 // This file contains the X86 implementation of TargetFrameLowering class.
73 // So, this is required for x86 functions that have push sequences even
100 return X86::SUB64ri8;
101 return X86::SUB64ri32;
104 return X86::SUB32ri8;
105 return X86::SUB32ri;
112 return X86::ADD64ri8;
113 return X86::ADD64ri32;
116 return X86::ADD32ri8
[all...] |
| X86MachineFunctionInfo.cpp | 1 //===-- X86MachineFunctionInfo.cpp - X86 machine function info ------------===//
28 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
|
| X86ISelDAGToDAG.cpp | 1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
10 // This file defines a DAG pattern matching instruction selector for X86,
11 // converting from a legalized dag to a X86 dag.
15 #include "X86.h"
40 #define DEBUG_TYPE "x86-isel"
94 return RegNode->getReg() == X86::RIP;
148 /// ISel - X86-specific code to select X86 machine instructions for
169 return "X86 DAG->DAG Instruction Selection";
350 if ((RegNode->getReg() == X86::ESP) |
[all...] |
| X86OptimizeLEAs.cpp | 18 #include "X86.h"
34 #define DEBUG_TYPE "x86-optimize-LEAs"
36 static cl::opt<bool> EnableX86LEAOpt("enable-x86-lea-opt", cl::Hidden,
37 cl::desc("X86: Enable LEA optimizations."),
47 const char *getPassName() const override { return "X86 LEA Optimize"; }
148 if (TII->getRegClass(Desc, MemOpNo + X86::AddrBaseReg, TRI, *MF) !=
188 return Opcode == X86::LEA16r || Opcode == X86::LEA32r ||
189 Opcode == X86::LEA64r || Opcode == X86::LEA64_32r
[all...] |
| X86SelectionDAGInfo.cpp | 1 //===-- X86SelectionDAGInfo.cpp - X86 SelectionDAG Info -------------------===//
25 #define DEBUG_TYPE "x86-selectiondag-info"
57 const unsigned ClobberSet[] = {X86::RCX, X86::RAX, X86::RDI,
58 X86::ECX, X86::EAX, X86::EDI};
117 ValReg = X86::AX;
122 ValReg = X86::EAX
[all...] |
| /external/llvm/lib/Target/X86/Disassembler/ |
| X86Disassembler.cpp | 1 //===-- X86Disassembler.cpp - Disassembler for x86 and x86_64 -------------===//
10 // This file is part of the X86 Disassembler.
32 #define DEBUG_TYPE "x86-disassembler"
59 namespace X86 {
84 if (FB[X86::Mode16Bit]) {
87 } else if (FB[X86::Mode32Bit]) {
90 } else if (FB[X86::Mode64Bit]) {
176 #define ENTRY(x) X86::x,
229 X86::CS,
230 X86::SS
[all...] |
| /external/eclipse-basebuilder/basebuilder-3.6.2/org.eclipse.releng.basebuilder/plugins/org.eclipse.equinox.launcher.gtk.linux.x86_1.1.2.R36x_v20101019_1345/ |
| launcher.gtk.linux.x86.properties | 11 pluginName = Equinox Launcher Linux X86 Fragment
|
| /external/eclipse-basebuilder/basebuilder-3.6.2/org.eclipse.releng.basebuilder/plugins/org.eclipse.equinox.launcher.win32.win32.x86_1.1.2.R36x_v20101019_1345/ |
| launcher.win32.win32.x86.properties | 11 pluginName = Equinox Launcher Win32 X86 Fragment
|
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86InstComments.cpp | 10 // This defines functionality used to emit comments about X86 instructions to
25 if (X86::ZMM0 <= RegNo && RegNo <= X86::ZMM31)
27 if (X86::YMM0 <= RegNo && RegNo <= X86::YMM31)
29 if (X86::XMM0 <= RegNo && RegNo <= X86::XMM31)
31 if (X86::MM0 <= RegNo && RegNo <= X86::MM7)
54 case X86::PMOVZXBWrm
[all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86AsmBackend.cpp | 1 //===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
45 case X86::reloc_riprel_4byte:
46 case X86::reloc_riprel_4byte_movq_load:
47 case X86::reloc_signed_4byte:
48 case X86::reloc_global_offset_table:
55 case X86::reloc_global_offset_table8:
88 return X86::NumTargetFixupKinds;
92 const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = {
142 case X86::JAE_1: return X86::JAE_4
[all...] |
| X86BaseInfo.h | 1 //===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===//
11 // the X86 target useful for the compiler back-end and the MC libraries.
27 namespace X86 {
44 } // end namespace X86;
53 // X86 Specific MachineOperand flags.
70 /// See the X86-64 ELF ABI supplement for more details.
77 /// See the X86-64 ELF ABI supplement for more details.
85 /// See the X86-64 ELF ABI supplement for more details.
92 /// See the X86-64 ELF ABI supplement for more details.
109 /// block for the symbol. Used in the x86-64 local dynamic TLS access model
[all...] |
| X86FixupKinds.h | 1 //===-- X86FixupKinds.h - X86 Specific Fixup Entries ------------*- C++ -*-===//
16 namespace X86 {
|
| X86WinCOFFObjectWriter.cpp | 1 //===-- X86WinCOFFObjectWriter.cpp - X86 Win COFF Writer ------------------===//
54 case X86::reloc_riprel_4byte:
55 case X86::reloc_riprel_4byte_movq_load:
58 case X86::reloc_signed_4byte:
74 case X86::reloc_riprel_4byte:
75 case X86::reloc_riprel_4byte_movq_load:
78 case X86::reloc_signed_4byte:
|
| /external/lzma/Java/Tukaani/src/org/tukaani/xz/ |
| X86Options.java | 13 import org.tukaani.xz.simple.X86;
16 * BCJ filter for x86 (32-bit and 64-bit) instructions.
26 return new SimpleOutputStream(out, new X86(true, startOffset));
30 return new SimpleInputStream(in, new X86(false, startOffset));
|
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmInstrumentation.cpp | 1 //===-- X86AsmInstrumentation.cpp - Instrument X86 inline assembly C++ -*-===//
117 bool IsStackReg(unsigned Reg) { return Reg == X86::RSP || Reg == X86::ESP; }
152 if (Reg != X86::NoRegister)
162 static const MCPhysReg Candidates[] = { X86::RBP, X86::RAX, X86::RBX,
163 X86::RCX, X86::RDX, X86::RDI
[all...] |
| X86Operand.h | 1 //===-- X86Operand.h - Parsed X86 machine instruction --------------------===//
23 /// X86Operand - Instances of this class represent a parsed X86 machine
239 getMemIndexReg() >= X86::XMM0 && getMemIndexReg() <= X86::XMM15;
243 getMemIndexReg() >= X86::XMM0 && getMemIndexReg() <= X86::XMM31;
247 getMemIndexReg() >= X86::YMM0 && getMemIndexReg() <= X86::YMM15;
251 getMemIndexReg() >= X86::YMM0 && getMemIndexReg() <= X86::YMM31
[all...] |
| /art/tools/dexfuzz/src/dexfuzz/executors/ |
| Architecture.java | 25 X86("x86"),
|
| /external/llvm/host/include/llvm/Config/ |
| Targets.def | 28 LLVM_TARGET(X86)
|
