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      1 //=== HexagonSplitConst32AndConst64.cpp - split CONST32/Const64 into HI/LO ===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // When the compiler is invoked with no small data, for instance, with the -G0
     11 // command line option, then all CONST32_* opcodes should be broken down into
     12 // appropriate LO and HI instructions. This splitting is done by this pass.
     13 // The only reason this is not done in the DAG lowering itself is that there
     14 // is no simple way of getting the register allocator to allot the same hard
     15 // register to the result of LO and HI instructions. This pass is always
     16 // scheduled after register allocation.
     17 //
     18 //===----------------------------------------------------------------------===//
     19 
     20 #include "HexagonMachineFunctionInfo.h"
     21 #include "HexagonSubtarget.h"
     22 #include "HexagonTargetMachine.h"
     23 #include "HexagonTargetObjectFile.h"
     24 #include "llvm/ADT/Statistic.h"
     25 #include "llvm/CodeGen/LatencyPriorityQueue.h"
     26 #include "llvm/CodeGen/MachineDominators.h"
     27 #include "llvm/CodeGen/MachineFunctionPass.h"
     28 #include "llvm/CodeGen/MachineInstrBuilder.h"
     29 #include "llvm/CodeGen/MachineLoopInfo.h"
     30 #include "llvm/CodeGen/MachineRegisterInfo.h"
     31 #include "llvm/CodeGen/Passes.h"
     32 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
     33 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
     34 #include "llvm/CodeGen/SchedulerRegistry.h"
     35 #include "llvm/Support/CommandLine.h"
     36 #include "llvm/Support/Compiler.h"
     37 #include "llvm/Support/Debug.h"
     38 #include "llvm/Support/MathExtras.h"
     39 #include "llvm/Target/TargetInstrInfo.h"
     40 #include "llvm/Target/TargetMachine.h"
     41 #include "llvm/Target/TargetRegisterInfo.h"
     42 #include <map>
     43 
     44 using namespace llvm;
     45 
     46 #define DEBUG_TYPE "xfer"
     47 
     48 namespace llvm {
     49   FunctionPass *createHexagonSplitConst32AndConst64();
     50   void initializeHexagonSplitConst32AndConst64Pass(PassRegistry&);
     51 }
     52 
     53 namespace {
     54 
     55 class HexagonSplitConst32AndConst64 : public MachineFunctionPass {
     56  public:
     57     static char ID;
     58     HexagonSplitConst32AndConst64() : MachineFunctionPass(ID) {}
     59 
     60     const char *getPassName() const override {
     61       return "Hexagon Split Const32s and Const64s";
     62     }
     63     bool runOnMachineFunction(MachineFunction &Fn) override;
     64 };
     65 
     66 
     67 char HexagonSplitConst32AndConst64::ID = 0;
     68 
     69 
     70 bool HexagonSplitConst32AndConst64::runOnMachineFunction(MachineFunction &Fn) {
     71 
     72   const HexagonTargetObjectFile &TLOF =
     73       *static_cast<const HexagonTargetObjectFile *>(
     74           Fn.getTarget().getObjFileLowering());
     75   if (TLOF.IsSmallDataEnabled())
     76     return true;
     77 
     78   const TargetInstrInfo *TII = Fn.getSubtarget().getInstrInfo();
     79   const TargetRegisterInfo *TRI = Fn.getSubtarget().getRegisterInfo();
     80 
     81   // Loop over all of the basic blocks
     82   for (MachineFunction::iterator MBBb = Fn.begin(), MBBe = Fn.end();
     83        MBBb != MBBe; ++MBBb) {
     84     MachineBasicBlock *MBB = &*MBBb;
     85     // Traverse the basic block
     86     MachineBasicBlock::iterator MII = MBB->begin();
     87     MachineBasicBlock::iterator MIE = MBB->end ();
     88     while (MII != MIE) {
     89       MachineInstr *MI = MII;
     90       int Opc = MI->getOpcode();
     91       if (Opc == Hexagon::CONST32_Int_Real &&
     92           MI->getOperand(1).isBlockAddress()) {
     93         int DestReg = MI->getOperand(0).getReg();
     94         MachineOperand &Symbol = MI->getOperand (1);
     95 
     96         BuildMI (*MBB, MII, MI->getDebugLoc(),
     97                  TII->get(Hexagon::LO), DestReg).addOperand(Symbol);
     98         BuildMI (*MBB, MII, MI->getDebugLoc(),
     99                  TII->get(Hexagon::HI), DestReg).addOperand(Symbol);
    100         // MBB->erase returns the iterator to the next instruction, which is the
    101         // one we want to process next
    102         MII = MBB->erase (MI);
    103         continue;
    104       }
    105 
    106       else if (Opc == Hexagon::CONST32_Int_Real ||
    107                Opc == Hexagon::CONST32_Float_Real) {
    108         int DestReg = MI->getOperand(0).getReg();
    109 
    110         // We have to convert an FP immediate into its corresponding integer
    111         // representation
    112         int64_t ImmValue;
    113         if (Opc == Hexagon::CONST32_Float_Real) {
    114           APFloat Val = MI->getOperand(1).getFPImm()->getValueAPF();
    115           ImmValue = *Val.bitcastToAPInt().getRawData();
    116         }
    117         else
    118           ImmValue = MI->getOperand(1).getImm();
    119 
    120         BuildMI(*MBB, MII, MI->getDebugLoc(),
    121                  TII->get(Hexagon::A2_tfrsi), DestReg).addImm(ImmValue);
    122         MII = MBB->erase (MI);
    123         continue;
    124       }
    125       else if (Opc == Hexagon::CONST64_Int_Real ||
    126                Opc == Hexagon::CONST64_Float_Real) {
    127         int DestReg = MI->getOperand(0).getReg();
    128 
    129         // We have to convert an FP immediate into its corresponding integer
    130         // representation
    131         int64_t ImmValue;
    132         if (Opc == Hexagon::CONST64_Float_Real) {
    133           APFloat Val =  MI->getOperand(1).getFPImm()->getValueAPF();
    134           ImmValue = *Val.bitcastToAPInt().getRawData();
    135         }
    136         else
    137           ImmValue = MI->getOperand(1).getImm();
    138 
    139         unsigned DestLo = TRI->getSubReg(DestReg, Hexagon::subreg_loreg);
    140         unsigned DestHi = TRI->getSubReg(DestReg, Hexagon::subreg_hireg);
    141 
    142         int32_t LowWord = (ImmValue & 0xFFFFFFFF);
    143         int32_t HighWord = (ImmValue >> 32) & 0xFFFFFFFF;
    144 
    145         BuildMI(*MBB, MII, MI->getDebugLoc(),
    146                  TII->get(Hexagon::A2_tfrsi), DestLo).addImm(LowWord);
    147         BuildMI (*MBB, MII, MI->getDebugLoc(),
    148                  TII->get(Hexagon::A2_tfrsi), DestHi).addImm(HighWord);
    149         MII = MBB->erase (MI);
    150         continue;
    151       }
    152       ++MII;
    153     }
    154   }
    155 
    156   return true;
    157 }
    158 
    159 }
    160 
    161 //===----------------------------------------------------------------------===//
    162 //                         Public Constructor Functions
    163 //===----------------------------------------------------------------------===//
    164 
    165 FunctionPass *
    166 llvm::createHexagonSplitConst32AndConst64() {
    167   return new HexagonSplitConst32AndConst64();
    168 }
    169