| /external/llvm/lib/Target/ARM/ |
| Thumb1InstrInfo.cpp | 42 unsigned DestReg, unsigned SrcReg,
48 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
52 || !ARM::tGPRRegClass.contains(DestReg))
53 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
66 .addReg(DestReg, getDefRegState(true));
98 unsigned DestReg, int FI,
102 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
103 isARMLowRegister(DestReg))) && "Unknown regclass!");
106 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
107 isARMLowRegister(DestReg))) {
[all...] |
| Thumb1InstrInfo.h | 43 unsigned DestReg, unsigned SrcReg,
53 unsigned DestReg, int FrameIndex,
|
| ThumbRegisterInfo.cpp | 64 DebugLoc dl, unsigned DestReg,
77 .addReg(DestReg, getDefRegState(true), SubIdx)
84 DebugLoc dl, unsigned DestReg,
96 .addReg(DestReg, getDefRegState(true), SubIdx)
105 unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred,
110 assert((isARMLowRegister(DestReg) || isVirtualRegister(DestReg)) &&
112 return emitThumb1LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred,
115 return emitThumb2LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred,
120 /// a destreg = basereg + immediate in Thumb code. Materialize the immediat
[all...] |
| Thumb2InstrInfo.h | 44 unsigned DestReg, unsigned SrcReg,
55 unsigned DestReg, int FrameIndex,
|
| Thumb2InstrInfo.cpp | 114 unsigned DestReg, unsigned SrcReg,
117 if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
118 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
120 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
167 unsigned DestReg, int FI,
181 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
191 MRI->constrainRegClass(DestReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
194 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
195 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
199 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
[all...] |
| ThumbRegisterInfo.h | 42 DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val,
|
| /external/llvm/lib/Target/BPF/ |
| BPFInstrInfo.h | 34 DebugLoc DL, unsigned DestReg, unsigned SrcReg,
44 MachineBasicBlock::iterator MBBI, unsigned DestReg,
|
| BPFInstrInfo.cpp | 36 unsigned DestReg, unsigned SrcReg,
38 if (BPF::GPRRegClass.contains(DestReg, SrcReg))
39 BuildMI(MBB, I, DL, get(BPF::MOV_rr), DestReg)
65 unsigned DestReg, int FI,
73 BuildMI(MBB, I, DL, get(BPF::LDD), DestReg).addFrameIndex(FI).addImm(0);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonSplitConst32AndConst64.cpp | 93 int DestReg = MI->getOperand(0).getReg();
97 TII->get(Hexagon::LO), DestReg).addOperand(Symbol);
99 TII->get(Hexagon::HI), DestReg).addOperand(Symbol);
108 int DestReg = MI->getOperand(0).getReg();
121 TII->get(Hexagon::A2_tfrsi), DestReg).addImm(ImmValue);
127 int DestReg = MI->getOperand(0).getReg();
139 unsigned DestLo = TRI->getSubReg(DestReg, Hexagon::subreg_loreg);
140 unsigned DestHi = TRI->getSubReg(DestReg, Hexagon::subreg_hireg);
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXInstrInfo.h | 48 * unsigned DestReg, int FrameIndex,
54 unsigned DestReg, unsigned SrcReg, bool KillSrc) const override;
56 unsigned &DestReg) const;
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIInstrInfo.cpp | 39 unsigned DestReg, unsigned SrcReg,
46 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
48 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
|
| SIInstrInfo.h | 35 unsigned DestReg, unsigned SrcReg,
|
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 282 unsigned DestReg, unsigned SrcReg,
296 if (SP::IntRegsRegClass.contains(DestReg, SrcReg))
297 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
299 else if (SP::IntPairRegClass.contains(DestReg, SrcReg)) {
304 } else if (SP::FPRegsRegClass.contains(DestReg, SrcReg))
305 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
307 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) {
309 BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg)
317 } else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) {
320 BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg)
[all...] |
| SparcInstrInfo.h | 81 unsigned DestReg, unsigned SrcReg,
92 unsigned DestReg, int FrameIndex,
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 81 unsigned DestReg, unsigned SrcReg,
86 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.
107 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
115 if (Mips::CCRRegClass.contains(DestReg))
117 else if (Mips::FGR32RegClass.contains(DestReg))
119 else if (Mips::HI32RegClass.contains(DestReg))
120 Opc = Mips::MTHI, DestReg = 0;
121 else if (Mips::LO32RegClass.contains(DestReg))
122 Opc = Mips::MTLO, DestReg = 0;
123 else if (Mips::HI32DSPRegClass.contains(DestReg))
[all...] |
| MipsInstrInfo.h | 99 unsigned DestReg, int FrameIndex,
102 loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0);
114 unsigned DestReg, int FrameIndex,
|
| MipsSEInstrInfo.h | 48 unsigned DestReg, unsigned SrcReg,
60 unsigned DestReg, int FrameIndex,
|
| MipsFastISel.cpp | 119 bool emitCmp(unsigned DestReg, const CmpInst *CI);
127 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
130 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
132 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
134 unsigned DestReg);
136 unsigned DestReg);
334 unsigned DestReg = createResultReg(RC);
336 emitInst(Mips::MTC1, DestReg).addReg(TempReg);
337 return DestReg;
340 unsigned DestReg = createResultReg(RC)
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrInfo.h | 57 unsigned DestReg, unsigned SrcReg,
68 unsigned DestReg, int FrameIdx,
|
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.h | 66 unsigned DestReg, unsigned SrcReg,
77 unsigned DestReg, int FrameIndex,
|
| /external/llvm/lib/Target/AMDGPU/ |
| R600MachineScheduler.cpp | 275 unsigned DestReg = MI->getOperand(0).getReg();
276 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_XRegClass) ||
277 regBelongsToClass(DestReg, &AMDGPU::R600_AddrRegClass))
279 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_YRegClass))
281 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_ZRegClass))
283 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_WRegClass))
285 if (regBelongsToClass(DestReg, &AMDGPU::R600_Reg128RegClass))
364 unsigned DestReg = MI->getOperand(DstIndex).getReg();
371 MO.getReg() == DestReg)
374 // Constrains the regclass of DestReg to assign it to Slo
[all...] |
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyInstrInfo.cpp | 37 DebugLoc DL, unsigned DestReg,
42 const TargetRegisterClass *RC = TargetRegisterInfo::isVirtualRegister(DestReg) ?
43 MRI.getRegClass(DestReg) :
58 BuildMI(MBB, I, DL, get(CopyLocalOpcode), DestReg)
|
| WebAssemblyInstrInfo.h | 38 DebugLoc DL, unsigned DestReg, unsigned SrcReg,
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 244 unsigned DestReg) {
246 .addReg(DestReg, RegState::Define);
256 unsigned DestReg) {
260 return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define);
267 unsigned DestReg) {
271 return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define);
278 unsigned DestReg) {
281 return BuildMI(BB, MII, DL, MCID, DestReg);
285 return BuildMI(BB, MII, DL, MCID, DestReg);
338 unsigned DestReg) {
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.cpp | 125 unsigned DestReg = MI->getOperand(0).getReg();
127 bool DestIsHigh = isHighReg(DestReg);
133 DestReg, SrcReg, SystemZ::LR, 32,
136 MI->getOperand(1).setReg(DestReg);
164 // DestReg before MBBI in MBB. Use LowLowOpcode when both DestReg and SrcReg
170 DebugLoc DL, unsigned DestReg,
174 bool DestIsHigh = isHighReg(DestReg);
183 BuildMI(MBB, MBBI, DL, get(LowLowOpcode), DestReg)
188 BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
[all...] |
