| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| reginfo-1.s | 0 ldc1 $f4,($4)
|
| ldc1-forward.d | 3 #name: MIPS ldc1 forward
|
| ldc1-n32.d | 3 #name: MIPS ldc1 n32
|
| ldc1-n64.d | 3 #name: MIPS ldc1 n64
|
| ldc1.d | 3 #name: MIPS ldc1
|
| mips-macro-ill-sfp.s | 5 ldc1 $f2, d
6 ldc1 $22, d
|
| l_d-n32.d | 11 [0-9a-f]+ <[^>]*> ldc1 \$f4,0\(zero\)
12 [0-9a-f]+ <[^>]*> ldc1 \$f4,1\(zero\)
14 [0-9a-f]+ <[^>]*> ldc1 \$f4,-32768\(at\)
15 [0-9a-f]+ <[^>]*> ldc1 \$f4,-32768\(zero\)
17 [0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
19 [0-9a-f]+ <[^>]*> ldc1 \$f4,-23131\(at\)
20 [0-9a-f]+ <[^>]*> ldc1 \$f4,0\(a1\)
21 [0-9a-f]+ <[^>]*> ldc1 \$f4,1\(a1\)
24 [0-9a-f]+ <[^>]*> ldc1 \$f4,-32768\(at\)
25 [0-9a-f]+ <[^>]*> ldc1 \$f4,-32768\(a1\
[all...] |
| l_d.d | 11 [0-9a-f]+ <[^>]*> ldc1 \$f4,0\(zero\)
12 [0-9a-f]+ <[^>]*> ldc1 \$f4,1\(zero\)
14 [0-9a-f]+ <[^>]*> ldc1 \$f4,-32768\(at\)
15 [0-9a-f]+ <[^>]*> ldc1 \$f4,-32768\(zero\)
17 [0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
19 [0-9a-f]+ <[^>]*> ldc1 \$f4,-23131\(at\)
20 [0-9a-f]+ <[^>]*> ldc1 \$f4,0\(a1\)
21 [0-9a-f]+ <[^>]*> ldc1 \$f4,1\(a1\)
24 [0-9a-f]+ <[^>]*> ldc1 \$f4,-32768\(at\)
25 [0-9a-f]+ <[^>]*> ldc1 \$f4,-32768\(a1\
[all...] |
| ldc1-forward-n32.d | 3 #name: MIPS ldc1 forward n32
|
| ldc1-forward-n64.d | 3 #name: MIPS ldc1 forward n64
|
| mips-macro-ill-nofp.s | 5 ldc1 $f2, d
6 ldc1 $22, d
|
| mips-macro-ill-sfp.l | 2 .*:5: Error: opcode not supported on this processor: .* \(.*\) `ldc1 \$f2,d'
3 .*:6: Error: opcode not supported on this processor: .* \(.*\) `ldc1 \$22,d'
|
| /external/valgrind/none/tests/mips32/ |
| vfp.stdout.exp-mips32-BE | 0 LDC1
2 ldc1 $f0, 0($t1) :: ft 0x666666664095a266
3 ldc1 $f0, 8($t1) :: ft 0x0bff00000
4 ldc1 $f0, 16($t1) :: ft 0x03ff00000
5 ldc1 $f0, 24($t1) :: ft 0x262d2d2a252a2e2b
6 ldc1 $f0, 32($t1) :: ft 0xffffffffffffffff
7 ldc1 $f0, 40($t1) :: ft 0xb487e5c941d26580
8 ldc1 $f0, 48($t1) :: ft 0xb750e38842026580
9 ldc1 $f0, 56($t1) :: ft 0xe2308c3a3e45798e
10 ldc1 $f0, 64($t1) :: ft 0x3746f65f3fbf9ad
[all...] |
| vfp.stdout.exp-mips32-LE | 0 LDC1
2 ldc1 $f0, 0($t1) :: ft 0x4095a26666666666
3 ldc1 $f0, 8($t1) :: ft 0xbff000000
4 ldc1 $f0, 16($t1) :: ft 0x3ff000000
5 ldc1 $f0, 24($t1) :: ft 0x252a2e2b262d2d2a
6 ldc1 $f0, 32($t1) :: ft 0xffffffffffffffff
7 ldc1 $f0, 40($t1) :: ft 0x41d26580b487e5c9
8 ldc1 $f0, 48($t1) :: ft 0x42026580b750e388
9 ldc1 $f0, 56($t1) :: ft 0x3e45798ee2308c3a
10 ldc1 $f0, 64($t1) :: ft 0x3fbf9add3746f65
[all...] |
| test_fcsr.c | 8 "ldc1 $f0, 0(%0)" "\n\t"
13 "ldc1 $f0, 8(%0)" "\n\t"
|
| vfp.stdout.exp-mips32r2-BE | 0 LDC1
2 ldc1 $f0, 0($t1) :: ft 0x666666664095a266
3 ldc1 $f0, 8($t1) :: ft 0x0bff00000
4 ldc1 $f0, 16($t1) :: ft 0x03ff00000
5 ldc1 $f0, 24($t1) :: ft 0x262d2d2a252a2e2b
6 ldc1 $f0, 32($t1) :: ft 0xffffffffffffffff
7 ldc1 $f0, 40($t1) :: ft 0xb487e5c941d26580
8 ldc1 $f0, 48($t1) :: ft 0xb750e38842026580
9 ldc1 $f0, 56($t1) :: ft 0xe2308c3a3e45798e
10 ldc1 $f0, 64($t1) :: ft 0x3746f65f3fbf9ad
[all...] |
| vfp.stdout.exp-mips32r2-LE | 0 LDC1
2 ldc1 $f0, 0($t1) :: ft 0x4095a26666666666
3 ldc1 $f0, 8($t1) :: ft 0xbff000000
4 ldc1 $f0, 16($t1) :: ft 0x3ff000000
5 ldc1 $f0, 24($t1) :: ft 0x252a2e2b262d2d2a
6 ldc1 $f0, 32($t1) :: ft 0xffffffffffffffff
7 ldc1 $f0, 40($t1) :: ft 0x41d26580b487e5c9
8 ldc1 $f0, 48($t1) :: ft 0x42026580b750e388
9 ldc1 $f0, 56($t1) :: ft 0x3e45798ee2308c3a
10 ldc1 $f0, 64($t1) :: ft 0x3fbf9add3746f65
[all...] |
| vfp.c | 47 // ldc1 $f0, 0($t1)
172 "ldc1 $f0, "#offset"($t1)\n\t" \
192 "ldc1 $f0, "#offset"($t1)\n\t" \
271 printf("LDC1\n");
272 TESTINSN5LOAD("ldc1 $f0, 0($t1)", 0, 0, f0);
273 TESTINSN5LOAD("ldc1 $f0, 8($t1)", 0, 8, f0);
274 TESTINSN5LOAD("ldc1 $f0, 16($t1)", 0, 16, f0);
275 TESTINSN5LOAD("ldc1 $f0, 24($t1)", 0, 24, f0);
276 TESTINSN5LOAD("ldc1 $f0, 32($t1)", 0, 32, f0);
277 TESTINSN5LOAD("ldc1 $f0, 40($t1)", 0, 40, f0)
[all...] |
| /external/llvm/test/CodeGen/Mips/ |
| mips64-f128-call.ll | 17 ; CHECK: ldc1 $f13, 8(${{[0-9]+}})
18 ; CHECK: ldc1 $f12, 0(${{[0-9]+}})
34 ; CHECK: ldc1 $f0, 0($[[R1]])
35 ; CHECK: ldc1 $f2, 8($[[R1]])
|
| mno-ldc1-sdc1.ll | 3 ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R1-LDC1
7 ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R6-LDC1
9 ; Check that -mno-ldc1-sdc1 disables [sl]dc1
10 ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 \
14 ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 \
18 ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 \
24 ; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 \
28 ; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 \
32 ; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 \
38 ; RUN: llc -march=mipsel -relocation-model=static -mno-ldc1-sdc1
[all...] |
| /external/llvm/test/CodeGen/Mips/cconv/ |
| callee-saved-float.ll | 61 ; O32-DAG: ldc1 [[F20]], [[OFF20]]($sp)
62 ; O32-DAG: ldc1 [[F22]], [[OFF22]]($sp)
63 ; O32-DAG: ldc1 [[F24]], [[OFF24]]($sp)
65 ; O32-DAG: ldc1 [[F26]], [[OFF26]]($sp)
67 ; O32-DAG: ldc1 [[F28]], [[OFF28]]($sp)
69 ; O32-DAG: ldc1 [[F30]], [[OFF30]]($sp)
80 ; N32-DAG: ldc1 [[F20]], [[OFF20]]($sp)
81 ; N32-DAG: ldc1 [[F22]], [[OFF22]]($sp)
82 ; N32-DAG: ldc1 [[F24]], [[OFF24]]($sp)
84 ; N32-DAG: ldc1 [[F26]], [[OFF26]]($sp
[all...] |
| /external/valgrind/none/tests/mips64/ |
| fpu_load_store.stdout.exp-BE | 1 --- LDC1 ---
2 ldc1 :: offset: 0x0, out: 0x0
3 ldc1 :: offset: 0x8, out: 0x9823b6e0d4326d9
4 ldc1 :: offset: 0x10, out: 0x130476dc17c56b6b
5 ldc1 :: offset: 0x18, out: 0x1a864db21e475005
6 ldc1 :: offset: 0x20, out: 0x2608edb822c9f00f
7 ldc1 :: offset: 0x28, out: 0x2f8ad6d62b4bcb61
8 ldc1 :: offset: 0x30, out: 0x350c9b6431cd86d3
9 ldc1 :: offset: 0x38, out: 0x3c8ea00a384fbdbd
10 ldc1 :: offset: 0x40, out: 0x4c11db7048d0c6c
[all...] |
| fpu_load_store.stdout.exp-LE | 1 --- LDC1 ---
2 ldc1 :: offset: 0x0, out: 0x0
3 ldc1 :: offset: 0x8, out: 0xd4326d909823b6e
4 ldc1 :: offset: 0x10, out: 0x17c56b6b130476dc
5 ldc1 :: offset: 0x18, out: 0x1e4750051a864db2
6 ldc1 :: offset: 0x20, out: 0x22c9f00f2608edb8
7 ldc1 :: offset: 0x28, out: 0x2b4bcb612f8ad6d6
8 ldc1 :: offset: 0x30, out: 0x31cd86d3350c9b64
9 ldc1 :: offset: 0x38, out: 0x384fbdbd3c8ea00a
10 ldc1 :: offset: 0x40, out: 0x48d0c6c74c11db7
[all...] |
| fpu_load_store.c | 14 printf("--- LDC1 ---\n");
16 TEST3("ldc1", i, reg_val1);
19 TEST3("ldc1", i, reg_val2);
|
| /external/llvm/test/MC/Mips/ |
| elf-relsym.s | 56 ldc1 $f0, %lo($CPI0_0)($2)
58 ldc1 $f2, 0($2)
60 ldc1 $f4, %lo($CPI0_1)($3)
64 ldc1 $f0, 0($1)
|
