1 ; RUN: llc -march=mips < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s 2 ; RUN: llc -march=mipsel < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s 3 ; RUN: llc -march=mips < %s | FileCheck --check-prefix=ALL --check-prefix=O32-INV %s 4 ; RUN: llc -march=mipsel < %s | FileCheck --check-prefix=ALL --check-prefix=O32-INV %s 5 6 ; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s 7 ; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s 8 ; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=ALL-INV --check-prefix=O32-INV %s 9 ; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=ALL-INV --check-prefix=O32-INV %s 10 11 ; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s 12 ; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s 13 ; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=ALL-INV --check-prefix=N32-INV %s 14 ; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=ALL-INV --check-prefix=N32-INV %s 15 16 ; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s 17 ; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s 18 ; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=ALL-INV --check-prefix=N64-INV %s 19 ; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=ALL-INV --check-prefix=N64-INV %s 20 21 ; Test the the callee-saved registers are callee-saved as specified by section 22 ; 2 of the MIPSpro N32 Handbook and section 3 of the SYSV ABI spec. 23 24 define void @fpu_clobber() nounwind { 25 entry: 26 call void asm "# Clobber", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f12},~{$f13},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"() 27 ret void 28 } 29 30 ; ALL-LABEL: fpu_clobber: 31 ; ALL-INV-NOT: sdc1 $f0, 32 ; ALL-INV-NOT: sdc1 $f1, 33 ; ALL-INV-NOT: sdc1 $f2, 34 ; ALL-INV-NOT: sdc1 $f3, 35 ; ALL-INV-NOT: sdc1 $f4, 36 ; ALL-INV-NOT: sdc1 $f5, 37 ; ALL-INV-NOT: sdc1 $f6, 38 ; ALL-INV-NOT: sdc1 $f7, 39 ; ALL-INV-NOT: sdc1 $f8, 40 ; ALL-INV-NOT: sdc1 $f9, 41 ; ALL-INV-NOT: sdc1 $f10, 42 ; ALL-INV-NOT: sdc1 $f11, 43 ; ALL-INV-NOT: sdc1 $f12, 44 ; ALL-INV-NOT: sdc1 $f13, 45 ; ALL-INV-NOT: sdc1 $f14, 46 ; ALL-INV-NOT: sdc1 $f15, 47 ; ALL-INV-NOT: sdc1 $f16, 48 ; ALL-INV-NOT: sdc1 $f17, 49 ; ALL-INV-NOT: sdc1 $f18, 50 ; ALL-INV-NOT: sdc1 $f19, 51 ; ALL-INV-NOT: sdc1 $f21, 52 ; ALL-INV-NOT: sdc1 $f23, 53 54 ; O32: addiu $sp, $sp, -48 55 ; O32-DAG: sdc1 [[F20:\$f20]], [[OFF20:[0-9]+]]($sp) 56 ; O32-DAG: sdc1 [[F22:\$f22]], [[OFF22:[0-9]+]]($sp) 57 ; O32-DAG: sdc1 [[F24:\$f24]], [[OFF24:[0-9]+]]($sp) 58 ; O32-DAG: sdc1 [[F26:\$f26]], [[OFF26:[0-9]+]]($sp) 59 ; O32-DAG: sdc1 [[F28:\$f28]], [[OFF28:[0-9]+]]($sp) 60 ; O32-DAG: sdc1 [[F30:\$f30]], [[OFF30:[0-9]+]]($sp) 61 ; O32-DAG: ldc1 [[F20]], [[OFF20]]($sp) 62 ; O32-DAG: ldc1 [[F22]], [[OFF22]]($sp) 63 ; O32-DAG: ldc1 [[F24]], [[OFF24]]($sp) 64 ; O32-INV-NOT: sdc1 $f25, 65 ; O32-DAG: ldc1 [[F26]], [[OFF26]]($sp) 66 ; O32-INV-NOT: sdc1 $f27, 67 ; O32-DAG: ldc1 [[F28]], [[OFF28]]($sp) 68 ; O32-INV-NOT: sdc1 $f29, 69 ; O32-DAG: ldc1 [[F30]], [[OFF30]]($sp) 70 ; O32-INV-NOT: sdc1 $f31, 71 ; O32: addiu $sp, $sp, 48 72 73 ; N32: addiu $sp, $sp, -48 74 ; N32-DAG: sdc1 [[F20:\$f20]], [[OFF20:[0-9]+]]($sp) 75 ; N32-DAG: sdc1 [[F22:\$f22]], [[OFF22:[0-9]+]]($sp) 76 ; N32-DAG: sdc1 [[F24:\$f24]], [[OFF24:[0-9]+]]($sp) 77 ; N32-DAG: sdc1 [[F26:\$f26]], [[OFF26:[0-9]+]]($sp) 78 ; N32-DAG: sdc1 [[F28:\$f28]], [[OFF28:[0-9]+]]($sp) 79 ; N32-DAG: sdc1 [[F30:\$f30]], [[OFF30:[0-9]+]]($sp) 80 ; N32-DAG: ldc1 [[F20]], [[OFF20]]($sp) 81 ; N32-DAG: ldc1 [[F22]], [[OFF22]]($sp) 82 ; N32-DAG: ldc1 [[F24]], [[OFF24]]($sp) 83 ; N32-INV-NOT: sdc1 $f25, 84 ; N32-DAG: ldc1 [[F26]], [[OFF26]]($sp) 85 ; N32-INV-NOT: sdc1 $f27, 86 ; N32-DAG: ldc1 [[F28]], [[OFF28]]($sp) 87 ; N32-INV-NOT: sdc1 $f29, 88 ; N32-DAG: ldc1 [[F30]], [[OFF30]]($sp) 89 ; N32-INV-NOT: sdc1 $f31, 90 ; N32: addiu $sp, $sp, 48 91 92 ; N64: addiu $sp, $sp, -64 93 ; N64-INV-NOT: sdc1 $f20, 94 ; N64-INV-NOT: sdc1 $f22, 95 ; N64-DAG: sdc1 [[F24:\$f24]], [[OFF24:[0-9]+]]($sp) 96 ; N64-DAG: sdc1 [[F25:\$f25]], [[OFF25:[0-9]+]]($sp) 97 ; N64-DAG: sdc1 [[F26:\$f26]], [[OFF26:[0-9]+]]($sp) 98 ; N64-DAG: sdc1 [[F27:\$f27]], [[OFF27:[0-9]+]]($sp) 99 ; N64-DAG: sdc1 [[F28:\$f28]], [[OFF28:[0-9]+]]($sp) 100 ; N64-DAG: sdc1 [[F29:\$f29]], [[OFF29:[0-9]+]]($sp) 101 ; N64-DAG: sdc1 [[F30:\$f30]], [[OFF30:[0-9]+]]($sp) 102 ; N64-DAG: sdc1 [[F31:\$f31]], [[OFF31:[0-9]+]]($sp) 103 ; N64-DAG: ldc1 [[F24]], [[OFF24]]($sp) 104 ; N64-DAG: ldc1 [[F25]], [[OFF25]]($sp) 105 ; N64-DAG: ldc1 [[F26]], [[OFF26]]($sp) 106 ; N64-DAG: ldc1 [[F27]], [[OFF27]]($sp) 107 ; N64-DAG: ldc1 [[F28]], [[OFF28]]($sp) 108 ; N64-DAG: ldc1 [[F29]], [[OFF29]]($sp) 109 ; N64-DAG: ldc1 [[F30]], [[OFF30]]($sp) 110 ; N64-DAG: ldc1 [[F31]], [[OFF31]]($sp) 111 ; N64: addiu $sp, $sp, 64 112
