| /external/llvm/test/CodeGen/AMDGPU/ |
| sign_extend.ll | 15 ; SI: s_ashr_i32
39 ; SI: s_ashr_i32
|
| sext-in-reg.ll | 170 ; XSI: s_ashr_i32 {{v[0-9]+}}, [[EXTRACT]], 31
|
| /external/llvm/test/CodeGen/MIR/AMDGPU/ |
| target-index-operands.mir | 60 %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc
91 %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc
|
| expected-target-index-name.mir | 51 %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc
|
| invalid-target-index-operand.mir | 51 %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc
|
| /external/llvm/test/MC/AMDGPU/ |
| sop2.s | 100 // CHECK: s_ashr_i32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x91]
101 s_ashr_i32 s2, s4, s6 label
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIInstructions.td | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIInstructions.td | 304 defm S_ASHR_I32 : SOP2_32 <sop2<0x22, 0x20>, "s_ashr_i32",
[all...] |
| SIInstrInfo.cpp | [all...] |
