| /external/clang/test/CodeGen/ |
| arm64_vshift.c | 200 // CHECK: call <8 x i8> @llvm.aarch64.neon.sqshlu.v8i8(<8 x i8> %in, <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
206 // CHECK: call <4 x i16> @llvm.aarch64.neon.sqshlu.v4i16(<4 x i16> %in, <4 x i16> <i16 1, i16 1, i16 1, i16 1>)
212 // CHECK: call <2 x i32> @llvm.aarch64.neon.sqshlu.v2i32(<2 x i32> %in, <2 x i32> <i32 1, i32 1>)
218 // CHECK: call <1 x i64> @llvm.aarch64.neon.sqshlu.v1i64(<1 x i64> %in, <1 x i64> <i64 1>)
225 // CHECK: call <16 x i8> @llvm.aarch64.neon.sqshlu.v16i8(<16 x i8> %in, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
231 // CHECK: call <8 x i16> @llvm.aarch64.neon.sqshlu.v8i16(<8 x i16> %in, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
237 // CHECK: call <4 x i32> @llvm.aarch64.neon.sqshlu.v4i32(<4 x i32> %in, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
243 // CHECK: call <2 x i64> @llvm.aarch64.neon.sqshlu.v2i64(<2 x i64> %in, <2 x i64> <i64 1, i64 1>
|
| aarch64-neon-intrinsics.c | [all...] |
| /external/llvm/test/MC/AArch64/ |
| neon-scalar-shift-imm.s | 97 sqshlu b15, b18, #6
98 sqshlu h19, h17, #6
99 sqshlu s16, s14, #25
100 sqshlu d11, d13, #32
102 // CHECK: sqshlu b15, b18, #6 // encoding: [0x4f,0x66,0x0e,0x7f]
103 // CHECK: sqshlu h19, h17, #6 // encoding: [0x33,0x66,0x16,0x7f]
104 // CHECK: sqshlu s16, s14, #25 // encoding: [0xd0,0x65,0x39,0x7f]
105 // CHECK: sqshlu d11, d13, #32 // encoding: [0xab,0x65,0x60,0x7f]
|
| neon-simd-shift.s | 201 sqshlu v0.8b, v1.8b, #3
202 sqshlu v0.4h, v1.4h, #3
203 sqshlu v0.2s, v1.2s, #3
204 sqshlu v0.16b, v1.16b, #3
205 sqshlu v0.8h, v1.8h, #3
206 sqshlu v0.4s, v1.4s, #3
207 sqshlu v0.2d, v1.2d, #3
209 // CHECK: sqshlu v0.8b, v1.8b, #3 // encoding: [0x20,0x64,0x0b,0x2f]
210 // CHECK: sqshlu v0.4h, v1.4h, #3 // encoding: [0x20,0x64,0x13,0x2f]
211 // CHECK: sqshlu v0.2s, v1.2s, #3 // encoding: [0x20,0x64,0x23,0x2f
[all...] |
| arm64-advsimd.s | [all...] |
| neon-diagnostics.s | [all...] |
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-vshift.ll | 555 ;CHECK: sqshlu.8b v0, {{v[0-9]+}}, #1
557 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshlu.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
563 ;CHECK: sqshlu.4h v0, {{v[0-9]+}}, #1
565 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqshlu.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 1, i16 1, i16 1, i16 1>)
571 ;CHECK: sqshlu.2s v0, {{v[0-9]+}}, #1
573 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqshlu.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 1, i32 1>)
579 ;CHECK: sqshlu.16b v0, {{v[0-9]+}}, #1
581 %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqshlu.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
587 ;CHECK: sqshlu.8h v0, {{v[0-9]+}}, #1
589 %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqshlu.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
[all...] |
| /external/valgrind/none/tests/arm64/ |
| fp_and_simd.c | [all...] |
| /external/llvm/test/MC/Disassembler/AArch64/ |
| arm64-advsimd.txt | [all...] |
| neon-instructions.txt | 900 # CHECK: sqshlu v0.8b, v1.8b, #3
901 # CHECK: sqshlu v0.4h, v1.4h, #3
902 # CHECK: sqshlu v0.2s, v1.2s, #3
903 # CHECK: sqshlu v0.16b, v1.16b, #3
904 # CHECK: sqshlu v0.8h, v1.8h, #3
905 # CHECK: sqshlu v0.4s, v1.4s, #3
906 # CHECK: sqshlu v0.2d, v1.2d, #3
[all...] |
| /external/vixl/test/ |
| test-simulator-traces-a64.h | [all...] |
| test-disasm-a64.cc | [all...] |
| test-simulator-a64.cc | [all...] |
| /external/libjpeg-turbo/simd/ |
| jsimd_arm64_neon.S | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64SchedCyclone.td | 488 // SQSHL,SQSHLU,UQSHL are WriteV.
|
| AArch64SchedA57.td | 397 def : InstRW<[A57Write_4cyc_1X], (instregex "^SQSHLU")>;
[all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| aarch64-dis-2.c | [all...] |
| aarch64-tbl.h | [all...] |
| /external/vixl/doc/ |
| supported-instructions.md | [all...] |
| /external/vixl/src/vixl/a64/ |
| disasm-a64.cc | [all...] |
| macro-assembler-a64.h | [all...] |
| simulator-a64.h | [all...] |
| simulator-a64.cc | [all...] |
| /external/valgrind/VEX/priv/ |
| host_arm64_defs.c | [all...] |
| guest_arm64_toIR.c | [all...] |
