1 //=- AArch64SchedA57.td - ARM Cortex-A57 Scheduling Defs -----*- tablegen -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the machine model for ARM Cortex-A57 to support 11 // instruction scheduling and other instruction cost heuristics. 12 // 13 //===----------------------------------------------------------------------===// 14 15 //===----------------------------------------------------------------------===// 16 // The Cortex-A57 is a traditional superscaler microprocessor with a 17 // conservative 3-wide in-order stage for decode and dispatch. Combined with the 18 // much wider out-of-order issue stage, this produced a need to carefully 19 // schedule micro-ops so that all three decoded each cycle are successfully 20 // issued as the reservation station(s) simply don't stay occupied for long. 21 // Therefore, IssueWidth is set to the narrower of the two at three, while still 22 // modeling the machine as out-of-order. 23 24 def CortexA57Model : SchedMachineModel { 25 let IssueWidth = 3; // 3-way decode and dispatch 26 let MicroOpBufferSize = 128; // 128 micro-op re-order buffer 27 let LoadLatency = 4; // Optimistic load latency 28 let MispredictPenalty = 14; // Fetch + Decode/Rename/Dispatch + Branch 29 30 // Enable partial & runtime unrolling. The magic number is chosen based on 31 // experiments and benchmarking data. 32 let LoopMicroOpBufferSize = 16; 33 } 34 35 //===----------------------------------------------------------------------===// 36 // Define each kind of processor resource and number available on Cortex-A57. 37 // Cortex A-57 has 8 pipelines that each has its own 8-entry queue where 38 // micro-ops wait for their operands and then issue out-of-order. 39 40 def A57UnitB : ProcResource<1>; // Type B micro-ops 41 def A57UnitI : ProcResource<2>; // Type I micro-ops 42 def A57UnitM : ProcResource<1>; // Type M micro-ops 43 def A57UnitL : ProcResource<1>; // Type L micro-ops 44 def A57UnitS : ProcResource<1>; // Type S micro-ops 45 def A57UnitX : ProcResource<1>; // Type X micro-ops 46 def A57UnitW : ProcResource<1>; // Type W micro-ops 47 let SchedModel = CortexA57Model in { 48 def A57UnitV : ProcResGroup<[A57UnitX, A57UnitW]>; // Type V micro-ops 49 } 50 51 let SchedModel = CortexA57Model in { 52 53 //===----------------------------------------------------------------------===// 54 // Define customized scheduler read/write types specific to the Cortex-A57. 55 56 include "AArch64SchedA57WriteRes.td" 57 58 //===----------------------------------------------------------------------===// 59 // Map the target-defined scheduler read/write resources and latency for 60 // Cortex-A57. The Cortex-A57 types are directly associated with resources, so 61 // defining the aliases precludes the need for mapping them using WriteRes. The 62 // aliases are sufficient for creating a coarse, working model. As the model 63 // evolves, InstRWs will be used to override some of these SchedAliases. 64 // 65 // WARNING: Using SchedAliases is convenient and works well for latency and 66 // resource lookup for instructions. However, this creates an entry in 67 // AArch64WriteLatencyTable with a WriteResourceID of 0, breaking 68 // any SchedReadAdvance since the lookup will fail. 69 70 def : SchedAlias<WriteImm, A57Write_1cyc_1I>; 71 def : SchedAlias<WriteI, A57Write_1cyc_1I>; 72 def : SchedAlias<WriteISReg, A57Write_2cyc_1M>; 73 def : SchedAlias<WriteIEReg, A57Write_2cyc_1M>; 74 def : SchedAlias<WriteExtr, A57Write_1cyc_1I>; 75 def : SchedAlias<WriteIS, A57Write_1cyc_1I>; 76 def : SchedAlias<WriteID32, A57Write_19cyc_1M>; 77 def : SchedAlias<WriteID64, A57Write_35cyc_1M>; 78 def : WriteRes<WriteIM32, [A57UnitM]> { let Latency = 3; } 79 def : WriteRes<WriteIM64, [A57UnitM]> { let Latency = 5; } 80 def : SchedAlias<WriteBr, A57Write_1cyc_1B>; 81 def : SchedAlias<WriteBrReg, A57Write_1cyc_1B>; 82 def : SchedAlias<WriteLD, A57Write_4cyc_1L>; 83 def : SchedAlias<WriteST, A57Write_1cyc_1S>; 84 def : SchedAlias<WriteSTP, A57Write_1cyc_1S>; 85 def : SchedAlias<WriteAdr, A57Write_1cyc_1I>; 86 def : SchedAlias<WriteLDIdx, A57Write_4cyc_1I_1L>; 87 def : SchedAlias<WriteSTIdx, A57Write_1cyc_1I_1S>; 88 def : SchedAlias<WriteF, A57Write_3cyc_1V>; 89 def : SchedAlias<WriteFCmp, A57Write_3cyc_1V>; 90 def : SchedAlias<WriteFCvt, A57Write_5cyc_1V>; 91 def : SchedAlias<WriteFCopy, A57Write_5cyc_1L>; 92 def : SchedAlias<WriteFImm, A57Write_3cyc_1V>; 93 def : SchedAlias<WriteFMul, A57Write_5cyc_1V>; 94 def : SchedAlias<WriteFDiv, A57Write_18cyc_1X>; 95 def : SchedAlias<WriteV, A57Write_3cyc_1V>; 96 def : SchedAlias<WriteVLD, A57Write_5cyc_1L>; 97 def : SchedAlias<WriteVST, A57Write_1cyc_1S>; 98 99 def : WriteRes<WriteSys, []> { let Latency = 1; } 100 def : WriteRes<WriteBarrier, []> { let Latency = 1; } 101 def : WriteRes<WriteHint, []> { let Latency = 1; } 102 103 def : WriteRes<WriteLDHi, []> { let Latency = 4; } 104 105 // Forwarding logic is only modeled for multiply and accumulate 106 def : ReadAdvance<ReadI, 0>; 107 def : ReadAdvance<ReadISReg, 0>; 108 def : ReadAdvance<ReadIEReg, 0>; 109 def : ReadAdvance<ReadIM, 0>; 110 def : ReadAdvance<ReadIMA, 2, [WriteIM32, WriteIM64]>; 111 def : ReadAdvance<ReadID, 0>; 112 def : ReadAdvance<ReadExtrHi, 0>; 113 def : ReadAdvance<ReadAdrBase, 0>; 114 def : ReadAdvance<ReadVLD, 0>; 115 116 117 //===----------------------------------------------------------------------===// 118 // Specialize the coarse model by associating instruction groups with the 119 // subtarget-defined types. As the modeled is refined, this will override most 120 // of the above ShchedAlias mappings. 121 122 // Miscellaneous 123 // ----------------------------------------------------------------------------- 124 125 def : InstRW<[WriteI], (instrs COPY)>; 126 127 128 // Branch Instructions 129 // ----------------------------------------------------------------------------- 130 131 def : InstRW<[A57Write_1cyc_1B_1I], (instrs BL)>; 132 def : InstRW<[A57Write_2cyc_1B_1I], (instrs BLR)>; 133 134 135 // Shifted Register with Shift == 0 136 // ---------------------------------------------------------------------------- 137 138 def A57WriteISReg : SchedWriteVariant<[ 139 SchedVar<RegShiftedPred, [WriteISReg]>, 140 SchedVar<NoSchedPred, [WriteI]>]>; 141 def : InstRW<[A57WriteISReg], (instregex ".*rs$")>; 142 143 144 // Divide and Multiply Instructions 145 // ----------------------------------------------------------------------------- 146 147 // Multiply high 148 def : InstRW<[A57Write_6cyc_1M], (instrs SMULHrr, UMULHrr)>; 149 150 151 // Miscellaneous Data-Processing Instructions 152 // ----------------------------------------------------------------------------- 153 154 def : InstRW<[A57Write_1cyc_1I], (instrs EXTRWrri)>; 155 def : InstRW<[A57Write_3cyc_1I_1M], (instrs EXTRXrri)>; 156 def : InstRW<[A57Write_2cyc_1M], (instregex "BFM")>; 157 158 159 // Cryptography Extensions 160 // ----------------------------------------------------------------------------- 161 162 def : InstRW<[A57Write_3cyc_1W], (instregex "^AES")>; 163 def : InstRW<[A57Write_6cyc_2V], (instregex "^SHA1SU0")>; 164 def : InstRW<[A57Write_3cyc_1W], (instregex "^SHA1(H|SU1)")>; 165 def : InstRW<[A57Write_6cyc_2W], (instregex "^SHA1[CMP]")>; 166 def : InstRW<[A57Write_3cyc_1W], (instregex "^SHA256SU0")>; 167 def : InstRW<[A57Write_6cyc_2W], (instregex "^SHA256(H|H2|SU1)")>; 168 def : InstRW<[A57Write_3cyc_1W], (instregex "^CRC32")>; 169 170 171 // Vector Load 172 // ----------------------------------------------------------------------------- 173 174 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD1i(8|16|32)$")>; 175 def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1i(8|16|32)_POST$")>; 176 def : InstRW<[A57Write_5cyc_1L], (instregex "LD1i(64)$")>; 177 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1i(64)_POST$")>; 178 179 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD1Rv(8b|4h|2s)$")>; 180 def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1Rv(8b|4h|2s)_POST$")>; 181 def : InstRW<[A57Write_5cyc_1L], (instregex "LD1Rv(1d)$")>; 182 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1Rv(1d)_POST$")>; 183 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD1Rv(16b|8h|4s|2d)$")>; 184 def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>; 185 186 def : InstRW<[A57Write_5cyc_1L], (instregex "LD1Onev(8b|4h|2s|1d)$")>; 187 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1Onev(8b|4h|2s|1d)_POST$")>; 188 def : InstRW<[A57Write_5cyc_1L], (instregex "LD1Onev(16b|8h|4s|2d)$")>; 189 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1Onev(16b|8h|4s|2d)_POST$")>; 190 def : InstRW<[A57Write_5cyc_1L], (instregex "LD1Twov(8b|4h|2s|1d)$")>; 191 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1Twov(8b|4h|2s|1d)_POST$")>; 192 def : InstRW<[A57Write_6cyc_2L], (instregex "LD1Twov(16b|8h|4s|2d)$")>; 193 def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD1Twov(16b|8h|4s|2d)_POST$")>; 194 def : InstRW<[A57Write_6cyc_2L], (instregex "LD1Threev(8b|4h|2s|1d)$")>; 195 def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD1Threev(8b|4h|2s|1d)_POST$")>; 196 def : InstRW<[A57Write_7cyc_3L], (instregex "LD1Threev(16b|8h|4s|2d)$")>; 197 def : InstRW<[A57Write_7cyc_3L, WriteAdr], (instregex "LD1Threev(16b|8h|4s|2d)_POST$")>; 198 def : InstRW<[A57Write_6cyc_2L], (instregex "LD1Fourv(8b|4h|2s|1d)$")>; 199 def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD1Fourv(8b|4h|2s|1d)_POST$")>; 200 def : InstRW<[A57Write_8cyc_4L], (instregex "LD1Fourv(16b|8h|4s|2d)$")>; 201 def : InstRW<[A57Write_8cyc_4L, WriteAdr], (instregex "LD1Fourv(16b|8h|4s|2d)_POST$")>; 202 203 def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD2i(8|16)$")>; 204 def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD2i(8|16)_POST$")>; 205 def : InstRW<[A57Write_6cyc_2L], (instregex "LD2i(32)$")>; 206 def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD2i(32)_POST$")>; 207 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD2i(64)$")>; 208 def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD2i(64)_POST$")>; 209 210 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD2Rv(8b|4h|2s)$")>; 211 def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD2Rv(8b|4h|2s)_POST$")>; 212 def : InstRW<[A57Write_5cyc_1L], (instregex "LD2Rv(1d)$")>; 213 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD2Rv(1d)_POST$")>; 214 def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD2Rv(16b|8h|4s|2d)$")>; 215 def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>; 216 217 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD2Twov(8b|4h|2s)$")>; 218 def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD2Twov(8b|4h|2s)_POST$")>; 219 def : InstRW<[A57Write_9cyc_2L_2V], (instregex "LD2Twov(16b|8h|4s)$")>; 220 def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr], (instregex "LD2Twov(16b|8h|4s)_POST$")>; 221 def : InstRW<[A57Write_6cyc_2L], (instregex "LD2Twov(2d)$")>; 222 def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD2Twov(2d)_POST$")>; 223 224 def : InstRW<[A57Write_9cyc_1L_3V], (instregex "LD3i(8|16)$")>; 225 def : InstRW<[A57Write_9cyc_1L_3V, WriteAdr], (instregex "LD3i(8|16)_POST$")>; 226 def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD3i(32)$")>; 227 def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD3i(32)_POST$")>; 228 def : InstRW<[A57Write_6cyc_2L], (instregex "LD3i(64)$")>; 229 def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD3i(64)_POST$")>; 230 231 def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD3Rv(8b|4h|2s)$")>; 232 def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD3Rv(8b|4h|2s)_POST$")>; 233 def : InstRW<[A57Write_6cyc_2L], (instregex "LD3Rv(1d)$")>; 234 def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD3Rv(1d)_POST$")>; 235 def : InstRW<[A57Write_9cyc_1L_3V], (instregex "LD3Rv(16b|8h|4s)$")>; 236 def : InstRW<[A57Write_9cyc_1L_3V, WriteAdr], (instregex "LD3Rv(16b|8h|4s)_POST$")>; 237 def : InstRW<[A57Write_9cyc_2L_3V], (instregex "LD3Rv(2d)$")>; 238 def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD3Rv(2d)_POST$")>; 239 240 def : InstRW<[A57Write_9cyc_2L_2V], (instregex "LD3Threev(8b|4h|2s)$")>; 241 def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr], (instregex "LD3Threev(8b|4h|2s)_POST$")>; 242 def : InstRW<[A57Write_10cyc_3L_4V], (instregex "LD3Threev(16b|8h|4s)$")>; 243 def : InstRW<[A57Write_10cyc_3L_4V, WriteAdr], (instregex "LD3Threev(16b|8h|4s)_POST$")>; 244 def : InstRW<[A57Write_8cyc_4L], (instregex "LD3Threev(2d)$")>; 245 def : InstRW<[A57Write_8cyc_4L, WriteAdr], (instregex "LD3Threev(2d)_POST$")>; 246 247 def : InstRW<[A57Write_9cyc_2L_3V], (instregex "LD4i(8|16)$")>; 248 def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD4i(8|16)_POST$")>; 249 def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD4i(32)$")>; 250 def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD4i(32)_POST$")>; 251 def : InstRW<[A57Write_9cyc_2L_3V], (instregex "LD4i(64)$")>; 252 def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD4i(64)_POST$")>; 253 254 def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD4Rv(8b|4h|2s)$")>; 255 def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD4Rv(8b|4h|2s)_POST$")>; 256 def : InstRW<[A57Write_6cyc_2L], (instregex "LD4Rv(1d)$")>; 257 def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD4Rv(1d)_POST$")>; 258 def : InstRW<[A57Write_9cyc_2L_3V], (instregex "LD4Rv(16b|8h|4s)$")>; 259 def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD4Rv(16b|8h|4s)_POST$")>; 260 def : InstRW<[A57Write_9cyc_2L_4V], (instregex "LD4Rv(2d)$")>; 261 def : InstRW<[A57Write_9cyc_2L_4V, WriteAdr], (instregex "LD4Rv(2d)_POST$")>; 262 263 def : InstRW<[A57Write_9cyc_2L_2V], (instregex "LD4Fourv(8b|4h|2s)$")>; 264 def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr], (instregex "LD4Fourv(8b|4h|2s)_POST$")>; 265 def : InstRW<[A57Write_11cyc_4L_4V], (instregex "LD4Fourv(16b|8h|4s)$")>; 266 def : InstRW<[A57Write_11cyc_4L_4V, WriteAdr], (instregex "LD4Fourv(16b|8h|4s)_POST$")>; 267 def : InstRW<[A57Write_8cyc_4L], (instregex "LD4Fourv(2d)$")>; 268 def : InstRW<[A57Write_8cyc_4L, WriteAdr], (instregex "LD4Fourv(2d)_POST$")>; 269 270 // Vector Store 271 // ----------------------------------------------------------------------------- 272 273 def : InstRW<[A57Write_1cyc_1S], (instregex "ST1i(8|16|32)$")>; 274 def : InstRW<[A57Write_1cyc_1S, WriteAdr], (instregex "ST1i(8|16|32)_POST$")>; 275 def : InstRW<[A57Write_3cyc_1S_1V], (instregex "ST1i(64)$")>; 276 def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST1i(64)_POST$")>; 277 278 def : InstRW<[A57Write_1cyc_1S], (instregex "ST1Onev(8b|4h|2s|1d)$")>; 279 def : InstRW<[A57Write_1cyc_1S, WriteAdr], (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>; 280 def : InstRW<[A57Write_2cyc_2S], (instregex "ST1Onev(16b|8h|4s|2d)$")>; 281 def : InstRW<[A57Write_2cyc_2S, WriteAdr], (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>; 282 def : InstRW<[A57Write_2cyc_2S], (instregex "ST1Twov(8b|4h|2s|1d)$")>; 283 def : InstRW<[A57Write_2cyc_2S, WriteAdr], (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>; 284 def : InstRW<[A57Write_4cyc_4S], (instregex "ST1Twov(16b|8h|4s|2d)$")>; 285 def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>; 286 def : InstRW<[A57Write_3cyc_3S], (instregex "ST1Threev(8b|4h|2s|1d)$")>; 287 def : InstRW<[A57Write_3cyc_3S, WriteAdr], (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>; 288 def : InstRW<[A57Write_6cyc_6S], (instregex "ST1Threev(16b|8h|4s|2d)$")>; 289 def : InstRW<[A57Write_6cyc_6S, WriteAdr], (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>; 290 def : InstRW<[A57Write_4cyc_4S], (instregex "ST1Fourv(8b|4h|2s|1d)$")>; 291 def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>; 292 def : InstRW<[A57Write_8cyc_8S], (instregex "ST1Fourv(16b|8h|4s|2d)$")>; 293 def : InstRW<[A57Write_8cyc_8S, WriteAdr], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>; 294 295 def : InstRW<[A57Write_3cyc_1S_1V], (instregex "ST2i(8|16|32)$")>; 296 def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST2i(8|16|32)_POST$")>; 297 def : InstRW<[A57Write_2cyc_2S], (instregex "ST2i(64)$")>; 298 def : InstRW<[A57Write_2cyc_2S, WriteAdr], (instregex "ST2i(64)_POST$")>; 299 300 def : InstRW<[A57Write_3cyc_2S_1V], (instregex "ST2Twov(8b|4h|2s)$")>; 301 def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr], (instregex "ST2Twov(8b|4h|2s)_POST$")>; 302 def : InstRW<[A57Write_4cyc_4S_2V], (instregex "ST2Twov(16b|8h|4s)$")>; 303 def : InstRW<[A57Write_4cyc_4S_2V, WriteAdr], (instregex "ST2Twov(16b|8h|4s)_POST$")>; 304 def : InstRW<[A57Write_4cyc_4S], (instregex "ST2Twov(2d)$")>; 305 def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST2Twov(2d)_POST$")>; 306 307 def : InstRW<[A57Write_3cyc_1S_1V], (instregex "ST3i(8|16)$")>; 308 def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST3i(8|16)_POST$")>; 309 def : InstRW<[A57Write_3cyc_3S], (instregex "ST3i(32)$")>; 310 def : InstRW<[A57Write_3cyc_3S, WriteAdr], (instregex "ST3i(32)_POST$")>; 311 def : InstRW<[A57Write_3cyc_2S_1V], (instregex "ST3i(64)$")>; 312 def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr], (instregex "ST3i(64)_POST$")>; 313 314 def : InstRW<[A57Write_3cyc_3S_2V], (instregex "ST3Threev(8b|4h|2s)$")>; 315 def : InstRW<[A57Write_3cyc_3S_2V, WriteAdr], (instregex "ST3Threev(8b|4h|2s)_POST$")>; 316 def : InstRW<[A57Write_6cyc_6S_4V], (instregex "ST3Threev(16b|8h|4s)$")>; 317 def : InstRW<[A57Write_6cyc_6S_4V, WriteAdr], (instregex "ST3Threev(16b|8h|4s)_POST$")>; 318 def : InstRW<[A57Write_6cyc_6S], (instregex "ST3Threev(2d)$")>; 319 def : InstRW<[A57Write_6cyc_6S, WriteAdr], (instregex "ST3Threev(2d)_POST$")>; 320 321 def : InstRW<[A57Write_3cyc_1S_1V], (instregex "ST4i(8|16)$")>; 322 def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST4i(8|16)_POST$")>; 323 def : InstRW<[A57Write_4cyc_4S], (instregex "ST4i(32)$")>; 324 def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST4i(32)_POST$")>; 325 def : InstRW<[A57Write_3cyc_2S_1V], (instregex "ST4i(64)$")>; 326 def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr], (instregex "ST4i(64)_POST$")>; 327 328 def : InstRW<[A57Write_4cyc_4S_2V], (instregex "ST4Fourv(8b|4h|2s)$")>; 329 def : InstRW<[A57Write_4cyc_4S_2V, WriteAdr], (instregex "ST4Fourv(8b|4h|2s)_POST$")>; 330 def : InstRW<[A57Write_8cyc_8S_4V], (instregex "ST4Fourv(16b|8h|4s)$")>; 331 def : InstRW<[A57Write_8cyc_8S_4V, WriteAdr], (instregex "ST4Fourv(16b|8h|4s)_POST$")>; 332 def : InstRW<[A57Write_8cyc_8S], (instregex "ST4Fourv(2d)$")>; 333 def : InstRW<[A57Write_8cyc_8S, WriteAdr], (instregex "ST4Fourv(2d)_POST$")>; 334 335 // Vector - Integer 336 // ----------------------------------------------------------------------------- 337 338 // Reference for forms in this group 339 // D form - v8i8, v4i16, v2i32 340 // Q form - v16i8, v8i16, v4i32 341 // D form - v1i8, v1i16, v1i32, v1i64 342 // Q form - v16i8, v8i16, v4i32, v2i64 343 // D form - v8i8_v8i16, v4i16_v4i32, v2i32_v2i64 344 // Q form - v16i8_v8i16, v8i16_v4i32, v4i32_v2i64 345 346 // ASIMD absolute diff accum, D-form 347 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]ABA(v8i8|v4i16|v2i32)$")>; 348 // ASIMD absolute diff accum, Q-form 349 def : InstRW<[A57Write_5cyc_2X], (instregex "^[SU]ABA(v16i8|v8i16|v4i32)$")>; 350 // ASIMD absolute diff accum long 351 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]ABAL")>; 352 353 // ASIMD arith, reduce, 4H/4S 354 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]?ADDL?V(v8i8|v4i16|v2i32)v$")>; 355 // ASIMD arith, reduce, 8B/8H 356 def : InstRW<[A57Write_7cyc_1V_1X], (instregex "^[SU]?ADDL?V(v8i16|v4i32)v$")>; 357 // ASIMD arith, reduce, 16B 358 def : InstRW<[A57Write_8cyc_2X], (instregex "^[SU]?ADDL?Vv16i8v$")>; 359 360 // ASIMD max/min, reduce, 4H/4S 361 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU](MIN|MAX)V(v4i16|v4i32)v$")>; 362 // ASIMD max/min, reduce, 8B/8H 363 def : InstRW<[A57Write_7cyc_1V_1X], (instregex "^[SU](MIN|MAX)V(v8i8|v8i16)v$")>; 364 // ASIMD max/min, reduce, 16B 365 def : InstRW<[A57Write_8cyc_2X], (instregex "^[SU](MIN|MAX)Vv16i8v$")>; 366 367 // ASIMD multiply, D-form 368 def : InstRW<[A57Write_5cyc_1W], (instregex "^(P?MUL|SQR?DMULH)(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)(_indexed)?$")>; 369 // ASIMD multiply, Q-form 370 def : InstRW<[A57Write_6cyc_2W], (instregex "^(P?MUL|SQR?DMULH)(v16i8|v8i16|v4i32)(_indexed)?$")>; 371 372 // ASIMD multiply accumulate, D-form 373 def : InstRW<[A57Write_5cyc_1W], (instregex "^ML[AS](v8i8|v4i16|v2i32)(_indexed)?$")>; 374 // ASIMD multiply accumulate, Q-form 375 def : InstRW<[A57Write_6cyc_2W], (instregex "^ML[AS](v16i8|v8i16|v4i32)(_indexed)?$")>; 376 377 // ASIMD multiply accumulate long 378 // ASIMD multiply accumulate saturating long 379 def A57WriteIVMA : SchedWriteRes<[A57UnitW]> { let Latency = 5; } 380 def A57ReadIVMA4 : SchedReadAdvance<4, [A57WriteIVMA]>; 381 def : InstRW<[A57WriteIVMA, A57ReadIVMA4], (instregex "^(S|U|SQD)ML[AS]L")>; 382 383 // ASIMD multiply long 384 def : InstRW<[A57Write_5cyc_1W], (instregex "^(S|U|SQD)MULL")>; 385 def : InstRW<[A57Write_5cyc_1W], (instregex "^PMULL(v8i8|v16i8)")>; 386 def : InstRW<[A57Write_3cyc_1W], (instregex "^PMULL(v1i64|v2i64)")>; 387 388 // ASIMD pairwise add and accumulate 389 // ASIMD shift accumulate 390 def A57WriteIVA : SchedWriteRes<[A57UnitX]> { let Latency = 4; } 391 def A57ReadIVA3 : SchedReadAdvance<3, [A57WriteIVA]>; 392 def : InstRW<[A57WriteIVA, A57ReadIVA3], (instregex "^[SU]ADALP")>; 393 def : InstRW<[A57WriteIVA, A57ReadIVA3], (instregex "^(S|SR|U|UR)SRA")>; 394 395 // ASIMD shift by immed, complex 396 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]?(Q|R){1,2}SHR")>; 397 def : InstRW<[A57Write_4cyc_1X], (instregex "^SQSHLU")>; 398 399 400 // ASIMD shift by register, basic, Q-form 401 def : InstRW<[A57Write_4cyc_2X], (instregex "^[SU]SHL(v16i8|v8i16|v4i32|v2i64)")>; 402 403 // ASIMD shift by register, complex, D-form 404 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32|b|d|h|s)")>; 405 406 // ASIMD shift by register, complex, Q-form 407 def : InstRW<[A57Write_5cyc_2X], (instregex "^[SU][QR]{1,2}SHL(v16i8|v8i16|v4i32|v2i64)")>; 408 409 410 // Vector - Floating Point 411 // ----------------------------------------------------------------------------- 412 413 // Reference for forms in this group 414 // D form - v2f32 415 // Q form - v4f32, v2f64 416 // D form - 32, 64 417 // D form - v1i32, v1i64 418 // D form - v2i32 419 // Q form - v4i32, v2i64 420 421 // ASIMD FP arith, normal, D-form 422 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FABD|FADD|FSUB)(v2f32|32|64|v2i32p)")>; 423 // ASIMD FP arith, normal, Q-form 424 def : InstRW<[A57Write_5cyc_2V], (instregex "^(FABD|FADD|FSUB)(v4f32|v2f64|v2i64p)")>; 425 426 // ASIMD FP arith, pairwise, D-form 427 def : InstRW<[A57Write_5cyc_1V], (instregex "^FADDP(v2f32|32|64|v2i32)")>; 428 // ASIMD FP arith, pairwise, Q-form 429 def : InstRW<[A57Write_9cyc_3V], (instregex "^FADDP(v4f32|v2f64|v2i64)")>; 430 431 // ASIMD FP compare, D-form 432 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FACGE|FACGT|FCMEQ|FCMGE|FCMGT|FCMLE|FCMLT)(v2f32|32|64|v1i32|v2i32|v1i64)")>; 433 // ASIMD FP compare, Q-form 434 def : InstRW<[A57Write_5cyc_2V], (instregex "^(FACGE|FACGT|FCMEQ|FCMGE|FCMGT|FCMLE|FCMLT)(v4f32|v2f64|v4i32|v2i64)")>; 435 436 // ASIMD FP convert, long and narrow 437 def : InstRW<[A57Write_8cyc_3V], (instregex "^FCVT(L|N|XN)v")>; 438 // ASIMD FP convert, other, D-form 439 def : InstRW<[A57Write_5cyc_1V], (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v2f32|v1i32|v2i32|v1i64)")>; 440 // ASIMD FP convert, other, Q-form 441 def : InstRW<[A57Write_5cyc_2V], (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v4f32|v2f64|v4i32|v2i64)")>; 442 443 // ASIMD FP divide, D-form, F32 444 def : InstRW<[A57Write_18cyc_1X], (instregex "FDIVv2f32")>; 445 // ASIMD FP divide, Q-form, F32 446 def : InstRW<[A57Write_36cyc_2X], (instregex "FDIVv4f32")>; 447 // ASIMD FP divide, Q-form, F64 448 def : InstRW<[A57Write_64cyc_2X], (instregex "FDIVv2f64")>; 449 450 // Note: These were simply duplicated from ASIMD FDIV because of missing documentation 451 // ASIMD FP square root, D-form, F32 452 def : InstRW<[A57Write_18cyc_1X], (instregex "FSQRTv2f32")>; 453 // ASIMD FP square root, Q-form, F32 454 def : InstRW<[A57Write_36cyc_2X], (instregex "FSQRTv4f32")>; 455 // ASIMD FP square root, Q-form, F64 456 def : InstRW<[A57Write_64cyc_2X], (instregex "FSQRTv2f64")>; 457 458 // ASIMD FP max/min, normal, D-form 459 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FMAX|FMIN)(NM)?(v2f32)")>; 460 // ASIMD FP max/min, normal, Q-form 461 def : InstRW<[A57Write_5cyc_2V], (instregex "^(FMAX|FMIN)(NM)?(v4f32|v2f64)")>; 462 // ASIMD FP max/min, pairwise, D-form 463 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FMAX|FMIN)(NM)?P(v2f32|v2i32)")>; 464 // ASIMD FP max/min, pairwise, Q-form 465 def : InstRW<[A57Write_9cyc_3V], (instregex "^(FMAX|FMIN)(NM)?P(v4f32|v2f64|v2i64)")>; 466 // ASIMD FP max/min, reduce 467 def : InstRW<[A57Write_10cyc_3V], (instregex "^(FMAX|FMIN)(NM)?Vv")>; 468 469 // ASIMD FP multiply, D-form, FZ 470 def : InstRW<[A57Write_5cyc_1V], (instregex "^FMULX?(v2f32|v1i32|v2i32|v1i64|32|64)")>; 471 // ASIMD FP multiply, Q-form, FZ 472 def : InstRW<[A57Write_5cyc_2V], (instregex "^FMULX?(v4f32|v2f64|v4i32|v2i64)")>; 473 474 // ASIMD FP multiply accumulate, D-form, FZ 475 // ASIMD FP multiply accumulate, Q-form, FZ 476 def A57WriteFPVMAD : SchedWriteRes<[A57UnitV]> { let Latency = 9; } 477 def A57WriteFPVMAQ : SchedWriteRes<[A57UnitV, A57UnitV]> { let Latency = 10; } 478 def A57ReadFPVMA5 : SchedReadAdvance<5, [A57WriteFPVMAD, A57WriteFPVMAQ]>; 479 def : InstRW<[A57WriteFPVMAD, A57ReadFPVMA5], (instregex "^FML[AS](v2f32|v1i32|v2i32|v1i64)")>; 480 def : InstRW<[A57WriteFPVMAQ, A57ReadFPVMA5], (instregex "^FML[AS](v4f32|v2f64|v4i32|v2i64)")>; 481 482 // ASIMD FP round, D-form 483 def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT[AIMNPXZ](v2f32)")>; 484 // ASIMD FP round, Q-form 485 def : InstRW<[A57Write_5cyc_2V], (instregex "^FRINT[AIMNPXZ](v4f32|v2f64)")>; 486 487 488 // Vector - Miscellaneous 489 // ----------------------------------------------------------------------------- 490 491 // Reference for forms in this group 492 // D form - v8i8, v4i16, v2i32 493 // Q form - v16i8, v8i16, v4i32 494 // D form - v1i8, v1i16, v1i32, v1i64 495 // Q form - v16i8, v8i16, v4i32, v2i64 496 497 // ASIMD bitwise insert, Q-form 498 def : InstRW<[A57Write_3cyc_2V], (instregex "^(BIF|BIT|BSL)v16i8")>; 499 500 // ASIMD duplicate, gen reg, D-form and Q-form 501 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^CPY")>; 502 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^DUPv.+gpr")>; 503 504 // ASIMD move, saturating 505 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]QXTU?N")>; 506 507 // ASIMD reciprocal estimate, D-form 508 def : InstRW<[A57Write_5cyc_1V], (instregex "^[FU](RECP|RSQRT)(E|X)(v2f32|v1i32|v2i32|v1i64)")>; 509 // ASIMD reciprocal estimate, Q-form 510 def : InstRW<[A57Write_5cyc_2V], (instregex "^[FU](RECP|RSQRT)(E|X)(v2f64|v4f32|v4i32)")>; 511 512 // ASIMD reciprocal step, D-form, FZ 513 def : InstRW<[A57Write_9cyc_1V], (instregex "^F(RECP|RSQRT)S(v2f32|v1i32|v2i32|v1i64|32|64)")>; 514 // ASIMD reciprocal step, Q-form, FZ 515 def : InstRW<[A57Write_9cyc_2V], (instregex "^F(RECP|RSQRT)S(v2f64|v4f32|v4i32)")>; 516 517 // ASIMD table lookup, D-form 518 def : InstRW<[A57Write_3cyc_1V], (instregex "^TB[LX]v8i8One")>; 519 def : InstRW<[A57Write_6cyc_2V], (instregex "^TB[LX]v8i8Two")>; 520 def : InstRW<[A57Write_9cyc_3V], (instregex "^TB[LX]v8i8Three")>; 521 def : InstRW<[A57Write_12cyc_4V], (instregex "^TB[LX]v8i8Four")>; 522 // ASIMD table lookup, Q-form 523 def : InstRW<[A57Write_6cyc_3V], (instregex "^TB[LX]v16i8One")>; 524 def : InstRW<[A57Write_9cyc_5V], (instregex "^TB[LX]v16i8Two")>; 525 def : InstRW<[A57Write_12cyc_7V], (instregex "^TB[LX]v16i8Three")>; 526 def : InstRW<[A57Write_15cyc_9V], (instregex "^TB[LX]v16i8Four")>; 527 528 // ASIMD transfer, element to gen reg 529 def : InstRW<[A57Write_6cyc_1I_1L], (instregex "^[SU]MOVv")>; 530 531 // ASIMD transfer, gen reg to element 532 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^INSv")>; 533 534 // ASIMD unzip/zip, Q-form 535 def : InstRW<[A57Write_6cyc_3V], (instregex "^(UZP|ZIP)(1|2)(v16i8|v8i16|v4i32|v2i64)")>; 536 537 538 // Remainder 539 // ----------------------------------------------------------------------------- 540 541 def : InstRW<[A57Write_5cyc_1V], (instregex "^F(ADD|SUB)[DS]rr")>; 542 543 def A57WriteFPMA : SchedWriteRes<[A57UnitV]> { let Latency = 9; } 544 def A57ReadFPMA5 : SchedReadAdvance<5, [A57WriteFPMA]>; 545 def A57ReadFPM : SchedReadAdvance<0>; 546 def : InstRW<[A57WriteFPMA, A57ReadFPM, A57ReadFPM, A57ReadFPMA5], (instregex "^FN?M(ADD|SUB)[DS]rrr")>; 547 548 def : InstRW<[A57Write_10cyc_1L_1V], (instregex "^[FSU]CVT[AMNPZ][SU](_Int)?[SU]?[XW]?[DS]?[rds]i?")>; 549 def : InstRW<[A57Write_10cyc_1L_1V], (instregex "^[SU]CVTF")>; 550 551 def : InstRW<[A57Write_32cyc_1X], (instrs FDIVDrr)>; 552 def : InstRW<[A57Write_18cyc_1X], (instrs FDIVSrr)>; 553 554 def : InstRW<[A57Write_5cyc_1V], (instregex "^F(MAX|MIN).+rr")>; 555 556 def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT.+r")>; 557 558 def : InstRW<[A57Write_32cyc_1X], (instrs FSQRTDr)>; 559 def : InstRW<[A57Write_18cyc_1X], (instrs FSQRTSr)>; 560 561 def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDNPDi)>; 562 def : InstRW<[A57Write_6cyc_2L, WriteLDHi], (instrs LDNPQi)>; 563 def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDNPSi)>; 564 def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDPDi)>; 565 def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPDpost)>; 566 def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPDpre)>; 567 def : InstRW<[A57Write_6cyc_2L, WriteLDHi], (instrs LDPQi)>; 568 def : InstRW<[A57Write_6cyc_2L, WriteLDHi, WriteAdr], (instrs LDPQpost)>; 569 def : InstRW<[A57Write_6cyc_2L, WriteLDHi, WriteAdr], (instrs LDPQpre)>; 570 def : InstRW<[A57Write_5cyc_1I_2L, WriteLDHi], (instrs LDPSWi)>; 571 def : InstRW<[A57Write_5cyc_1I_2L, WriteLDHi, WriteAdr], (instrs LDPSWpost)>; 572 def : InstRW<[A57Write_5cyc_1I_2L, WriteLDHi, WriteAdr], (instrs LDPSWpre)>; 573 def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDPSi)>; 574 def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPSpost)>; 575 def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPSpre)>; 576 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRBpost)>; 577 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRBpre)>; 578 def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRBroW)>; 579 def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRBroX)>; 580 def : InstRW<[A57Write_5cyc_1L], (instrs LDRBui)>; 581 def : InstRW<[A57Write_5cyc_1L], (instrs LDRDl)>; 582 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRDpost)>; 583 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRDpre)>; 584 def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRDroW)>; 585 def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRDroX)>; 586 def : InstRW<[A57Write_5cyc_1L], (instrs LDRDui)>; 587 def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRHHroW)>; 588 def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRHHroX)>; 589 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRHpost)>; 590 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRHpre)>; 591 def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRHroW)>; 592 def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRHroX)>; 593 def : InstRW<[A57Write_5cyc_1L], (instrs LDRHui)>; 594 def : InstRW<[A57Write_5cyc_1L], (instrs LDRQl)>; 595 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRQpost)>; 596 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRQpre)>; 597 def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRQroW)>; 598 def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRQroX)>; 599 def : InstRW<[A57Write_5cyc_1L], (instrs LDRQui)>; 600 def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHWroW)>; 601 def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHWroX)>; 602 def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHXroW)>; 603 def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHXroX)>; 604 def : InstRW<[A57Write_5cyc_1L], (instrs LDRSl)>; 605 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRSpost)>; 606 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRSpre)>; 607 def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRSroW)>; 608 def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRSroX)>; 609 def : InstRW<[A57Write_5cyc_1L], (instrs LDRSui)>; 610 def : InstRW<[A57Write_5cyc_1L], (instrs LDURBi)>; 611 def : InstRW<[A57Write_5cyc_1L], (instrs LDURDi)>; 612 def : InstRW<[A57Write_5cyc_1L], (instrs LDURHi)>; 613 def : InstRW<[A57Write_5cyc_1L], (instrs LDURQi)>; 614 def : InstRW<[A57Write_5cyc_1L], (instrs LDURSi)>; 615 616 def : InstRW<[A57Write_2cyc_2S], (instrs STNPDi)>; 617 def : InstRW<[A57Write_4cyc_1I_4S], (instrs STNPQi)>; 618 def : InstRW<[A57Write_2cyc_2S], (instrs STNPXi)>; 619 def : InstRW<[A57Write_2cyc_2S], (instrs STPDi)>; 620 def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPDpost)>; 621 def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPDpre)>; 622 def : InstRW<[A57Write_4cyc_1I_4S], (instrs STPQi)>; 623 def : InstRW<[WriteAdr, A57Write_4cyc_1I_4S], (instrs STPQpost)>; 624 def : InstRW<[WriteAdr, A57Write_4cyc_2I_4S], (instrs STPQpre)>; 625 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPSpost)>; 626 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPSpre)>; 627 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPWpost)>; 628 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPWpre)>; 629 def : InstRW<[A57Write_2cyc_2S], (instrs STPXi)>; 630 def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPXpost)>; 631 def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPXpre)>; 632 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRBBpost)>; 633 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRBBpre)>; 634 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRBpost)>; 635 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRBpre)>; 636 def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRBroW)>; 637 def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRBroX)>; 638 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRDpost)>; 639 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRDpre)>; 640 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRHHpost)>; 641 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRHHpre)>; 642 def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHHroW)>; 643 def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHHroX)>; 644 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRHpost)>; 645 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRHpre)>; 646 def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHroW)>; 647 def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHroX)>; 648 def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S, ReadAdrBase], (instrs STRQpost)>; 649 def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STRQpre)>; 650 def : InstRW<[A57Write_2cyc_1I_2S, ReadAdrBase], (instrs STRQroW)>; 651 def : InstRW<[A57Write_2cyc_1I_2S, ReadAdrBase], (instrs STRQroX)>; 652 def : InstRW<[A57Write_2cyc_1I_2S], (instrs STRQui)>; 653 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRSpost)>; 654 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRSpre)>; 655 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRWpost)>; 656 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRWpre)>; 657 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRXpost)>; 658 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRXpre)>; 659 def : InstRW<[A57Write_2cyc_2S], (instrs STURQi)>; 660 661 } // SchedModel = CortexA57Model 662
