1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef VIRTGPU_DRM_H 20 #define VIRTGPU_DRM_H 21 #include <stddef.h> 22 #include "drm/drm.h" 23 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24 #define DRM_VIRTGPU_MAP 0x01 25 #define DRM_VIRTGPU_EXECBUFFER 0x02 26 #define DRM_VIRTGPU_GETPARAM 0x03 27 #define DRM_VIRTGPU_RESOURCE_CREATE 0x04 28 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29 #define DRM_VIRTGPU_RESOURCE_INFO 0x05 30 #define DRM_VIRTGPU_TRANSFER_FROM_HOST 0x06 31 #define DRM_VIRTGPU_TRANSFER_TO_HOST 0x07 32 #define DRM_VIRTGPU_WAIT 0x08 33 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34 #define DRM_VIRTGPU_GET_CAPS 0x09 35 struct drm_virtgpu_map { 36 uint64_t offset; 37 uint32_t handle; 38 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39 uint32_t pad; 40 }; 41 struct drm_virtgpu_execbuffer { 42 uint32_t flags; 43 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44 uint32_t size; 45 uint64_t command; 46 uint64_t bo_handles; 47 uint32_t num_bo_handles; 48 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49 uint32_t pad; 50 }; 51 #define VIRTGPU_PARAM_3D_FEATURES 1 52 struct drm_virtgpu_getparam { 53 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54 uint64_t param; 55 uint64_t value; 56 }; 57 struct drm_virtgpu_resource_create { 58 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59 uint32_t target; 60 uint32_t format; 61 uint32_t bind; 62 uint32_t width; 63 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64 uint32_t height; 65 uint32_t depth; 66 uint32_t array_size; 67 uint32_t last_level; 68 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69 uint32_t nr_samples; 70 uint32_t flags; 71 uint32_t bo_handle; 72 uint32_t res_handle; 73 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74 uint32_t size; 75 uint32_t stride; 76 }; 77 struct drm_virtgpu_resource_info { 78 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79 uint32_t bo_handle; 80 uint32_t res_handle; 81 uint32_t size; 82 uint32_t stride; 83 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84 }; 85 struct drm_virtgpu_3d_box { 86 uint32_t x; 87 uint32_t y; 88 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89 uint32_t z; 90 uint32_t w; 91 uint32_t h; 92 uint32_t d; 93 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94 }; 95 struct drm_virtgpu_3d_transfer_to_host { 96 uint32_t bo_handle; 97 struct drm_virtgpu_3d_box box; 98 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99 uint32_t level; 100 uint32_t offset; 101 }; 102 struct drm_virtgpu_3d_transfer_from_host { 103 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104 uint32_t bo_handle; 105 struct drm_virtgpu_3d_box box; 106 uint32_t level; 107 uint32_t offset; 108 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109 }; 110 #define VIRTGPU_WAIT_NOWAIT 1 111 struct drm_virtgpu_3d_wait { 112 uint32_t handle; 113 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114 uint32_t flags; 115 }; 116 struct drm_virtgpu_get_caps { 117 uint32_t cap_set_id; 118 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119 uint32_t cap_set_ver; 120 uint64_t addr; 121 uint32_t size; 122 uint32_t pad; 123 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124 }; 125 #define DRM_IOCTL_VIRTGPU_MAP DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map) 126 #define DRM_IOCTL_VIRTGPU_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER, struct drm_virtgpu_execbuffer) 127 #define DRM_IOCTL_VIRTGPU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GETPARAM, struct drm_virtgpu_getparam) 128 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129 #define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE, struct drm_virtgpu_resource_create) 130 #define DRM_IOCTL_VIRTGPU_RESOURCE_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_INFO, struct drm_virtgpu_resource_info) 131 #define DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_FROM_HOST, struct drm_virtgpu_3d_transfer_from_host) 132 #define DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_TO_HOST, struct drm_virtgpu_3d_transfer_to_host) 133 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134 #define DRM_IOCTL_VIRTGPU_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_WAIT, struct drm_virtgpu_3d_wait) 135 #define DRM_IOCTL_VIRTGPU_GET_CAPS DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GET_CAPS, struct drm_virtgpu_get_caps) 136 #endif 137
