1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef VIRTIO_GPU_HW_H 20 #define VIRTIO_GPU_HW_H 21 #include <linux/types.h> 22 #define VIRTIO_GPU_F_VIRGL 0 23 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24 enum virtio_gpu_ctrl_type { 25 VIRTIO_GPU_UNDEFINED = 0, 26 VIRTIO_GPU_CMD_GET_DISPLAY_INFO = 0x0100, 27 VIRTIO_GPU_CMD_RESOURCE_CREATE_2D, 28 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29 VIRTIO_GPU_CMD_RESOURCE_UNREF, 30 VIRTIO_GPU_CMD_SET_SCANOUT, 31 VIRTIO_GPU_CMD_RESOURCE_FLUSH, 32 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D, 33 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34 VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING, 35 VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING, 36 VIRTIO_GPU_CMD_GET_CAPSET_INFO, 37 VIRTIO_GPU_CMD_GET_CAPSET, 38 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39 VIRTIO_GPU_CMD_CTX_CREATE = 0x0200, 40 VIRTIO_GPU_CMD_CTX_DESTROY, 41 VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE, 42 VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE, 43 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44 VIRTIO_GPU_CMD_RESOURCE_CREATE_3D, 45 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D, 46 VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D, 47 VIRTIO_GPU_CMD_SUBMIT_3D, 48 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49 VIRTIO_GPU_CMD_UPDATE_CURSOR = 0x0300, 50 VIRTIO_GPU_CMD_MOVE_CURSOR, 51 VIRTIO_GPU_RESP_OK_NODATA = 0x1100, 52 VIRTIO_GPU_RESP_OK_DISPLAY_INFO, 53 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54 VIRTIO_GPU_RESP_OK_CAPSET_INFO, 55 VIRTIO_GPU_RESP_OK_CAPSET, 56 VIRTIO_GPU_RESP_ERR_UNSPEC = 0x1200, 57 VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY, 58 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59 VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID, 60 VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID, 61 VIRTIO_GPU_RESP_ERR_INVALID_CONTEXT_ID, 62 VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER, 63 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64 }; 65 #define VIRTIO_GPU_FLAG_FENCE (1 << 0) 66 struct virtio_gpu_ctrl_hdr { 67 __le32 type; 68 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69 __le32 flags; 70 __le64 fence_id; 71 __le32 ctx_id; 72 __le32 padding; 73 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74 }; 75 struct virtio_gpu_cursor_pos { 76 __le32 scanout_id; 77 __le32 x; 78 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79 __le32 y; 80 __le32 padding; 81 }; 82 struct virtio_gpu_update_cursor { 83 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84 struct virtio_gpu_ctrl_hdr hdr; 85 struct virtio_gpu_cursor_pos pos; 86 __le32 resource_id; 87 __le32 hot_x; 88 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89 __le32 hot_y; 90 __le32 padding; 91 }; 92 struct virtio_gpu_rect { 93 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94 __le32 x; 95 __le32 y; 96 __le32 width; 97 __le32 height; 98 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99 }; 100 struct virtio_gpu_resource_unref { 101 struct virtio_gpu_ctrl_hdr hdr; 102 __le32 resource_id; 103 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104 __le32 padding; 105 }; 106 struct virtio_gpu_resource_create_2d { 107 struct virtio_gpu_ctrl_hdr hdr; 108 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109 __le32 resource_id; 110 __le32 format; 111 __le32 width; 112 __le32 height; 113 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114 }; 115 struct virtio_gpu_set_scanout { 116 struct virtio_gpu_ctrl_hdr hdr; 117 struct virtio_gpu_rect r; 118 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119 __le32 scanout_id; 120 __le32 resource_id; 121 }; 122 struct virtio_gpu_resource_flush { 123 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124 struct virtio_gpu_ctrl_hdr hdr; 125 struct virtio_gpu_rect r; 126 __le32 resource_id; 127 __le32 padding; 128 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129 }; 130 struct virtio_gpu_transfer_to_host_2d { 131 struct virtio_gpu_ctrl_hdr hdr; 132 struct virtio_gpu_rect r; 133 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134 __le64 offset; 135 __le32 resource_id; 136 __le32 padding; 137 }; 138 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139 struct virtio_gpu_mem_entry { 140 __le64 addr; 141 __le32 length; 142 __le32 padding; 143 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144 }; 145 struct virtio_gpu_resource_attach_backing { 146 struct virtio_gpu_ctrl_hdr hdr; 147 __le32 resource_id; 148 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 149 __le32 nr_entries; 150 }; 151 struct virtio_gpu_resource_detach_backing { 152 struct virtio_gpu_ctrl_hdr hdr; 153 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 154 __le32 resource_id; 155 __le32 padding; 156 }; 157 #define VIRTIO_GPU_MAX_SCANOUTS 16 158 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 159 struct virtio_gpu_resp_display_info { 160 struct virtio_gpu_ctrl_hdr hdr; 161 struct virtio_gpu_display_one { 162 struct virtio_gpu_rect r; 163 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 164 __le32 enabled; 165 __le32 flags; 166 } pmodes[VIRTIO_GPU_MAX_SCANOUTS]; 167 }; 168 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 169 struct virtio_gpu_box { 170 __le32 x, y, z; 171 __le32 w, h, d; 172 }; 173 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 174 struct virtio_gpu_transfer_host_3d { 175 struct virtio_gpu_ctrl_hdr hdr; 176 struct virtio_gpu_box box; 177 __le64 offset; 178 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 179 __le32 resource_id; 180 __le32 level; 181 __le32 stride; 182 __le32 layer_stride; 183 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 184 }; 185 #define VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP (1 << 0) 186 struct virtio_gpu_resource_create_3d { 187 struct virtio_gpu_ctrl_hdr hdr; 188 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 189 __le32 resource_id; 190 __le32 target; 191 __le32 format; 192 __le32 bind; 193 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 194 __le32 width; 195 __le32 height; 196 __le32 depth; 197 __le32 array_size; 198 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 199 __le32 last_level; 200 __le32 nr_samples; 201 __le32 flags; 202 __le32 padding; 203 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 204 }; 205 struct virtio_gpu_ctx_create { 206 struct virtio_gpu_ctrl_hdr hdr; 207 __le32 nlen; 208 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 209 __le32 padding; 210 char debug_name[64]; 211 }; 212 struct virtio_gpu_ctx_destroy { 213 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 214 struct virtio_gpu_ctrl_hdr hdr; 215 }; 216 struct virtio_gpu_ctx_resource { 217 struct virtio_gpu_ctrl_hdr hdr; 218 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 219 __le32 resource_id; 220 __le32 padding; 221 }; 222 struct virtio_gpu_cmd_submit { 223 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 224 struct virtio_gpu_ctrl_hdr hdr; 225 __le32 size; 226 __le32 padding; 227 }; 228 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 229 #define VIRTIO_GPU_CAPSET_VIRGL 1 230 struct virtio_gpu_get_capset_info { 231 struct virtio_gpu_ctrl_hdr hdr; 232 __le32 capset_index; 233 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 234 __le32 padding; 235 }; 236 struct virtio_gpu_resp_capset_info { 237 struct virtio_gpu_ctrl_hdr hdr; 238 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 239 __le32 capset_id; 240 __le32 capset_max_version; 241 __le32 capset_max_size; 242 __le32 padding; 243 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 244 }; 245 struct virtio_gpu_get_capset { 246 struct virtio_gpu_ctrl_hdr hdr; 247 __le32 capset_id; 248 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 249 __le32 capset_version; 250 }; 251 struct virtio_gpu_resp_capset { 252 struct virtio_gpu_ctrl_hdr hdr; 253 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 254 uint8_t capset_data[]; 255 }; 256 #define VIRTIO_GPU_EVENT_DISPLAY (1 << 0) 257 struct virtio_gpu_config { 258 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 259 __u32 events_read; 260 __u32 events_clear; 261 __u32 num_scanouts; 262 __u32 num_capsets; 263 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 264 }; 265 enum virtio_gpu_formats { 266 VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM = 1, 267 VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM = 2, 268 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 269 VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM = 3, 270 VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM = 4, 271 VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM = 67, 272 VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM = 68, 273 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 274 VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM = 121, 275 VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM = 134, 276 }; 277 #endif 278 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 279
