1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. 7 * Copyright (C) 2013 Cavium, Inc. 8 * Authors: Sanjay Lal <sanjayl (at) kymasys.com> 9 */ 10 11 #ifndef __LINUX_KVM_MIPS_H 12 #define __LINUX_KVM_MIPS_H 13 14 #include <linux/types.h> 15 16 /* 17 * KVM MIPS specific structures and definitions. 18 * 19 * Some parts derived from the x86 version of this file. 20 */ 21 22 /* 23 * for KVM_GET_REGS and KVM_SET_REGS 24 * 25 * If Config[AT] is zero (32-bit CPU), the register contents are 26 * stored in the lower 32-bits of the struct kvm_regs fields and sign 27 * extended to 64-bits. 28 */ 29 struct kvm_regs { 30 /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */ 31 __u64 gpr[32]; 32 __u64 hi; 33 __u64 lo; 34 __u64 pc; 35 }; 36 37 /* 38 * for KVM_GET_FPU and KVM_SET_FPU 39 */ 40 struct kvm_fpu { 41 }; 42 43 44 /* 45 * For MIPS, we use KVM_SET_ONE_REG and KVM_GET_ONE_REG to access various 46 * registers. The id field is broken down as follows: 47 * 48 * bits[63..52] - As per linux/kvm.h 49 * bits[51..32] - Must be zero. 50 * bits[31..16] - Register set. 51 * 52 * Register set = 0: GP registers from kvm_regs (see definitions below). 53 * 54 * Register set = 1: CP0 registers. 55 * bits[15..8] - Must be zero. 56 * bits[7..3] - Register 'rd' index. 57 * bits[2..0] - Register 'sel' index. 58 * 59 * Register set = 2: KVM specific registers (see definitions below). 60 * 61 * Register set = 3: FPU / MSA registers (see definitions below). 62 * 63 * Other sets registers may be added in the future. Each set would 64 * have its own identifier in bits[31..16]. 65 */ 66 67 #define KVM_REG_MIPS_GP (KVM_REG_MIPS | 0x0000000000000000ULL) 68 #define KVM_REG_MIPS_CP0 (KVM_REG_MIPS | 0x0000000000010000ULL) 69 #define KVM_REG_MIPS_KVM (KVM_REG_MIPS | 0x0000000000020000ULL) 70 #define KVM_REG_MIPS_FPU (KVM_REG_MIPS | 0x0000000000030000ULL) 71 72 73 /* 74 * KVM_REG_MIPS_GP - General purpose registers from kvm_regs. 75 */ 76 77 #define KVM_REG_MIPS_R0 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 0) 78 #define KVM_REG_MIPS_R1 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 1) 79 #define KVM_REG_MIPS_R2 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 2) 80 #define KVM_REG_MIPS_R3 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 3) 81 #define KVM_REG_MIPS_R4 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 4) 82 #define KVM_REG_MIPS_R5 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 5) 83 #define KVM_REG_MIPS_R6 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 6) 84 #define KVM_REG_MIPS_R7 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 7) 85 #define KVM_REG_MIPS_R8 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 8) 86 #define KVM_REG_MIPS_R9 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 9) 87 #define KVM_REG_MIPS_R10 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 10) 88 #define KVM_REG_MIPS_R11 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 11) 89 #define KVM_REG_MIPS_R12 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 12) 90 #define KVM_REG_MIPS_R13 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 13) 91 #define KVM_REG_MIPS_R14 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 14) 92 #define KVM_REG_MIPS_R15 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 15) 93 #define KVM_REG_MIPS_R16 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 16) 94 #define KVM_REG_MIPS_R17 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 17) 95 #define KVM_REG_MIPS_R18 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 18) 96 #define KVM_REG_MIPS_R19 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 19) 97 #define KVM_REG_MIPS_R20 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 20) 98 #define KVM_REG_MIPS_R21 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 21) 99 #define KVM_REG_MIPS_R22 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 22) 100 #define KVM_REG_MIPS_R23 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 23) 101 #define KVM_REG_MIPS_R24 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 24) 102 #define KVM_REG_MIPS_R25 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 25) 103 #define KVM_REG_MIPS_R26 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 26) 104 #define KVM_REG_MIPS_R27 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 27) 105 #define KVM_REG_MIPS_R28 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 28) 106 #define KVM_REG_MIPS_R29 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 29) 107 #define KVM_REG_MIPS_R30 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 30) 108 #define KVM_REG_MIPS_R31 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 31) 109 110 #define KVM_REG_MIPS_HI (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 32) 111 #define KVM_REG_MIPS_LO (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 33) 112 #define KVM_REG_MIPS_PC (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 34) 113 114 115 /* 116 * KVM_REG_MIPS_KVM - KVM specific control registers. 117 */ 118 119 /* 120 * CP0_Count control 121 * DC: Set 0: Master disable CP0_Count and set COUNT_RESUME to now 122 * Set 1: Master re-enable CP0_Count with unchanged bias, handling timer 123 * interrupts since COUNT_RESUME 124 * This can be used to freeze the timer to get a consistent snapshot of 125 * the CP0_Count and timer interrupt pending state, while also resuming 126 * safely without losing time or guest timer interrupts. 127 * Other: Reserved, do not change. 128 */ 129 #define KVM_REG_MIPS_COUNT_CTL (KVM_REG_MIPS_KVM | KVM_REG_SIZE_U64 | 0) 130 #define KVM_REG_MIPS_COUNT_CTL_DC 0x00000001 131 132 /* 133 * CP0_Count resume monotonic nanoseconds 134 * The monotonic nanosecond time of the last set of COUNT_CTL.DC (master 135 * disable). Any reads and writes of Count related registers while 136 * COUNT_CTL.DC=1 will appear to occur at this time. When COUNT_CTL.DC is 137 * cleared again (master enable) any timer interrupts since this time will be 138 * emulated. 139 * Modifications to times in the future are rejected. 140 */ 141 #define KVM_REG_MIPS_COUNT_RESUME (KVM_REG_MIPS_KVM | KVM_REG_SIZE_U64 | 1) 142 /* 143 * CP0_Count rate in Hz 144 * Specifies the rate of the CP0_Count timer in Hz. Modifications occur without 145 * discontinuities in CP0_Count. 146 */ 147 #define KVM_REG_MIPS_COUNT_HZ (KVM_REG_MIPS_KVM | KVM_REG_SIZE_U64 | 2) 148 149 150 /* 151 * KVM_REG_MIPS_FPU - Floating Point and MIPS SIMD Architecture (MSA) registers. 152 * 153 * bits[15..8] - Register subset (see definitions below). 154 * bits[7..5] - Must be zero. 155 * bits[4..0] - Register number within register subset. 156 */ 157 158 #define KVM_REG_MIPS_FPR (KVM_REG_MIPS_FPU | 0x0000000000000000ULL) 159 #define KVM_REG_MIPS_FCR (KVM_REG_MIPS_FPU | 0x0000000000000100ULL) 160 #define KVM_REG_MIPS_MSACR (KVM_REG_MIPS_FPU | 0x0000000000000200ULL) 161 162 /* 163 * KVM_REG_MIPS_FPR - Floating point / Vector registers. 164 */ 165 #define KVM_REG_MIPS_FPR_32(n) (KVM_REG_MIPS_FPR | KVM_REG_SIZE_U32 | (n)) 166 #define KVM_REG_MIPS_FPR_64(n) (KVM_REG_MIPS_FPR | KVM_REG_SIZE_U64 | (n)) 167 #define KVM_REG_MIPS_VEC_128(n) (KVM_REG_MIPS_FPR | KVM_REG_SIZE_U128 | (n)) 168 169 /* 170 * KVM_REG_MIPS_FCR - Floating point control registers. 171 */ 172 #define KVM_REG_MIPS_FCR_IR (KVM_REG_MIPS_FCR | KVM_REG_SIZE_U32 | 0) 173 #define KVM_REG_MIPS_FCR_CSR (KVM_REG_MIPS_FCR | KVM_REG_SIZE_U32 | 31) 174 175 /* 176 * KVM_REG_MIPS_MSACR - MIPS SIMD Architecture (MSA) control registers. 177 */ 178 #define KVM_REG_MIPS_MSA_IR (KVM_REG_MIPS_MSACR | KVM_REG_SIZE_U32 | 0) 179 #define KVM_REG_MIPS_MSA_CSR (KVM_REG_MIPS_MSACR | KVM_REG_SIZE_U32 | 1) 180 181 182 /* 183 * KVM MIPS specific structures and definitions 184 * 185 */ 186 struct kvm_debug_exit_arch { 187 __u64 epc; 188 }; 189 190 /* for KVM_SET_GUEST_DEBUG */ 191 struct kvm_guest_debug_arch { 192 }; 193 194 /* definition of registers in kvm_run */ 195 struct kvm_sync_regs { 196 }; 197 198 /* dummy definition */ 199 struct kvm_sregs { 200 }; 201 202 struct kvm_mips_interrupt { 203 /* in */ 204 __u32 cpu; 205 __u32 irq; 206 }; 207 208 #endif /* __LINUX_KVM_MIPS_H */ 209
