1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef _AMDGPU_TEST_H_ 25 #define _AMDGPU_TEST_H_ 26 27 #include "amdgpu.h" 28 #include "amdgpu_drm.h" 29 30 /** 31 * Define max. number of card in system which we are able to handle 32 */ 33 #define MAX_CARDS_SUPPORTED 4 34 35 /* Forward reference for array to keep "drm" handles */ 36 extern int drm_amdgpu[MAX_CARDS_SUPPORTED]; 37 38 /************************* Basic test suite ********************************/ 39 40 /* 41 * Define basic test suite to serve as the starting point for future testing 42 */ 43 44 /** 45 * Initialize basic test suite 46 */ 47 int suite_basic_tests_init(); 48 49 /** 50 * Deinitialize basic test suite 51 */ 52 int suite_basic_tests_clean(); 53 54 /** 55 * Tests in basic test suite 56 */ 57 extern CU_TestInfo basic_tests[]; 58 59 /** 60 * Initialize bo test suite 61 */ 62 int suite_bo_tests_init(); 63 64 /** 65 * Deinitialize bo test suite 66 */ 67 int suite_bo_tests_clean(); 68 69 /** 70 * Tests in bo test suite 71 */ 72 extern CU_TestInfo bo_tests[]; 73 74 /** 75 * Initialize cs test suite 76 */ 77 int suite_cs_tests_init(); 78 79 /** 80 * Deinitialize cs test suite 81 */ 82 int suite_cs_tests_clean(); 83 84 /** 85 * Tests in cs test suite 86 */ 87 extern CU_TestInfo cs_tests[]; 88 89 /** 90 * Initialize vce test suite 91 */ 92 int suite_vce_tests_init(); 93 94 /** 95 * Deinitialize vce test suite 96 */ 97 int suite_vce_tests_clean(); 98 99 /** 100 * Tests in vce test suite 101 */ 102 extern CU_TestInfo vce_tests[]; 103 104 /** 105 * Helper functions 106 */ 107 static inline amdgpu_bo_handle gpu_mem_alloc( 108 amdgpu_device_handle device_handle, 109 uint64_t size, 110 uint64_t alignment, 111 uint32_t type, 112 uint64_t flags, 113 uint64_t *vmc_addr, 114 amdgpu_va_handle *va_handle) 115 { 116 struct amdgpu_bo_alloc_request req = {0}; 117 amdgpu_bo_handle buf_handle; 118 int r; 119 120 CU_ASSERT_NOT_EQUAL(vmc_addr, NULL); 121 122 req.alloc_size = size; 123 req.phys_alignment = alignment; 124 req.preferred_heap = type; 125 req.flags = flags; 126 127 r = amdgpu_bo_alloc(device_handle, &req, &buf_handle); 128 CU_ASSERT_EQUAL(r, 0); 129 130 r = amdgpu_va_range_alloc(device_handle, 131 amdgpu_gpu_va_range_general, 132 size, alignment, 0, vmc_addr, 133 va_handle, 0); 134 CU_ASSERT_EQUAL(r, 0); 135 136 r = amdgpu_bo_va_op(buf_handle, 0, size, *vmc_addr, 0, AMDGPU_VA_OP_MAP); 137 CU_ASSERT_EQUAL(r, 0); 138 139 return buf_handle; 140 } 141 142 static inline int gpu_mem_free(amdgpu_bo_handle bo, 143 amdgpu_va_handle va_handle, 144 uint64_t vmc_addr, 145 uint64_t size) 146 { 147 int r; 148 149 r = amdgpu_bo_va_op(bo, 0, size, vmc_addr, 0, AMDGPU_VA_OP_UNMAP); 150 CU_ASSERT_EQUAL(r, 0); 151 152 r = amdgpu_va_range_free(va_handle); 153 CU_ASSERT_EQUAL(r, 0); 154 155 r = amdgpu_bo_free(bo); 156 CU_ASSERT_EQUAL(r, 0); 157 158 return 0; 159 } 160 161 static inline int 162 amdgpu_bo_alloc_and_map(amdgpu_device_handle dev, unsigned size, 163 unsigned alignment, unsigned heap, uint64_t flags, 164 amdgpu_bo_handle *bo, void **cpu, uint64_t *mc_address, 165 amdgpu_va_handle *va_handle) 166 { 167 struct amdgpu_bo_alloc_request request = {}; 168 amdgpu_bo_handle buf_handle; 169 amdgpu_va_handle handle; 170 uint64_t vmc_addr; 171 int r; 172 173 request.alloc_size = size; 174 request.phys_alignment = alignment; 175 request.preferred_heap = heap; 176 request.flags = flags; 177 178 r = amdgpu_bo_alloc(dev, &request, &buf_handle); 179 if (r) 180 return r; 181 182 r = amdgpu_va_range_alloc(dev, 183 amdgpu_gpu_va_range_general, 184 size, alignment, 0, &vmc_addr, 185 &handle, 0); 186 if (r) 187 goto error_va_alloc; 188 189 r = amdgpu_bo_va_op(buf_handle, 0, size, vmc_addr, 0, AMDGPU_VA_OP_MAP); 190 if (r) 191 goto error_va_map; 192 193 r = amdgpu_bo_cpu_map(buf_handle, cpu); 194 if (r) 195 goto error_cpu_map; 196 197 *bo = buf_handle; 198 *mc_address = vmc_addr; 199 *va_handle = handle; 200 201 return 0; 202 203 error_cpu_map: 204 amdgpu_bo_cpu_unmap(buf_handle); 205 206 error_va_map: 207 amdgpu_bo_va_op(buf_handle, 0, size, vmc_addr, 0, AMDGPU_VA_OP_UNMAP); 208 209 error_va_alloc: 210 amdgpu_bo_free(buf_handle); 211 return r; 212 } 213 214 static inline int 215 amdgpu_bo_unmap_and_free(amdgpu_bo_handle bo, amdgpu_va_handle va_handle, 216 uint64_t mc_addr, uint64_t size) 217 { 218 amdgpu_bo_cpu_unmap(bo); 219 amdgpu_bo_va_op(bo, 0, size, mc_addr, 0, AMDGPU_VA_OP_UNMAP); 220 amdgpu_va_range_free(va_handle); 221 amdgpu_bo_free(bo); 222 223 return 0; 224 225 } 226 227 static inline int 228 amdgpu_get_bo_list(amdgpu_device_handle dev, amdgpu_bo_handle bo1, 229 amdgpu_bo_handle bo2, amdgpu_bo_list_handle *list) 230 { 231 amdgpu_bo_handle resources[] = {bo1, bo2}; 232 233 return amdgpu_bo_list_create(dev, bo2 ? 2 : 1, resources, NULL, list); 234 } 235 236 #endif /* #ifdef _AMDGPU_TEST_H_ */ 237
