1 //===-- EvergreenInstructions.td - EG Instruction defs ----*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // TableGen definitions for instructions which are: 11 // - Available to Evergreen and newer VLIW4/VLIW5 GPUs 12 // - Available only on Evergreen family GPUs. 13 // 14 //===----------------------------------------------------------------------===// 15 16 def isEG : Predicate< 17 "Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && " 18 "Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && " 19 "!Subtarget->hasCaymanISA()" 20 >; 21 22 def isEGorCayman : Predicate< 23 "Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||" 24 "Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS" 25 >; 26 27 //===----------------------------------------------------------------------===// 28 // Evergreen / Cayman store instructions 29 //===----------------------------------------------------------------------===// 30 31 let Predicates = [isEGorCayman] in { 32 33 class CF_MEM_RAT_CACHELESS <bits<6> rat_inst, bits<4> rat_id, bits<4> mask, dag ins, 34 string name, list<dag> pattern> 35 : EG_CF_RAT <0x57, rat_inst, rat_id, mask, (outs), ins, 36 "MEM_RAT_CACHELESS "#name, pattern>; 37 38 class CF_MEM_RAT <bits<6> rat_inst, bits<4> rat_id, dag ins, string name, 39 list<dag> pattern> 40 : EG_CF_RAT <0x56, rat_inst, rat_id, 0xf /* mask */, (outs), ins, 41 "MEM_RAT "#name, pattern>; 42 43 class CF_MEM_RAT_STORE_TYPED<bits<1> has_eop> 44 : CF_MEM_RAT <0x1, ?, (ins R600_Reg128:$rw_gpr, R600_Reg128:$index_gpr, 45 i32imm:$rat_id, InstFlag:$eop), 46 "STORE_TYPED RAT($rat_id) $rw_gpr, $index_gpr" 47 #!if(has_eop, ", $eop", ""), 48 [(int_r600_rat_store_typed R600_Reg128:$rw_gpr, 49 R600_Reg128:$index_gpr, 50 (i32 imm:$rat_id))]>; 51 52 def RAT_MSKOR : CF_MEM_RAT <0x11, 0, 53 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr), 54 "MSKOR $rw_gpr.XW, $index_gpr", 55 [(mskor_global v4i32:$rw_gpr, i32:$index_gpr)] 56 > { 57 let eop = 0; 58 } 59 60 } // End let Predicates = [isEGorCayman] 61 62 //===----------------------------------------------------------------------===// 63 // Evergreen Only instructions 64 //===----------------------------------------------------------------------===// 65 66 let Predicates = [isEG] in { 67 68 def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>; 69 defm DIV_eg : DIV_Common<RECIP_IEEE_eg>; 70 71 def MULLO_INT_eg : MULLO_INT_Common<0x8F>; 72 def MULHI_INT_eg : MULHI_INT_Common<0x90>; 73 def MULLO_UINT_eg : MULLO_UINT_Common<0x91>; 74 def MULHI_UINT_eg : MULHI_UINT_Common<0x92>; 75 def RECIP_UINT_eg : RECIP_UINT_Common<0x94>; 76 def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>; 77 def EXP_IEEE_eg : EXP_IEEE_Common<0x81>; 78 def LOG_IEEE_eg : LOG_IEEE_Common<0x83>; 79 def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>; 80 def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>; 81 def : RsqPat<RECIPSQRT_IEEE_eg, f32>; 82 def SIN_eg : SIN_Common<0x8D>; 83 def COS_eg : COS_Common<0x8E>; 84 85 def : POW_Common <LOG_IEEE_eg, EXP_IEEE_eg, MUL>; 86 def : Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_eg $src))>; 87 88 defm : Expand24IBitOps<MULLO_INT_eg, ADD_INT>; 89 90 //===----------------------------------------------------------------------===// 91 // Memory read/write instructions 92 //===----------------------------------------------------------------------===// 93 94 let usesCustomInserter = 1 in { 95 96 // 32-bit store 97 def RAT_WRITE_CACHELESS_32_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0x1, 98 (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop), 99 "STORE_RAW $rw_gpr, $index_gpr, $eop", 100 [(global_store i32:$rw_gpr, i32:$index_gpr)] 101 >; 102 103 // 64-bit store 104 def RAT_WRITE_CACHELESS_64_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0x3, 105 (ins R600_Reg64:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop), 106 "STORE_RAW $rw_gpr.XY, $index_gpr, $eop", 107 [(global_store v2i32:$rw_gpr, i32:$index_gpr)] 108 >; 109 110 //128-bit store 111 def RAT_WRITE_CACHELESS_128_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0xf, 112 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop), 113 "STORE_RAW $rw_gpr.XYZW, $index_gpr, $eop", 114 [(global_store v4i32:$rw_gpr, i32:$index_gpr)] 115 >; 116 117 def RAT_STORE_TYPED_eg: CF_MEM_RAT_STORE_TYPED<1>; 118 119 } // End usesCustomInserter = 1 120 121 class VTX_READ_eg <string name, bits<8> buffer_id, dag outs, list<dag> pattern> 122 : VTX_WORD0_eg, VTX_READ<name, buffer_id, outs, pattern> { 123 124 // Static fields 125 let VC_INST = 0; 126 let FETCH_TYPE = 2; 127 let FETCH_WHOLE_QUAD = 0; 128 let BUFFER_ID = buffer_id; 129 let SRC_REL = 0; 130 // XXX: We can infer this field based on the SRC_GPR. This would allow us 131 // to store vertex addresses in any channel, not just X. 132 let SRC_SEL_X = 0; 133 134 let Inst{31-0} = Word0; 135 } 136 137 class VTX_READ_8_eg <bits<8> buffer_id, list<dag> pattern> 138 : VTX_READ_eg <"VTX_READ_8 $dst_gpr, $src_gpr", buffer_id, 139 (outs R600_TReg32_X:$dst_gpr), pattern> { 140 141 let MEGA_FETCH_COUNT = 1; 142 let DST_SEL_X = 0; 143 let DST_SEL_Y = 7; // Masked 144 let DST_SEL_Z = 7; // Masked 145 let DST_SEL_W = 7; // Masked 146 let DATA_FORMAT = 1; // FMT_8 147 } 148 149 class VTX_READ_16_eg <bits<8> buffer_id, list<dag> pattern> 150 : VTX_READ_eg <"VTX_READ_16 $dst_gpr, $src_gpr", buffer_id, 151 (outs R600_TReg32_X:$dst_gpr), pattern> { 152 let MEGA_FETCH_COUNT = 2; 153 let DST_SEL_X = 0; 154 let DST_SEL_Y = 7; // Masked 155 let DST_SEL_Z = 7; // Masked 156 let DST_SEL_W = 7; // Masked 157 let DATA_FORMAT = 5; // FMT_16 158 159 } 160 161 class VTX_READ_32_eg <bits<8> buffer_id, list<dag> pattern> 162 : VTX_READ_eg <"VTX_READ_32 $dst_gpr, $src_gpr", buffer_id, 163 (outs R600_TReg32_X:$dst_gpr), pattern> { 164 165 let MEGA_FETCH_COUNT = 4; 166 let DST_SEL_X = 0; 167 let DST_SEL_Y = 7; // Masked 168 let DST_SEL_Z = 7; // Masked 169 let DST_SEL_W = 7; // Masked 170 let DATA_FORMAT = 0xD; // COLOR_32 171 172 // This is not really necessary, but there were some GPU hangs that appeared 173 // to be caused by ALU instructions in the next instruction group that wrote 174 // to the $src_gpr registers of the VTX_READ. 175 // e.g. 176 // %T3_X<def> = VTX_READ_PARAM_32_eg %T2_X<kill>, 24 177 // %T2_X<def> = MOV %ZERO 178 //Adding this constraint prevents this from happening. 179 let Constraints = "$src_gpr.ptr = $dst_gpr"; 180 } 181 182 class VTX_READ_64_eg <bits<8> buffer_id, list<dag> pattern> 183 : VTX_READ_eg <"VTX_READ_64 $dst_gpr.XY, $src_gpr", buffer_id, 184 (outs R600_Reg64:$dst_gpr), pattern> { 185 186 let MEGA_FETCH_COUNT = 8; 187 let DST_SEL_X = 0; 188 let DST_SEL_Y = 1; 189 let DST_SEL_Z = 7; 190 let DST_SEL_W = 7; 191 let DATA_FORMAT = 0x1D; // COLOR_32_32 192 } 193 194 class VTX_READ_128_eg <bits<8> buffer_id, list<dag> pattern> 195 : VTX_READ_eg <"VTX_READ_128 $dst_gpr.XYZW, $src_gpr", buffer_id, 196 (outs R600_Reg128:$dst_gpr), pattern> { 197 198 let MEGA_FETCH_COUNT = 16; 199 let DST_SEL_X = 0; 200 let DST_SEL_Y = 1; 201 let DST_SEL_Z = 2; 202 let DST_SEL_W = 3; 203 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32 204 205 // XXX: Need to force VTX_READ_128 instructions to write to the same register 206 // that holds its buffer address to avoid potential hangs. We can't use 207 // the same constraint as VTX_READ_32_eg, because the $src_gpr.ptr and $dst 208 // registers are different sizes. 209 } 210 211 //===----------------------------------------------------------------------===// 212 // VTX Read from parameter memory space 213 //===----------------------------------------------------------------------===// 214 215 def VTX_READ_PARAM_8_eg : VTX_READ_8_eg <0, 216 [(set i32:$dst_gpr, (load_param_exti8 ADDRVTX_READ:$src_gpr))] 217 >; 218 219 def VTX_READ_PARAM_16_eg : VTX_READ_16_eg <0, 220 [(set i32:$dst_gpr, (load_param_exti16 ADDRVTX_READ:$src_gpr))] 221 >; 222 223 def VTX_READ_PARAM_32_eg : VTX_READ_32_eg <0, 224 [(set i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))] 225 >; 226 227 def VTX_READ_PARAM_64_eg : VTX_READ_64_eg <0, 228 [(set v2i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))] 229 >; 230 231 def VTX_READ_PARAM_128_eg : VTX_READ_128_eg <0, 232 [(set v4i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))] 233 >; 234 235 //===----------------------------------------------------------------------===// 236 // VTX Read from global memory space 237 //===----------------------------------------------------------------------===// 238 239 // 8-bit reads 240 def VTX_READ_GLOBAL_8_eg : VTX_READ_8_eg <1, 241 [(set i32:$dst_gpr, (az_extloadi8_global ADDRVTX_READ:$src_gpr))] 242 >; 243 244 def VTX_READ_GLOBAL_16_eg : VTX_READ_16_eg <1, 245 [(set i32:$dst_gpr, (az_extloadi16_global ADDRVTX_READ:$src_gpr))] 246 >; 247 248 // 32-bit reads 249 def VTX_READ_GLOBAL_32_eg : VTX_READ_32_eg <1, 250 [(set i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))] 251 >; 252 253 // 64-bit reads 254 def VTX_READ_GLOBAL_64_eg : VTX_READ_64_eg <1, 255 [(set v2i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))] 256 >; 257 258 // 128-bit reads 259 def VTX_READ_GLOBAL_128_eg : VTX_READ_128_eg <1, 260 [(set v4i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))] 261 >; 262 263 } // End Predicates = [isEG] 264 265 //===----------------------------------------------------------------------===// 266 // Evergreen / Cayman Instructions 267 //===----------------------------------------------------------------------===// 268 269 let Predicates = [isEGorCayman] in { 270 271 // Should be predicated on FeatureFP64 272 // def FMA_64 : R600_3OP < 273 // 0xA, "FMA_64", 274 // [(set f64:$dst, (fma f64:$src0, f64:$src1, f64:$src2))] 275 // >; 276 277 // BFE_UINT - bit_extract, an optimization for mask and shift 278 // Src0 = Input 279 // Src1 = Offset 280 // Src2 = Width 281 // 282 // bit_extract = (Input << (32 - Offset - Width)) >> (32 - Width) 283 // 284 // Example Usage: 285 // (Offset, Width) 286 // 287 // (0, 8) = (Input << 24) >> 24 = (Input & 0xff) >> 0 288 // (8, 8) = (Input << 16) >> 24 = (Input & 0xffff) >> 8 289 // (16, 8) = (Input << 8) >> 24 = (Input & 0xffffff) >> 16 290 // (24, 8) = (Input << 0) >> 24 = (Input & 0xffffffff) >> 24 291 def BFE_UINT_eg : R600_3OP <0x4, "BFE_UINT", 292 [(set i32:$dst, (AMDGPUbfe_u32 i32:$src0, i32:$src1, i32:$src2))], 293 VecALU 294 >; 295 296 def BFE_INT_eg : R600_3OP <0x5, "BFE_INT", 297 [(set i32:$dst, (AMDGPUbfe_i32 i32:$src0, i32:$src1, i32:$src2))], 298 VecALU 299 >; 300 301 def : BFEPattern <BFE_UINT_eg, MOV_IMM_I32>; 302 303 def BFI_INT_eg : R600_3OP <0x06, "BFI_INT", 304 [(set i32:$dst, (AMDGPUbfi i32:$src0, i32:$src1, i32:$src2))], 305 VecALU 306 >; 307 308 def : Pat<(i32 (sext_inreg i32:$src, i1)), 309 (BFE_INT_eg i32:$src, (i32 ZERO), (i32 ONE_INT))>; 310 def : Pat<(i32 (sext_inreg i32:$src, i8)), 311 (BFE_INT_eg i32:$src, (i32 ZERO), (MOV_IMM_I32 8))>; 312 def : Pat<(i32 (sext_inreg i32:$src, i16)), 313 (BFE_INT_eg i32:$src, (i32 ZERO), (MOV_IMM_I32 16))>; 314 315 defm : BFIPatterns <BFI_INT_eg, MOV_IMM_I32, R600_Reg64>; 316 317 def BFM_INT_eg : R600_2OP <0xA0, "BFM_INT", 318 [(set i32:$dst, (AMDGPUbfm i32:$src0, i32:$src1))], 319 VecALU 320 >; 321 322 def MULADD_UINT24_eg : R600_3OP <0x10, "MULADD_UINT24", 323 [(set i32:$dst, (AMDGPUmad_u24 i32:$src0, i32:$src1, i32:$src2))], VecALU 324 >; 325 326 def : UMad24Pat<MULADD_UINT24_eg>; 327 328 def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT", [], VecALU>; 329 def : ROTRPattern <BIT_ALIGN_INT_eg>; 330 def MULADD_eg : MULADD_Common<0x14>; 331 def MULADD_IEEE_eg : MULADD_IEEE_Common<0x18>; 332 def FMA_eg : FMA_Common<0x7>; 333 def ASHR_eg : ASHR_Common<0x15>; 334 def LSHR_eg : LSHR_Common<0x16>; 335 def LSHL_eg : LSHL_Common<0x17>; 336 def CNDE_eg : CNDE_Common<0x19>; 337 def CNDGT_eg : CNDGT_Common<0x1A>; 338 def CNDGE_eg : CNDGE_Common<0x1B>; 339 def MUL_LIT_eg : MUL_LIT_Common<0x1F>; 340 def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>; 341 def MUL_UINT24_eg : R600_2OP <0xB5, "MUL_UINT24", 342 [(set i32:$dst, (AMDGPUmul_u24 i32:$src0, i32:$src1))], VecALU 343 >; 344 def DOT4_eg : DOT4_Common<0xBE>; 345 defm CUBE_eg : CUBE_Common<0xC0>; 346 347 def BCNT_INT : R600_1OP_Helper <0xAA, "BCNT_INT", ctpop, VecALU>; 348 349 def ADDC_UINT : R600_2OP_Helper <0x52, "ADDC_UINT", AMDGPUcarry>; 350 def SUBB_UINT : R600_2OP_Helper <0x53, "SUBB_UINT", AMDGPUborrow>; 351 352 def FFBH_UINT : R600_1OP_Helper <0xAB, "FFBH_UINT", ctlz_zero_undef, VecALU>; 353 def FFBL_INT : R600_1OP_Helper <0xAC, "FFBL_INT", cttz_zero_undef, VecALU>; 354 355 let hasSideEffects = 1 in { 356 def MOVA_INT_eg : R600_1OP <0xCC, "MOVA_INT", [], VecALU>; 357 } 358 359 def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common<MUL_LIT_eg, LOG_CLAMPED_eg, EXP_IEEE_eg>; 360 361 def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> { 362 let Pattern = []; 363 let Itinerary = AnyALU; 364 } 365 366 def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>; 367 368 def FLT_TO_UINT_eg : FLT_TO_UINT_Common<0x9A> { 369 let Pattern = []; 370 } 371 372 def UINT_TO_FLT_eg : UINT_TO_FLT_Common<0x9C>; 373 374 def GROUP_BARRIER : InstR600 < 375 (outs), (ins), " GROUP_BARRIER", [(int_AMDGPU_barrier_local), (int_AMDGPU_barrier_global)], AnyALU>, 376 R600ALU_Word0, 377 R600ALU_Word1_OP2 <0x54> { 378 379 let dst = 0; 380 let dst_rel = 0; 381 let src0 = 0; 382 let src0_rel = 0; 383 let src0_neg = 0; 384 let src0_abs = 0; 385 let src1 = 0; 386 let src1_rel = 0; 387 let src1_neg = 0; 388 let src1_abs = 0; 389 let write = 0; 390 let omod = 0; 391 let clamp = 0; 392 let last = 1; 393 let bank_swizzle = 0; 394 let pred_sel = 0; 395 let update_exec_mask = 0; 396 let update_pred = 0; 397 398 let Inst{31-0} = Word0; 399 let Inst{63-32} = Word1; 400 401 let ALUInst = 1; 402 } 403 404 def : Pat < 405 (int_AMDGPU_barrier_global), 406 (GROUP_BARRIER) 407 >; 408 409 //===----------------------------------------------------------------------===// 410 // LDS Instructions 411 //===----------------------------------------------------------------------===// 412 class R600_LDS <bits<6> op, dag outs, dag ins, string asm, 413 list<dag> pattern = []> : 414 415 InstR600 <outs, ins, asm, pattern, XALU>, 416 R600_ALU_LDS_Word0, 417 R600LDS_Word1 { 418 419 bits<6> offset = 0; 420 let lds_op = op; 421 422 let Word1{27} = offset{0}; 423 let Word1{12} = offset{1}; 424 let Word1{28} = offset{2}; 425 let Word1{31} = offset{3}; 426 let Word0{12} = offset{4}; 427 let Word0{25} = offset{5}; 428 429 430 let Inst{31-0} = Word0; 431 let Inst{63-32} = Word1; 432 433 let ALUInst = 1; 434 let HasNativeOperands = 1; 435 let UseNamedOperandTable = 1; 436 } 437 438 class R600_LDS_1A <bits<6> lds_op, string name, list<dag> pattern> : R600_LDS < 439 lds_op, 440 (outs R600_Reg32:$dst), 441 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel, 442 LAST:$last, R600_Pred:$pred_sel, 443 BANK_SWIZZLE:$bank_swizzle), 444 " "#name#" $last OQAP, $src0$src0_rel $pred_sel", 445 pattern 446 > { 447 448 let src1 = 0; 449 let src1_rel = 0; 450 let src2 = 0; 451 let src2_rel = 0; 452 453 let usesCustomInserter = 1; 454 let LDS_1A = 1; 455 let DisableEncoding = "$dst"; 456 } 457 458 class R600_LDS_1A1D <bits<6> lds_op, dag outs, string name, list<dag> pattern, 459 string dst =""> : 460 R600_LDS < 461 lds_op, outs, 462 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel, 463 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel, 464 LAST:$last, R600_Pred:$pred_sel, 465 BANK_SWIZZLE:$bank_swizzle), 466 " "#name#" $last "#dst#"$src0$src0_rel, $src1$src1_rel, $pred_sel", 467 pattern 468 > { 469 470 field string BaseOp; 471 472 let src2 = 0; 473 let src2_rel = 0; 474 let LDS_1A1D = 1; 475 } 476 477 class R600_LDS_1A1D_NORET <bits<6> lds_op, string name, list<dag> pattern> : 478 R600_LDS_1A1D <lds_op, (outs), name, pattern> { 479 let BaseOp = name; 480 } 481 482 class R600_LDS_1A1D_RET <bits<6> lds_op, string name, list<dag> pattern> : 483 R600_LDS_1A1D <lds_op, (outs R600_Reg32:$dst), name##"_RET", pattern, "OQAP, "> { 484 485 let BaseOp = name; 486 let usesCustomInserter = 1; 487 let DisableEncoding = "$dst"; 488 } 489 490 class R600_LDS_1A2D <bits<6> lds_op, dag outs, string name, list<dag> pattern, 491 string dst =""> : 492 R600_LDS < 493 lds_op, outs, 494 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel, 495 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel, 496 R600_Reg32:$src2, REL:$src2_rel, SEL:$src2_sel, 497 LAST:$last, R600_Pred:$pred_sel, BANK_SWIZZLE:$bank_swizzle), 498 " "#name# "$last "#dst#"$src0$src0_rel, $src1$src1_rel, $src2$src2_rel, $pred_sel", 499 pattern> { 500 501 field string BaseOp; 502 503 let LDS_1A1D = 0; 504 let LDS_1A2D = 1; 505 } 506 507 class R600_LDS_1A2D_NORET <bits<6> lds_op, string name, list<dag> pattern> : 508 R600_LDS_1A2D <lds_op, (outs), name, pattern> { 509 let BaseOp = name; 510 } 511 512 class R600_LDS_1A2D_RET <bits<6> lds_op, string name, list<dag> pattern> : 513 R600_LDS_1A2D <lds_op, (outs R600_Reg32:$dst), name, pattern> { 514 515 let BaseOp = name; 516 let usesCustomInserter = 1; 517 let DisableEncoding = "$dst"; 518 } 519 520 def LDS_ADD : R600_LDS_1A1D_NORET <0x0, "LDS_ADD", [] >; 521 def LDS_SUB : R600_LDS_1A1D_NORET <0x1, "LDS_SUB", [] >; 522 def LDS_AND : R600_LDS_1A1D_NORET <0x9, "LDS_AND", [] >; 523 def LDS_OR : R600_LDS_1A1D_NORET <0xa, "LDS_OR", [] >; 524 def LDS_XOR : R600_LDS_1A1D_NORET <0xb, "LDS_XOR", [] >; 525 def LDS_WRXCHG: R600_LDS_1A1D_NORET <0xd, "LDS_WRXCHG", [] >; 526 def LDS_CMPST: R600_LDS_1A2D_NORET <0x10, "LDS_CMPST", [] >; 527 def LDS_MIN_INT : R600_LDS_1A1D_NORET <0x5, "LDS_MIN_INT", [] >; 528 def LDS_MAX_INT : R600_LDS_1A1D_NORET <0x6, "LDS_MAX_INT", [] >; 529 def LDS_MIN_UINT : R600_LDS_1A1D_NORET <0x7, "LDS_MIN_UINT", [] >; 530 def LDS_MAX_UINT : R600_LDS_1A1D_NORET <0x8, "LDS_MAX_UINT", [] >; 531 def LDS_WRITE : R600_LDS_1A1D_NORET <0xD, "LDS_WRITE", 532 [(local_store (i32 R600_Reg32:$src1), R600_Reg32:$src0)] 533 >; 534 def LDS_BYTE_WRITE : R600_LDS_1A1D_NORET<0x12, "LDS_BYTE_WRITE", 535 [(truncstorei8_local i32:$src1, i32:$src0)] 536 >; 537 def LDS_SHORT_WRITE : R600_LDS_1A1D_NORET<0x13, "LDS_SHORT_WRITE", 538 [(truncstorei16_local i32:$src1, i32:$src0)] 539 >; 540 def LDS_ADD_RET : R600_LDS_1A1D_RET <0x20, "LDS_ADD", 541 [(set i32:$dst, (atomic_load_add_local i32:$src0, i32:$src1))] 542 >; 543 def LDS_SUB_RET : R600_LDS_1A1D_RET <0x21, "LDS_SUB", 544 [(set i32:$dst, (atomic_load_sub_local i32:$src0, i32:$src1))] 545 >; 546 def LDS_AND_RET : R600_LDS_1A1D_RET <0x29, "LDS_AND", 547 [(set i32:$dst, (atomic_load_and_local i32:$src0, i32:$src1))] 548 >; 549 def LDS_OR_RET : R600_LDS_1A1D_RET <0x2a, "LDS_OR", 550 [(set i32:$dst, (atomic_load_or_local i32:$src0, i32:$src1))] 551 >; 552 def LDS_XOR_RET : R600_LDS_1A1D_RET <0x2b, "LDS_XOR", 553 [(set i32:$dst, (atomic_load_xor_local i32:$src0, i32:$src1))] 554 >; 555 def LDS_MIN_INT_RET : R600_LDS_1A1D_RET <0x25, "LDS_MIN_INT", 556 [(set i32:$dst, (atomic_load_min_local i32:$src0, i32:$src1))] 557 >; 558 def LDS_MAX_INT_RET : R600_LDS_1A1D_RET <0x26, "LDS_MAX_INT", 559 [(set i32:$dst, (atomic_load_max_local i32:$src0, i32:$src1))] 560 >; 561 def LDS_MIN_UINT_RET : R600_LDS_1A1D_RET <0x27, "LDS_MIN_UINT", 562 [(set i32:$dst, (atomic_load_umin_local i32:$src0, i32:$src1))] 563 >; 564 def LDS_MAX_UINT_RET : R600_LDS_1A1D_RET <0x28, "LDS_MAX_UINT", 565 [(set i32:$dst, (atomic_load_umax_local i32:$src0, i32:$src1))] 566 >; 567 def LDS_WRXCHG_RET : R600_LDS_1A1D_RET <0x2d, "LDS_WRXCHG", 568 [(set i32:$dst, (atomic_swap_local i32:$src0, i32:$src1))] 569 >; 570 def LDS_CMPST_RET : R600_LDS_1A2D_RET <0x30, "LDS_CMPST", 571 [(set i32:$dst, (atomic_cmp_swap_32_local i32:$src0, i32:$src1, i32:$src2))] 572 >; 573 def LDS_READ_RET : R600_LDS_1A <0x32, "LDS_READ_RET", 574 [(set (i32 R600_Reg32:$dst), (local_load R600_Reg32:$src0))] 575 >; 576 def LDS_BYTE_READ_RET : R600_LDS_1A <0x36, "LDS_BYTE_READ_RET", 577 [(set i32:$dst, (sextloadi8_local i32:$src0))] 578 >; 579 def LDS_UBYTE_READ_RET : R600_LDS_1A <0x37, "LDS_UBYTE_READ_RET", 580 [(set i32:$dst, (az_extloadi8_local i32:$src0))] 581 >; 582 def LDS_SHORT_READ_RET : R600_LDS_1A <0x38, "LDS_SHORT_READ_RET", 583 [(set i32:$dst, (sextloadi16_local i32:$src0))] 584 >; 585 def LDS_USHORT_READ_RET : R600_LDS_1A <0x39, "LDS_USHORT_READ_RET", 586 [(set i32:$dst, (az_extloadi16_local i32:$src0))] 587 >; 588 589 // TRUNC is used for the FLT_TO_INT instructions to work around a 590 // perceived problem where the rounding modes are applied differently 591 // depending on the instruction and the slot they are in. 592 // See: 593 // https://bugs.freedesktop.org/show_bug.cgi?id=50232 594 // Mesa commit: a1a0974401c467cb86ef818f22df67c21774a38c 595 // 596 // XXX: Lowering SELECT_CC will sometimes generate fp_to_[su]int nodes, 597 // which do not need to be truncated since the fp values are 0.0f or 1.0f. 598 // We should look into handling these cases separately. 599 def : Pat<(fp_to_sint f32:$src0), (FLT_TO_INT_eg (TRUNC $src0))>; 600 601 def : Pat<(fp_to_uint f32:$src0), (FLT_TO_UINT_eg (TRUNC $src0))>; 602 603 // SHA-256 Patterns 604 def : SHA256MaPattern <BFI_INT_eg, XOR_INT>; 605 606 def EG_ExportSwz : ExportSwzInst { 607 let Word1{19-16} = 0; // BURST_COUNT 608 let Word1{20} = 0; // VALID_PIXEL_MODE 609 let Word1{21} = eop; 610 let Word1{29-22} = inst; 611 let Word1{30} = 0; // MARK 612 let Word1{31} = 1; // BARRIER 613 } 614 defm : ExportPattern<EG_ExportSwz, 83>; 615 616 def EG_ExportBuf : ExportBufInst { 617 let Word1{19-16} = 0; // BURST_COUNT 618 let Word1{20} = 0; // VALID_PIXEL_MODE 619 let Word1{21} = eop; 620 let Word1{29-22} = inst; 621 let Word1{30} = 0; // MARK 622 let Word1{31} = 1; // BARRIER 623 } 624 defm : SteamOutputExportPattern<EG_ExportBuf, 0x40, 0x41, 0x42, 0x43>; 625 626 def CF_TC_EG : CF_CLAUSE_EG<1, (ins i32imm:$ADDR, i32imm:$COUNT), 627 "TEX $COUNT @$ADDR"> { 628 let POP_COUNT = 0; 629 } 630 def CF_VC_EG : CF_CLAUSE_EG<2, (ins i32imm:$ADDR, i32imm:$COUNT), 631 "VTX $COUNT @$ADDR"> { 632 let POP_COUNT = 0; 633 } 634 def WHILE_LOOP_EG : CF_CLAUSE_EG<6, (ins i32imm:$ADDR), 635 "LOOP_START_DX10 @$ADDR"> { 636 let POP_COUNT = 0; 637 let COUNT = 0; 638 } 639 def END_LOOP_EG : CF_CLAUSE_EG<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> { 640 let POP_COUNT = 0; 641 let COUNT = 0; 642 } 643 def LOOP_BREAK_EG : CF_CLAUSE_EG<9, (ins i32imm:$ADDR), 644 "LOOP_BREAK @$ADDR"> { 645 let POP_COUNT = 0; 646 let COUNT = 0; 647 } 648 def CF_CONTINUE_EG : CF_CLAUSE_EG<8, (ins i32imm:$ADDR), 649 "CONTINUE @$ADDR"> { 650 let POP_COUNT = 0; 651 let COUNT = 0; 652 } 653 def CF_JUMP_EG : CF_CLAUSE_EG<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 654 "JUMP @$ADDR POP:$POP_COUNT"> { 655 let COUNT = 0; 656 } 657 def CF_PUSH_EG : CF_CLAUSE_EG<11, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 658 "PUSH @$ADDR POP:$POP_COUNT"> { 659 let COUNT = 0; 660 } 661 def CF_ELSE_EG : CF_CLAUSE_EG<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 662 "ELSE @$ADDR POP:$POP_COUNT"> { 663 let COUNT = 0; 664 } 665 def CF_CALL_FS_EG : CF_CLAUSE_EG<19, (ins), "CALL_FS"> { 666 let ADDR = 0; 667 let COUNT = 0; 668 let POP_COUNT = 0; 669 } 670 def POP_EG : CF_CLAUSE_EG<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 671 "POP @$ADDR POP:$POP_COUNT"> { 672 let COUNT = 0; 673 } 674 def CF_END_EG : CF_CLAUSE_EG<0, (ins), "CF_END"> { 675 let COUNT = 0; 676 let POP_COUNT = 0; 677 let ADDR = 0; 678 let END_OF_PROGRAM = 1; 679 } 680 681 } // End Predicates = [isEGorCayman] 682
