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      1 //===-- SISchedule.td - SI Scheduling definitons -------------------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // MachineModel definitions for Southern Islands (SI)
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 def WriteBranch : SchedWrite;
     15 def WriteExport : SchedWrite;
     16 def WriteLDS    : SchedWrite;
     17 def WriteSALU   : SchedWrite;
     18 def WriteSMEM   : SchedWrite;
     19 def WriteVMEM   : SchedWrite;
     20 def WriteBarrier : SchedWrite;
     21 
     22 // Vector ALU instructions
     23 def Write32Bit         : SchedWrite;
     24 def WriteQuarterRate32 : SchedWrite;
     25 def WriteFullOrQuarterRate32 : SchedWrite;
     26 
     27 def WriteFloatFMA   : SchedWrite;
     28 
     29 // Slow quarter rate f64 instruction.
     30 def WriteDouble : SchedWrite;
     31 
     32 // half rate f64 instruction (same as v_add_f64)
     33 def WriteDoubleAdd  : SchedWrite;
     34 
     35 // Half rate 64-bit instructions.
     36 def Write64Bit : SchedWrite;
     37 
     38 // FIXME: Should there be a class for instructions which are VALU
     39 // instructions and have VALU rates, but write to the SALU (i.e. VOPC
     40 // instructions)
     41 
     42 def SIFullSpeedModel : SchedMachineModel;
     43 def SIQuarterSpeedModel : SchedMachineModel;
     44 
     45 // BufferSize = 0 means the processors are in-order.
     46 let BufferSize = 0 in {
     47 
     48 // XXX: Are the resource counts correct?
     49 def HWBranch : ProcResource<1>;
     50 def HWExport : ProcResource<7>;   // Taken from S_WAITCNT
     51 def HWLGKM   : ProcResource<31>;  // Taken from S_WAITCNT
     52 def HWSALU   : ProcResource<1>;
     53 def HWVMEM   : ProcResource<15>;  // Taken from S_WAITCNT
     54 def HWVALU   : ProcResource<1>;
     55 
     56 }
     57 
     58 class HWWriteRes<SchedWrite write, list<ProcResourceKind> resources,
     59                  int latency> : WriteRes<write, resources> {
     60   let Latency = latency;
     61 }
     62 
     63 class HWVALUWriteRes<SchedWrite write, int latency> :
     64   HWWriteRes<write, [HWVALU], latency>;
     65 
     66 
     67 // The latency numbers are taken from AMD Accelerated Parallel Processing
     68 // guide. They may not be accurate.
     69 
     70 // The latency values are 1 / (operations / cycle) / 4.
     71 multiclass SICommonWriteRes {
     72 
     73   def : HWWriteRes<WriteBranch,  [HWBranch], 100>; // XXX: Guessed ???
     74   def : HWWriteRes<WriteExport,  [HWExport], 100>; // XXX: Guessed ???
     75   def : HWWriteRes<WriteLDS,     [HWLGKM],    32>; // 2 - 64
     76   def : HWWriteRes<WriteSALU,    [HWSALU],     1>;
     77   def : HWWriteRes<WriteSMEM,    [HWLGKM],    10>; // XXX: Guessed ???
     78   def : HWWriteRes<WriteVMEM,    [HWVMEM],   450>; // 300 - 600
     79   def : HWWriteRes<WriteBarrier, [HWBranch], 500>; // XXX: Guessed ???
     80 
     81   def : HWVALUWriteRes<Write32Bit,         1>;
     82   def : HWVALUWriteRes<Write64Bit,         2>;
     83   def : HWVALUWriteRes<WriteQuarterRate32, 4>;
     84 }
     85 
     86 
     87 let SchedModel = SIFullSpeedModel in {
     88 
     89 defm : SICommonWriteRes;
     90 
     91 def : HWVALUWriteRes<WriteFloatFMA,   1>;
     92 def : HWVALUWriteRes<WriteDouble,     4>;
     93 def : HWVALUWriteRes<WriteDoubleAdd,  2>;
     94 
     95 } // End SchedModel = SIFullSpeedModel
     96 
     97 let SchedModel = SIQuarterSpeedModel in {
     98 
     99 defm : SICommonWriteRes;
    100 
    101 def : HWVALUWriteRes<WriteFloatFMA, 16>;
    102 def : HWVALUWriteRes<WriteDouble,   16>;
    103 def : HWVALUWriteRes<WriteDoubleAdd, 8>;
    104 
    105 }  // End SchedModel = SIQuarterSpeedModel
    106