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      1 //===-- Hexagon.td - Describe the Hexagon Target Machine --*- tablegen -*--===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This is the top level entry point for the Hexagon target.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 //===----------------------------------------------------------------------===//
     15 // Target-independent interfaces which we are implementing
     16 //===----------------------------------------------------------------------===//
     17 
     18 include "llvm/Target/Target.td"
     19 
     20 //===----------------------------------------------------------------------===//
     21 // Hexagon Subtarget features.
     22 //===----------------------------------------------------------------------===//
     23 
     24 // Hexagon Architectures
     25 def ArchV4:  SubtargetFeature<"v4",  "HexagonArchVersion", "V4",  "Hexagon V4">;
     26 def ArchV5:  SubtargetFeature<"v5",  "HexagonArchVersion", "V5",  "Hexagon V5">;
     27 def ArchV55: SubtargetFeature<"v55", "HexagonArchVersion", "V55", "Hexagon V55">;
     28 def ArchV60: SubtargetFeature<"v60", "HexagonArchVersion", "V60", "Hexagon V60">;
     29 
     30 // Hexagon ISA Extensions
     31 def ExtensionHVX: SubtargetFeature<"hvx", "UseHVXOps",
     32                                    "true", "Hexagon HVX instructions">;
     33 def ExtensionHVXDbl: SubtargetFeature<"hvx-double", "UseHVXDblOps",
     34                                    "true", "Hexagon HVX Double instructions">;
     35 
     36 //===----------------------------------------------------------------------===//
     37 // Hexagon Instruction Predicate Definitions.
     38 //===----------------------------------------------------------------------===//
     39 def HasV5T             : Predicate<"HST->hasV5TOps()">;
     40 def NoV5T              : Predicate<"!HST->hasV5TOps()">;
     41 def HasV55T            : Predicate<"HST->hasV55TOps()">,
     42                          AssemblerPredicate<"ArchV55">;
     43 def HasV60T            : Predicate<"HST->hasV60TOps()">,
     44                          AssemblerPredicate<"ArchV60">;
     45 def UseMEMOP           : Predicate<"HST->useMemOps()">;
     46 def IEEERndNearV5T     : Predicate<"HST->modeIEEERndNear()">;
     47 def UseHVXDbl          : Predicate<"HST->useHVXDblOps()">,
     48                          AssemblerPredicate<"ExtensionHVXDbl">;
     49 def UseHVXSgl          : Predicate<"HST->useHVXSglOps()">;
     50 
     51 def UseHVX             : Predicate<"HST->useHVXSglOps() ||HST->useHVXDblOps()">,
     52                          AssemblerPredicate<"ExtensionHVX">;
     53 
     54 //===----------------------------------------------------------------------===//
     55 // Classes used for relation maps.
     56 //===----------------------------------------------------------------------===//
     57 
     58 class ImmRegShl;
     59 // PredRel - Filter class used to relate non-predicated instructions with their
     60 // predicated forms.
     61 class PredRel;
     62 // PredNewRel - Filter class used to relate predicated instructions with their
     63 // predicate-new forms.
     64 class PredNewRel: PredRel;
     65 // ImmRegRel - Filter class used to relate instructions having reg-reg form
     66 // with their reg-imm counterparts.
     67 class ImmRegRel;
     68 // NewValueRel - Filter class used to relate regular store instructions with
     69 // their new-value store form.
     70 class NewValueRel: PredNewRel;
     71 // NewValueRel - Filter class used to relate load/store instructions having
     72 // different addressing modes with each other.
     73 class AddrModeRel: NewValueRel;
     74 class IntrinsicsRel;
     75 
     76 //===----------------------------------------------------------------------===//
     77 // Generate mapping table to relate non-predicate instructions with their
     78 // predicated formats - true and false.
     79 //
     80 
     81 def getPredOpcode : InstrMapping {
     82   let FilterClass = "PredRel";
     83   // Instructions with the same BaseOpcode and isNVStore values form a row.
     84   let RowFields = ["BaseOpcode", "isNVStore", "PNewValue", "isNT"];
     85   // Instructions with the same predicate sense form a column.
     86   let ColFields = ["PredSense"];
     87   // The key column is the unpredicated instructions.
     88   let KeyCol = [""];
     89   // Value columns are PredSense=true and PredSense=false
     90   let ValueCols = [["true"], ["false"]];
     91 }
     92 
     93 //===----------------------------------------------------------------------===//
     94 // Generate mapping table to relate predicate-true instructions with their
     95 // predicate-false forms
     96 //
     97 def getFalsePredOpcode : InstrMapping {
     98   let FilterClass = "PredRel";
     99   let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];
    100   let ColFields = ["PredSense"];
    101   let KeyCol = ["true"];
    102   let ValueCols = [["false"]];
    103 }
    104 
    105 //===----------------------------------------------------------------------===//
    106 // Generate mapping table to relate predicate-false instructions with their
    107 // predicate-true forms
    108 //
    109 def getTruePredOpcode : InstrMapping {
    110   let FilterClass = "PredRel";
    111   let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];
    112   let ColFields = ["PredSense"];
    113   let KeyCol = ["false"];
    114   let ValueCols = [["true"]];
    115 }
    116 
    117 //===----------------------------------------------------------------------===//
    118 // Generate mapping table to relate predicated instructions with their .new
    119 // format.
    120 //
    121 def getPredNewOpcode : InstrMapping {
    122   let FilterClass = "PredNewRel";
    123   let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"];
    124   let ColFields = ["PNewValue"];
    125   let KeyCol = [""];
    126   let ValueCols = [["new"]];
    127 }
    128 
    129 //===----------------------------------------------------------------------===//
    130 // Generate mapping table to relate .new predicated instructions with their old
    131 // format.
    132 //
    133 def getPredOldOpcode : InstrMapping {
    134   let FilterClass = "PredNewRel";
    135   let RowFields = ["BaseOpcode", "PredSense", "isNVStore"];
    136   let ColFields = ["PNewValue"];
    137   let KeyCol = ["new"];
    138   let ValueCols = [[""]];
    139 }
    140 
    141 //===----------------------------------------------------------------------===//
    142 // Generate mapping table to relate store instructions with their new-value
    143 // format.
    144 //
    145 def getNewValueOpcode : InstrMapping {
    146   let FilterClass = "NewValueRel";
    147   let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
    148   let ColFields = ["NValueST"];
    149   let KeyCol = ["false"];
    150   let ValueCols = [["true"]];
    151 }
    152 
    153 //===----------------------------------------------------------------------===//
    154 // Generate mapping table to relate new-value store instructions with their old
    155 // format.
    156 //
    157 def getNonNVStore : InstrMapping {
    158   let FilterClass = "NewValueRel";
    159   let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
    160   let ColFields = ["NValueST"];
    161   let KeyCol = ["true"];
    162   let ValueCols = [["false"]];
    163 }
    164 
    165 def getBaseWithImmOffset : InstrMapping {
    166   let FilterClass = "AddrModeRel";
    167   let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore",
    168                    "isFloat"];
    169   let ColFields = ["addrMode"];
    170   let KeyCol = ["Absolute"];
    171   let ValueCols = [["BaseImmOffset"]];
    172 }
    173 
    174 def getBaseWithRegOffset : InstrMapping {
    175   let FilterClass = "AddrModeRel";
    176   let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
    177   let ColFields = ["addrMode"];
    178   let KeyCol = ["BaseImmOffset"];
    179   let ValueCols = [["BaseRegOffset"]];
    180 }
    181 
    182 def getRegForm : InstrMapping {
    183   let FilterClass = "ImmRegRel";
    184   let RowFields = ["CextOpcode", "PredSense", "PNewValue"];
    185   let ColFields = ["InputType"];
    186   let KeyCol = ["imm"];
    187   let ValueCols = [["reg"]];
    188 }
    189 
    190 def getRegShlForm : InstrMapping {
    191   let FilterClass = "ImmRegShl";
    192   let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
    193   let ColFields = ["InputType"];
    194   let KeyCol = ["imm"];
    195   let ValueCols = [["reg"]];
    196 }
    197 
    198 def notTakenBranchPrediction : InstrMapping {
    199   let FilterClass = "PredRel";
    200   let RowFields = ["BaseOpcode", "PNewValue",  "PredSense", "isBranch", "isPredicated"];
    201   let ColFields = ["isBrTaken"];
    202   let KeyCol = ["true"];
    203   let ValueCols = [["false"]];
    204 }
    205 
    206 def takenBranchPrediction : InstrMapping {
    207   let FilterClass = "PredRel";
    208   let RowFields = ["BaseOpcode", "PNewValue",  "PredSense", "isBranch", "isPredicated"];
    209   let ColFields = ["isBrTaken"];
    210   let KeyCol = ["false"];
    211   let ValueCols = [["true"]];
    212 }
    213 
    214 def getRealHWInstr : InstrMapping {
    215   let FilterClass = "IntrinsicsRel";
    216   let RowFields = ["BaseOpcode"];
    217   let ColFields = ["InstrType"];
    218   let KeyCol = ["Pseudo"];
    219   let ValueCols = [["Pseudo"], ["Real"]];
    220 }
    221 //===----------------------------------------------------------------------===//
    222 // Register File, Calling Conv, Instruction Descriptions
    223 //===----------------------------------------------------------------------===//
    224 include "HexagonSchedule.td"
    225 include "HexagonRegisterInfo.td"
    226 include "HexagonCallingConv.td"
    227 include "HexagonInstrInfo.td"
    228 include "HexagonIntrinsics.td"
    229 include "HexagonIntrinsicsDerived.td"
    230 
    231 def HexagonInstrInfo : InstrInfo;
    232 
    233 //===----------------------------------------------------------------------===//
    234 // Hexagon processors supported.
    235 //===----------------------------------------------------------------------===//
    236 
    237 class Proc<string Name, SchedMachineModel Model,
    238            list<SubtargetFeature> Features>
    239  : ProcessorModel<Name, Model, Features>;
    240 
    241 def : Proc<"hexagonv4",  HexagonModelV4,
    242            [ArchV4]>;
    243 def : Proc<"hexagonv5",  HexagonModelV4,
    244            [ArchV4, ArchV5]>;
    245 def : Proc<"hexagonv55", HexagonModelV55,
    246            [ArchV4, ArchV5, ArchV55]>;
    247 def : Proc<"hexagonv60", HexagonModelV60,
    248            [ArchV4, ArchV5, ArchV55, ArchV60, ExtensionHVX]>;
    249 
    250 //===----------------------------------------------------------------------===//
    251 // Declare the target which we are implementing
    252 //===----------------------------------------------------------------------===//
    253 
    254 def HexagonAsmParserVariant : AsmParserVariant {
    255   int Variant = 0;
    256   string TokenizingCharacters = "#()=:.<>!+*";
    257 }
    258 
    259 def Hexagon : Target {
    260   // Pull in Instruction Info:
    261   let InstructionSet = HexagonInstrInfo;
    262   let AssemblyParserVariants = [HexagonAsmParserVariant];
    263 }
    264