1 //===- MipsMSAInstrInfo.td - MSA ASE instructions -*- tablegen ------------*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes Mips MSA ASE instructions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 def SDT_MipsVecCond : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>]>; 15 def SDT_VSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>, 16 SDTCisInt<1>, 17 SDTCisSameAs<1, 2>, 18 SDTCisVT<3, OtherVT>]>; 19 def SDT_VFSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>, 20 SDTCisFP<1>, 21 SDTCisSameAs<1, 2>, 22 SDTCisVT<3, OtherVT>]>; 23 def SDT_VSHF : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisVec<0>, 24 SDTCisInt<1>, SDTCisVec<1>, 25 SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>]>; 26 def SDT_SHF : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>, 27 SDTCisVT<1, i32>, SDTCisSameAs<0, 2>]>; 28 def SDT_ILV : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>, 29 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>; 30 def SDT_INSVE : SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0, 1>, 31 SDTCisVT<2, i32>, SDTCisSameAs<0, 3>, 32 SDTCisVT<4, i32>]>; 33 34 def MipsVAllNonZero : SDNode<"MipsISD::VALL_NONZERO", SDT_MipsVecCond>; 35 def MipsVAnyNonZero : SDNode<"MipsISD::VANY_NONZERO", SDT_MipsVecCond>; 36 def MipsVAllZero : SDNode<"MipsISD::VALL_ZERO", SDT_MipsVecCond>; 37 def MipsVAnyZero : SDNode<"MipsISD::VANY_ZERO", SDT_MipsVecCond>; 38 def MipsVSMax : SDNode<"MipsISD::VSMAX", SDTIntBinOp, 39 [SDNPCommutative, SDNPAssociative]>; 40 def MipsVSMin : SDNode<"MipsISD::VSMIN", SDTIntBinOp, 41 [SDNPCommutative, SDNPAssociative]>; 42 def MipsVUMax : SDNode<"MipsISD::VUMAX", SDTIntBinOp, 43 [SDNPCommutative, SDNPAssociative]>; 44 def MipsVUMin : SDNode<"MipsISD::VUMIN", SDTIntBinOp, 45 [SDNPCommutative, SDNPAssociative]>; 46 def MipsVNOR : SDNode<"MipsISD::VNOR", SDTIntBinOp, 47 [SDNPCommutative, SDNPAssociative]>; 48 def MipsVSHF : SDNode<"MipsISD::VSHF", SDT_VSHF>; 49 def MipsSHF : SDNode<"MipsISD::SHF", SDT_SHF>; 50 def MipsILVEV : SDNode<"MipsISD::ILVEV", SDT_ILV>; 51 def MipsILVOD : SDNode<"MipsISD::ILVOD", SDT_ILV>; 52 def MipsILVL : SDNode<"MipsISD::ILVL", SDT_ILV>; 53 def MipsILVR : SDNode<"MipsISD::ILVR", SDT_ILV>; 54 def MipsPCKEV : SDNode<"MipsISD::PCKEV", SDT_ILV>; 55 def MipsPCKOD : SDNode<"MipsISD::PCKOD", SDT_ILV>; 56 def MipsINSVE : SDNode<"MipsISD::INSVE", SDT_INSVE>; 57 58 def vsetcc : SDNode<"ISD::SETCC", SDT_VSetCC>; 59 def vfsetcc : SDNode<"ISD::SETCC", SDT_VFSetCC>; 60 61 def MipsVExtractSExt : SDNode<"MipsISD::VEXTRACT_SEXT_ELT", 62 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>; 63 def MipsVExtractZExt : SDNode<"MipsISD::VEXTRACT_ZEXT_ELT", 64 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>; 65 66 def immZExt1Ptr : ImmLeaf<iPTR, [{return isUInt<1>(Imm);}]>; 67 def immZExt2Ptr : ImmLeaf<iPTR, [{return isUInt<2>(Imm);}]>; 68 def immZExt4Ptr : ImmLeaf<iPTR, [{return isUInt<4>(Imm);}]>; 69 def immZExt6Ptr : ImmLeaf<iPTR, [{return isUInt<6>(Imm);}]>; 70 71 // Operands 72 73 def uimm4_ptr : Operand<iPTR> { 74 let PrintMethod = "printUnsignedImm8"; 75 } 76 77 def uimm6_ptr : Operand<iPTR> { 78 let PrintMethod = "printUnsignedImm8"; 79 } 80 81 def simm5 : Operand<i32>; 82 83 def vsplat_uimm1 : Operand<vAny> { 84 let PrintMethod = "printUnsignedImm8"; 85 } 86 87 def vsplat_uimm2 : Operand<vAny> { 88 let PrintMethod = "printUnsignedImm8"; 89 } 90 91 def vsplat_uimm3 : Operand<vAny> { 92 let PrintMethod = "printUnsignedImm8"; 93 } 94 95 def vsplat_uimm4 : Operand<vAny> { 96 let PrintMethod = "printUnsignedImm8"; 97 } 98 99 def vsplat_uimm5 : Operand<vAny> { 100 let PrintMethod = "printUnsignedImm8"; 101 } 102 103 def vsplat_uimm6 : Operand<vAny> { 104 let PrintMethod = "printUnsignedImm8"; 105 } 106 107 def vsplat_uimm8 : Operand<vAny> { 108 let PrintMethod = "printUnsignedImm8"; 109 } 110 111 def vsplat_simm5 : Operand<vAny>; 112 113 def vsplat_simm10 : Operand<vAny>; 114 115 def immZExt2Lsa : ImmLeaf<i32, [{return isUInt<2>(Imm - 1);}]>; 116 117 // Pattern fragments 118 def vextract_sext_i8 : PatFrag<(ops node:$vec, node:$idx), 119 (MipsVExtractSExt node:$vec, node:$idx, i8)>; 120 def vextract_sext_i16 : PatFrag<(ops node:$vec, node:$idx), 121 (MipsVExtractSExt node:$vec, node:$idx, i16)>; 122 def vextract_sext_i32 : PatFrag<(ops node:$vec, node:$idx), 123 (MipsVExtractSExt node:$vec, node:$idx, i32)>; 124 def vextract_sext_i64 : PatFrag<(ops node:$vec, node:$idx), 125 (MipsVExtractSExt node:$vec, node:$idx, i64)>; 126 127 def vextract_zext_i8 : PatFrag<(ops node:$vec, node:$idx), 128 (MipsVExtractZExt node:$vec, node:$idx, i8)>; 129 def vextract_zext_i16 : PatFrag<(ops node:$vec, node:$idx), 130 (MipsVExtractZExt node:$vec, node:$idx, i16)>; 131 def vextract_zext_i32 : PatFrag<(ops node:$vec, node:$idx), 132 (MipsVExtractZExt node:$vec, node:$idx, i32)>; 133 def vextract_zext_i64 : PatFrag<(ops node:$vec, node:$idx), 134 (MipsVExtractZExt node:$vec, node:$idx, i64)>; 135 136 def vinsert_v16i8 : PatFrag<(ops node:$vec, node:$val, node:$idx), 137 (v16i8 (vector_insert node:$vec, node:$val, node:$idx))>; 138 def vinsert_v8i16 : PatFrag<(ops node:$vec, node:$val, node:$idx), 139 (v8i16 (vector_insert node:$vec, node:$val, node:$idx))>; 140 def vinsert_v4i32 : PatFrag<(ops node:$vec, node:$val, node:$idx), 141 (v4i32 (vector_insert node:$vec, node:$val, node:$idx))>; 142 def vinsert_v2i64 : PatFrag<(ops node:$vec, node:$val, node:$idx), 143 (v2i64 (vector_insert node:$vec, node:$val, node:$idx))>; 144 145 def insve_v16i8 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), 146 (v16i8 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; 147 def insve_v8i16 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), 148 (v8i16 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; 149 def insve_v4i32 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), 150 (v4i32 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; 151 def insve_v2i64 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), 152 (v2i64 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; 153 154 class vfsetcc_type<ValueType ResTy, ValueType OpTy, CondCode CC> : 155 PatFrag<(ops node:$lhs, node:$rhs), 156 (ResTy (vfsetcc (OpTy node:$lhs), (OpTy node:$rhs), CC))>; 157 158 // ISD::SETFALSE cannot occur 159 def vfsetoeq_v4f32 : vfsetcc_type<v4i32, v4f32, SETOEQ>; 160 def vfsetoeq_v2f64 : vfsetcc_type<v2i64, v2f64, SETOEQ>; 161 def vfsetoge_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGE>; 162 def vfsetoge_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGE>; 163 def vfsetogt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGT>; 164 def vfsetogt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGT>; 165 def vfsetole_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLE>; 166 def vfsetole_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLE>; 167 def vfsetolt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLT>; 168 def vfsetolt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLT>; 169 def vfsetone_v4f32 : vfsetcc_type<v4i32, v4f32, SETONE>; 170 def vfsetone_v2f64 : vfsetcc_type<v2i64, v2f64, SETONE>; 171 def vfsetord_v4f32 : vfsetcc_type<v4i32, v4f32, SETO>; 172 def vfsetord_v2f64 : vfsetcc_type<v2i64, v2f64, SETO>; 173 def vfsetun_v4f32 : vfsetcc_type<v4i32, v4f32, SETUO>; 174 def vfsetun_v2f64 : vfsetcc_type<v2i64, v2f64, SETUO>; 175 def vfsetueq_v4f32 : vfsetcc_type<v4i32, v4f32, SETUEQ>; 176 def vfsetueq_v2f64 : vfsetcc_type<v2i64, v2f64, SETUEQ>; 177 def vfsetuge_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGE>; 178 def vfsetuge_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGE>; 179 def vfsetugt_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGT>; 180 def vfsetugt_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGT>; 181 def vfsetule_v4f32 : vfsetcc_type<v4i32, v4f32, SETULE>; 182 def vfsetule_v2f64 : vfsetcc_type<v2i64, v2f64, SETULE>; 183 def vfsetult_v4f32 : vfsetcc_type<v4i32, v4f32, SETULT>; 184 def vfsetult_v2f64 : vfsetcc_type<v2i64, v2f64, SETULT>; 185 def vfsetune_v4f32 : vfsetcc_type<v4i32, v4f32, SETUNE>; 186 def vfsetune_v2f64 : vfsetcc_type<v2i64, v2f64, SETUNE>; 187 // ISD::SETTRUE cannot occur 188 // ISD::SETFALSE2 cannot occur 189 // ISD::SETTRUE2 cannot occur 190 191 class vsetcc_type<ValueType ResTy, CondCode CC> : 192 PatFrag<(ops node:$lhs, node:$rhs), 193 (ResTy (vsetcc node:$lhs, node:$rhs, CC))>; 194 195 def vseteq_v16i8 : vsetcc_type<v16i8, SETEQ>; 196 def vseteq_v8i16 : vsetcc_type<v8i16, SETEQ>; 197 def vseteq_v4i32 : vsetcc_type<v4i32, SETEQ>; 198 def vseteq_v2i64 : vsetcc_type<v2i64, SETEQ>; 199 def vsetle_v16i8 : vsetcc_type<v16i8, SETLE>; 200 def vsetle_v8i16 : vsetcc_type<v8i16, SETLE>; 201 def vsetle_v4i32 : vsetcc_type<v4i32, SETLE>; 202 def vsetle_v2i64 : vsetcc_type<v2i64, SETLE>; 203 def vsetlt_v16i8 : vsetcc_type<v16i8, SETLT>; 204 def vsetlt_v8i16 : vsetcc_type<v8i16, SETLT>; 205 def vsetlt_v4i32 : vsetcc_type<v4i32, SETLT>; 206 def vsetlt_v2i64 : vsetcc_type<v2i64, SETLT>; 207 def vsetule_v16i8 : vsetcc_type<v16i8, SETULE>; 208 def vsetule_v8i16 : vsetcc_type<v8i16, SETULE>; 209 def vsetule_v4i32 : vsetcc_type<v4i32, SETULE>; 210 def vsetule_v2i64 : vsetcc_type<v2i64, SETULE>; 211 def vsetult_v16i8 : vsetcc_type<v16i8, SETULT>; 212 def vsetult_v8i16 : vsetcc_type<v8i16, SETULT>; 213 def vsetult_v4i32 : vsetcc_type<v4i32, SETULT>; 214 def vsetult_v2i64 : vsetcc_type<v2i64, SETULT>; 215 216 def vsplati8 : PatFrag<(ops node:$e0), 217 (v16i8 (build_vector node:$e0, node:$e0, 218 node:$e0, node:$e0, 219 node:$e0, node:$e0, 220 node:$e0, node:$e0, 221 node:$e0, node:$e0, 222 node:$e0, node:$e0, 223 node:$e0, node:$e0, 224 node:$e0, node:$e0))>; 225 def vsplati16 : PatFrag<(ops node:$e0), 226 (v8i16 (build_vector node:$e0, node:$e0, 227 node:$e0, node:$e0, 228 node:$e0, node:$e0, 229 node:$e0, node:$e0))>; 230 def vsplati32 : PatFrag<(ops node:$e0), 231 (v4i32 (build_vector node:$e0, node:$e0, 232 node:$e0, node:$e0))>; 233 def vsplati64 : PatFrag<(ops node:$e0), 234 (v2i64 (build_vector node:$e0, node:$e0))>; 235 def vsplatf32 : PatFrag<(ops node:$e0), 236 (v4f32 (build_vector node:$e0, node:$e0, 237 node:$e0, node:$e0))>; 238 def vsplatf64 : PatFrag<(ops node:$e0), 239 (v2f64 (build_vector node:$e0, node:$e0))>; 240 241 def vsplati8_elt : PatFrag<(ops node:$v, node:$i), 242 (MipsVSHF (vsplati8 node:$i), node:$v, node:$v)>; 243 def vsplati16_elt : PatFrag<(ops node:$v, node:$i), 244 (MipsVSHF (vsplati16 node:$i), node:$v, node:$v)>; 245 def vsplati32_elt : PatFrag<(ops node:$v, node:$i), 246 (MipsVSHF (vsplati32 node:$i), node:$v, node:$v)>; 247 def vsplati64_elt : PatFrag<(ops node:$v, node:$i), 248 (MipsVSHF (vsplati64 node:$i), node:$v, node:$v)>; 249 250 class SplatPatLeaf<Operand opclass, dag frag, code pred = [{}], 251 SDNodeXForm xform = NOOP_SDNodeXForm> 252 : PatLeaf<frag, pred, xform> { 253 Operand OpClass = opclass; 254 } 255 256 class SplatComplexPattern<Operand opclass, ValueType ty, int numops, string fn, 257 list<SDNode> roots = [], 258 list<SDNodeProperty> props = []> : 259 ComplexPattern<ty, numops, fn, roots, props> { 260 Operand OpClass = opclass; 261 } 262 263 def vsplati8_uimm3 : SplatComplexPattern<vsplat_uimm3, v16i8, 1, 264 "selectVSplatUimm3", 265 [build_vector, bitconvert]>; 266 267 def vsplati8_uimm4 : SplatComplexPattern<vsplat_uimm4, v16i8, 1, 268 "selectVSplatUimm4", 269 [build_vector, bitconvert]>; 270 271 def vsplati8_uimm5 : SplatComplexPattern<vsplat_uimm5, v16i8, 1, 272 "selectVSplatUimm5", 273 [build_vector, bitconvert]>; 274 275 def vsplati8_uimm8 : SplatComplexPattern<vsplat_uimm8, v16i8, 1, 276 "selectVSplatUimm8", 277 [build_vector, bitconvert]>; 278 279 def vsplati8_simm5 : SplatComplexPattern<vsplat_simm5, v16i8, 1, 280 "selectVSplatSimm5", 281 [build_vector, bitconvert]>; 282 283 def vsplati16_uimm3 : SplatComplexPattern<vsplat_uimm3, v8i16, 1, 284 "selectVSplatUimm3", 285 [build_vector, bitconvert]>; 286 287 def vsplati16_uimm4 : SplatComplexPattern<vsplat_uimm4, v8i16, 1, 288 "selectVSplatUimm4", 289 [build_vector, bitconvert]>; 290 291 def vsplati16_uimm5 : SplatComplexPattern<vsplat_uimm5, v8i16, 1, 292 "selectVSplatUimm5", 293 [build_vector, bitconvert]>; 294 295 def vsplati16_simm5 : SplatComplexPattern<vsplat_simm5, v8i16, 1, 296 "selectVSplatSimm5", 297 [build_vector, bitconvert]>; 298 299 def vsplati32_uimm2 : SplatComplexPattern<vsplat_uimm2, v4i32, 1, 300 "selectVSplatUimm2", 301 [build_vector, bitconvert]>; 302 303 def vsplati32_uimm5 : SplatComplexPattern<vsplat_uimm5, v4i32, 1, 304 "selectVSplatUimm5", 305 [build_vector, bitconvert]>; 306 307 def vsplati32_simm5 : SplatComplexPattern<vsplat_simm5, v4i32, 1, 308 "selectVSplatSimm5", 309 [build_vector, bitconvert]>; 310 311 def vsplati64_uimm1 : SplatComplexPattern<vsplat_uimm1, v2i64, 1, 312 "selectVSplatUimm1", 313 [build_vector, bitconvert]>; 314 315 def vsplati64_uimm5 : SplatComplexPattern<vsplat_uimm5, v2i64, 1, 316 "selectVSplatUimm5", 317 [build_vector, bitconvert]>; 318 319 def vsplati64_uimm6 : SplatComplexPattern<vsplat_uimm6, v2i64, 1, 320 "selectVSplatUimm6", 321 [build_vector, bitconvert]>; 322 323 def vsplati64_simm5 : SplatComplexPattern<vsplat_simm5, v2i64, 1, 324 "selectVSplatSimm5", 325 [build_vector, bitconvert]>; 326 327 // Any build_vector that is a constant splat with a value that is an exact 328 // power of 2 329 def vsplat_uimm_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmPow2", 330 [build_vector, bitconvert]>; 331 332 // Any build_vector that is a constant splat with a value that is the bitwise 333 // inverse of an exact power of 2 334 def vsplat_uimm_inv_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmInvPow2", 335 [build_vector, bitconvert]>; 336 337 // Any build_vector that is a constant splat with only a consecutive sequence 338 // of left-most bits set. 339 def vsplat_maskl_bits : SplatComplexPattern<vsplat_uimm8, vAny, 1, 340 "selectVSplatMaskL", 341 [build_vector, bitconvert]>; 342 343 // Any build_vector that is a constant splat with only a consecutive sequence 344 // of right-most bits set. 345 def vsplat_maskr_bits : SplatComplexPattern<vsplat_uimm8, vAny, 1, 346 "selectVSplatMaskR", 347 [build_vector, bitconvert]>; 348 349 // Any build_vector that is a constant splat with a value that equals 1 350 // FIXME: These should be a ComplexPattern but we can't use them because the 351 // ISel generator requires the uses to have a name, but providing a name 352 // causes other errors ("used in pattern but not operand list") 353 def vsplat_imm_eq_1 : PatLeaf<(build_vector), [{ 354 APInt Imm; 355 EVT EltTy = N->getValueType(0).getVectorElementType(); 356 357 return selectVSplat(N, Imm, EltTy.getSizeInBits()) && 358 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1; 359 }]>; 360 361 def vsplati64_imm_eq_1 : PatLeaf<(bitconvert (v4i32 (build_vector))), [{ 362 APInt Imm; 363 SDNode *BV = N->getOperand(0).getNode(); 364 EVT EltTy = N->getValueType(0).getVectorElementType(); 365 366 return selectVSplat(BV, Imm, EltTy.getSizeInBits()) && 367 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1; 368 }]>; 369 370 def vbclr_b : PatFrag<(ops node:$ws, node:$wt), 371 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt), 372 immAllOnesV))>; 373 def vbclr_h : PatFrag<(ops node:$ws, node:$wt), 374 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt), 375 immAllOnesV))>; 376 def vbclr_w : PatFrag<(ops node:$ws, node:$wt), 377 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt), 378 immAllOnesV))>; 379 def vbclr_d : PatFrag<(ops node:$ws, node:$wt), 380 (and node:$ws, (xor (shl (v2i64 vsplati64_imm_eq_1), 381 node:$wt), 382 (bitconvert (v4i32 immAllOnesV))))>; 383 384 def vbneg_b : PatFrag<(ops node:$ws, node:$wt), 385 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 386 def vbneg_h : PatFrag<(ops node:$ws, node:$wt), 387 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 388 def vbneg_w : PatFrag<(ops node:$ws, node:$wt), 389 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 390 def vbneg_d : PatFrag<(ops node:$ws, node:$wt), 391 (xor node:$ws, (shl (v2i64 vsplati64_imm_eq_1), 392 node:$wt))>; 393 394 def vbset_b : PatFrag<(ops node:$ws, node:$wt), 395 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 396 def vbset_h : PatFrag<(ops node:$ws, node:$wt), 397 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 398 def vbset_w : PatFrag<(ops node:$ws, node:$wt), 399 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 400 def vbset_d : PatFrag<(ops node:$ws, node:$wt), 401 (or node:$ws, (shl (v2i64 vsplati64_imm_eq_1), 402 node:$wt))>; 403 404 def fms : PatFrag<(ops node:$wd, node:$ws, node:$wt), 405 (fsub node:$wd, (fmul node:$ws, node:$wt))>; 406 407 def muladd : PatFrag<(ops node:$wd, node:$ws, node:$wt), 408 (add node:$wd, (mul node:$ws, node:$wt))>; 409 410 def mulsub : PatFrag<(ops node:$wd, node:$ws, node:$wt), 411 (sub node:$wd, (mul node:$ws, node:$wt))>; 412 413 def mul_fexp2 : PatFrag<(ops node:$ws, node:$wt), 414 (fmul node:$ws, (fexp2 node:$wt))>; 415 416 // Immediates 417 def immSExt5 : ImmLeaf<i32, [{return isInt<5>(Imm);}]>; 418 def immSExt10: ImmLeaf<i32, [{return isInt<10>(Imm);}]>; 419 420 // Instruction encoding. 421 class ADD_A_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010000>; 422 class ADD_A_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010000>; 423 class ADD_A_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010000>; 424 class ADD_A_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010000>; 425 426 class ADDS_A_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010000>; 427 class ADDS_A_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010000>; 428 class ADDS_A_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010000>; 429 class ADDS_A_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010000>; 430 431 class ADDS_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010000>; 432 class ADDS_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010000>; 433 class ADDS_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010000>; 434 class ADDS_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010000>; 435 436 class ADDS_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010000>; 437 class ADDS_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010000>; 438 class ADDS_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010000>; 439 class ADDS_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010000>; 440 441 class ADDV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001110>; 442 class ADDV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001110>; 443 class ADDV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001110>; 444 class ADDV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001110>; 445 446 class ADDVI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000110>; 447 class ADDVI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000110>; 448 class ADDVI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000110>; 449 class ADDVI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000110>; 450 451 class AND_V_ENC : MSA_VEC_FMT<0b00000, 0b011110>; 452 453 class ANDI_B_ENC : MSA_I8_FMT<0b00, 0b000000>; 454 455 class ASUB_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010001>; 456 class ASUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010001>; 457 class ASUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010001>; 458 class ASUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010001>; 459 460 class ASUB_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010001>; 461 class ASUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010001>; 462 class ASUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010001>; 463 class ASUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010001>; 464 465 class AVE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010000>; 466 class AVE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010000>; 467 class AVE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010000>; 468 class AVE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010000>; 469 470 class AVE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010000>; 471 class AVE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010000>; 472 class AVE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010000>; 473 class AVE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010000>; 474 475 class AVER_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010000>; 476 class AVER_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010000>; 477 class AVER_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010000>; 478 class AVER_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010000>; 479 480 class AVER_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010000>; 481 class AVER_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010000>; 482 class AVER_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010000>; 483 class AVER_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010000>; 484 485 class BCLR_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001101>; 486 class BCLR_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001101>; 487 class BCLR_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001101>; 488 class BCLR_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001101>; 489 490 class BCLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001001>; 491 class BCLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001001>; 492 class BCLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001001>; 493 class BCLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001001>; 494 495 class BINSL_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001101>; 496 class BINSL_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001101>; 497 class BINSL_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001101>; 498 class BINSL_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001101>; 499 500 class BINSLI_B_ENC : MSA_BIT_B_FMT<0b110, 0b001001>; 501 class BINSLI_H_ENC : MSA_BIT_H_FMT<0b110, 0b001001>; 502 class BINSLI_W_ENC : MSA_BIT_W_FMT<0b110, 0b001001>; 503 class BINSLI_D_ENC : MSA_BIT_D_FMT<0b110, 0b001001>; 504 505 class BINSR_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001101>; 506 class BINSR_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001101>; 507 class BINSR_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001101>; 508 class BINSR_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001101>; 509 510 class BINSRI_B_ENC : MSA_BIT_B_FMT<0b111, 0b001001>; 511 class BINSRI_H_ENC : MSA_BIT_H_FMT<0b111, 0b001001>; 512 class BINSRI_W_ENC : MSA_BIT_W_FMT<0b111, 0b001001>; 513 class BINSRI_D_ENC : MSA_BIT_D_FMT<0b111, 0b001001>; 514 515 class BMNZ_V_ENC : MSA_VEC_FMT<0b00100, 0b011110>; 516 517 class BMNZI_B_ENC : MSA_I8_FMT<0b00, 0b000001>; 518 519 class BMZ_V_ENC : MSA_VEC_FMT<0b00101, 0b011110>; 520 521 class BMZI_B_ENC : MSA_I8_FMT<0b01, 0b000001>; 522 523 class BNEG_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001101>; 524 class BNEG_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001101>; 525 class BNEG_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001101>; 526 class BNEG_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001101>; 527 528 class BNEGI_B_ENC : MSA_BIT_B_FMT<0b101, 0b001001>; 529 class BNEGI_H_ENC : MSA_BIT_H_FMT<0b101, 0b001001>; 530 class BNEGI_W_ENC : MSA_BIT_W_FMT<0b101, 0b001001>; 531 class BNEGI_D_ENC : MSA_BIT_D_FMT<0b101, 0b001001>; 532 533 class BNZ_B_ENC : MSA_CBRANCH_FMT<0b111, 0b00>; 534 class BNZ_H_ENC : MSA_CBRANCH_FMT<0b111, 0b01>; 535 class BNZ_W_ENC : MSA_CBRANCH_FMT<0b111, 0b10>; 536 class BNZ_D_ENC : MSA_CBRANCH_FMT<0b111, 0b11>; 537 538 class BNZ_V_ENC : MSA_CBRANCH_V_FMT<0b01111>; 539 540 class BSEL_V_ENC : MSA_VEC_FMT<0b00110, 0b011110>; 541 542 class BSELI_B_ENC : MSA_I8_FMT<0b10, 0b000001>; 543 544 class BSET_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001101>; 545 class BSET_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001101>; 546 class BSET_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001101>; 547 class BSET_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001101>; 548 549 class BSETI_B_ENC : MSA_BIT_B_FMT<0b100, 0b001001>; 550 class BSETI_H_ENC : MSA_BIT_H_FMT<0b100, 0b001001>; 551 class BSETI_W_ENC : MSA_BIT_W_FMT<0b100, 0b001001>; 552 class BSETI_D_ENC : MSA_BIT_D_FMT<0b100, 0b001001>; 553 554 class BZ_B_ENC : MSA_CBRANCH_FMT<0b110, 0b00>; 555 class BZ_H_ENC : MSA_CBRANCH_FMT<0b110, 0b01>; 556 class BZ_W_ENC : MSA_CBRANCH_FMT<0b110, 0b10>; 557 class BZ_D_ENC : MSA_CBRANCH_FMT<0b110, 0b11>; 558 559 class BZ_V_ENC : MSA_CBRANCH_V_FMT<0b01011>; 560 561 class CEQ_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001111>; 562 class CEQ_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001111>; 563 class CEQ_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001111>; 564 class CEQ_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001111>; 565 566 class CEQI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000111>; 567 class CEQI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000111>; 568 class CEQI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000111>; 569 class CEQI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000111>; 570 571 class CFCMSA_ENC : MSA_ELM_CFCMSA_FMT<0b0001111110, 0b011001>; 572 573 class CLE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001111>; 574 class CLE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001111>; 575 class CLE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001111>; 576 class CLE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001111>; 577 578 class CLE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001111>; 579 class CLE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001111>; 580 class CLE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001111>; 581 class CLE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001111>; 582 583 class CLEI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000111>; 584 class CLEI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000111>; 585 class CLEI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000111>; 586 class CLEI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000111>; 587 588 class CLEI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000111>; 589 class CLEI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000111>; 590 class CLEI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000111>; 591 class CLEI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000111>; 592 593 class CLT_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001111>; 594 class CLT_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001111>; 595 class CLT_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001111>; 596 class CLT_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001111>; 597 598 class CLT_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001111>; 599 class CLT_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001111>; 600 class CLT_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001111>; 601 class CLT_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001111>; 602 603 class CLTI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000111>; 604 class CLTI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000111>; 605 class CLTI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000111>; 606 class CLTI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000111>; 607 608 class CLTI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000111>; 609 class CLTI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000111>; 610 class CLTI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000111>; 611 class CLTI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000111>; 612 613 class COPY_S_B_ENC : MSA_ELM_COPY_B_FMT<0b0010, 0b011001>; 614 class COPY_S_H_ENC : MSA_ELM_COPY_H_FMT<0b0010, 0b011001>; 615 class COPY_S_W_ENC : MSA_ELM_COPY_W_FMT<0b0010, 0b011001>; 616 class COPY_S_D_ENC : MSA_ELM_COPY_D_FMT<0b0010, 0b011001>; 617 618 class COPY_U_B_ENC : MSA_ELM_COPY_B_FMT<0b0011, 0b011001>; 619 class COPY_U_H_ENC : MSA_ELM_COPY_H_FMT<0b0011, 0b011001>; 620 class COPY_U_W_ENC : MSA_ELM_COPY_W_FMT<0b0011, 0b011001>; 621 622 class CTCMSA_ENC : MSA_ELM_CTCMSA_FMT<0b0000111110, 0b011001>; 623 624 class DIV_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010010>; 625 class DIV_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010010>; 626 class DIV_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010010>; 627 class DIV_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010010>; 628 629 class DIV_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010010>; 630 class DIV_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010010>; 631 class DIV_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010010>; 632 class DIV_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010010>; 633 634 class DOTP_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010011>; 635 class DOTP_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010011>; 636 class DOTP_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010011>; 637 638 class DOTP_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010011>; 639 class DOTP_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010011>; 640 class DOTP_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010011>; 641 642 class DPADD_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010011>; 643 class DPADD_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010011>; 644 class DPADD_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010011>; 645 646 class DPADD_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010011>; 647 class DPADD_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010011>; 648 class DPADD_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010011>; 649 650 class DPSUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010011>; 651 class DPSUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010011>; 652 class DPSUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010011>; 653 654 class DPSUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010011>; 655 class DPSUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010011>; 656 class DPSUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010011>; 657 658 class FADD_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011011>; 659 class FADD_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011011>; 660 661 class FCAF_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011010>; 662 class FCAF_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011010>; 663 664 class FCEQ_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011010>; 665 class FCEQ_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011010>; 666 667 class FCLASS_W_ENC : MSA_2RF_FMT<0b110010000, 0b0, 0b011110>; 668 class FCLASS_D_ENC : MSA_2RF_FMT<0b110010000, 0b1, 0b011110>; 669 670 class FCLE_W_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011010>; 671 class FCLE_D_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011010>; 672 673 class FCLT_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011010>; 674 class FCLT_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011010>; 675 676 class FCNE_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011100>; 677 class FCNE_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011100>; 678 679 class FCOR_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011100>; 680 class FCOR_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011100>; 681 682 class FCUEQ_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011010>; 683 class FCUEQ_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011010>; 684 685 class FCULE_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011010>; 686 class FCULE_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011010>; 687 688 class FCULT_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011010>; 689 class FCULT_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011010>; 690 691 class FCUN_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011010>; 692 class FCUN_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011010>; 693 694 class FCUNE_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011100>; 695 class FCUNE_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011100>; 696 697 class FDIV_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011011>; 698 class FDIV_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011011>; 699 700 class FEXDO_H_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011011>; 701 class FEXDO_W_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011011>; 702 703 class FEXP2_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011011>; 704 class FEXP2_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011011>; 705 706 class FEXUPL_W_ENC : MSA_2RF_FMT<0b110011000, 0b0, 0b011110>; 707 class FEXUPL_D_ENC : MSA_2RF_FMT<0b110011000, 0b1, 0b011110>; 708 709 class FEXUPR_W_ENC : MSA_2RF_FMT<0b110011001, 0b0, 0b011110>; 710 class FEXUPR_D_ENC : MSA_2RF_FMT<0b110011001, 0b1, 0b011110>; 711 712 class FFINT_S_W_ENC : MSA_2RF_FMT<0b110011110, 0b0, 0b011110>; 713 class FFINT_S_D_ENC : MSA_2RF_FMT<0b110011110, 0b1, 0b011110>; 714 715 class FFINT_U_W_ENC : MSA_2RF_FMT<0b110011111, 0b0, 0b011110>; 716 class FFINT_U_D_ENC : MSA_2RF_FMT<0b110011111, 0b1, 0b011110>; 717 718 class FFQL_W_ENC : MSA_2RF_FMT<0b110011010, 0b0, 0b011110>; 719 class FFQL_D_ENC : MSA_2RF_FMT<0b110011010, 0b1, 0b011110>; 720 721 class FFQR_W_ENC : MSA_2RF_FMT<0b110011011, 0b0, 0b011110>; 722 class FFQR_D_ENC : MSA_2RF_FMT<0b110011011, 0b1, 0b011110>; 723 724 class FILL_B_ENC : MSA_2R_FILL_FMT<0b11000000, 0b00, 0b011110>; 725 class FILL_H_ENC : MSA_2R_FILL_FMT<0b11000000, 0b01, 0b011110>; 726 class FILL_W_ENC : MSA_2R_FILL_FMT<0b11000000, 0b10, 0b011110>; 727 class FILL_D_ENC : MSA_2R_FILL_D_FMT<0b11000000, 0b11, 0b011110>; 728 729 class FLOG2_W_ENC : MSA_2RF_FMT<0b110010111, 0b0, 0b011110>; 730 class FLOG2_D_ENC : MSA_2RF_FMT<0b110010111, 0b1, 0b011110>; 731 732 class FMADD_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011011>; 733 class FMADD_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011011>; 734 735 class FMAX_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011011>; 736 class FMAX_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011011>; 737 738 class FMAX_A_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011011>; 739 class FMAX_A_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011011>; 740 741 class FMIN_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011011>; 742 class FMIN_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011011>; 743 744 class FMIN_A_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011011>; 745 class FMIN_A_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011011>; 746 747 class FMSUB_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011011>; 748 class FMSUB_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011011>; 749 750 class FMUL_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011011>; 751 class FMUL_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011011>; 752 753 class FRINT_W_ENC : MSA_2RF_FMT<0b110010110, 0b0, 0b011110>; 754 class FRINT_D_ENC : MSA_2RF_FMT<0b110010110, 0b1, 0b011110>; 755 756 class FRCP_W_ENC : MSA_2RF_FMT<0b110010101, 0b0, 0b011110>; 757 class FRCP_D_ENC : MSA_2RF_FMT<0b110010101, 0b1, 0b011110>; 758 759 class FRSQRT_W_ENC : MSA_2RF_FMT<0b110010100, 0b0, 0b011110>; 760 class FRSQRT_D_ENC : MSA_2RF_FMT<0b110010100, 0b1, 0b011110>; 761 762 class FSAF_W_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011010>; 763 class FSAF_D_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011010>; 764 765 class FSEQ_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011010>; 766 class FSEQ_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011010>; 767 768 class FSLE_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011010>; 769 class FSLE_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011010>; 770 771 class FSLT_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011010>; 772 class FSLT_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011010>; 773 774 class FSNE_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011100>; 775 class FSNE_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011100>; 776 777 class FSOR_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011100>; 778 class FSOR_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011100>; 779 780 class FSQRT_W_ENC : MSA_2RF_FMT<0b110010011, 0b0, 0b011110>; 781 class FSQRT_D_ENC : MSA_2RF_FMT<0b110010011, 0b1, 0b011110>; 782 783 class FSUB_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011011>; 784 class FSUB_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011011>; 785 786 class FSUEQ_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011010>; 787 class FSUEQ_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011010>; 788 789 class FSULE_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011010>; 790 class FSULE_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011010>; 791 792 class FSULT_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011010>; 793 class FSULT_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011010>; 794 795 class FSUN_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011010>; 796 class FSUN_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011010>; 797 798 class FSUNE_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011100>; 799 class FSUNE_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011100>; 800 801 class FTINT_S_W_ENC : MSA_2RF_FMT<0b110011100, 0b0, 0b011110>; 802 class FTINT_S_D_ENC : MSA_2RF_FMT<0b110011100, 0b1, 0b011110>; 803 804 class FTINT_U_W_ENC : MSA_2RF_FMT<0b110011101, 0b0, 0b011110>; 805 class FTINT_U_D_ENC : MSA_2RF_FMT<0b110011101, 0b1, 0b011110>; 806 807 class FTQ_H_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011011>; 808 class FTQ_W_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011011>; 809 810 class FTRUNC_S_W_ENC : MSA_2RF_FMT<0b110010001, 0b0, 0b011110>; 811 class FTRUNC_S_D_ENC : MSA_2RF_FMT<0b110010001, 0b1, 0b011110>; 812 813 class FTRUNC_U_W_ENC : MSA_2RF_FMT<0b110010010, 0b0, 0b011110>; 814 class FTRUNC_U_D_ENC : MSA_2RF_FMT<0b110010010, 0b1, 0b011110>; 815 816 class HADD_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010101>; 817 class HADD_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010101>; 818 class HADD_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010101>; 819 820 class HADD_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010101>; 821 class HADD_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010101>; 822 class HADD_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010101>; 823 824 class HSUB_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010101>; 825 class HSUB_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010101>; 826 class HSUB_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010101>; 827 828 class HSUB_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010101>; 829 class HSUB_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010101>; 830 class HSUB_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010101>; 831 832 class ILVEV_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010100>; 833 class ILVEV_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010100>; 834 class ILVEV_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010100>; 835 class ILVEV_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010100>; 836 837 class ILVL_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010100>; 838 class ILVL_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010100>; 839 class ILVL_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010100>; 840 class ILVL_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010100>; 841 842 class ILVOD_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010100>; 843 class ILVOD_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010100>; 844 class ILVOD_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010100>; 845 class ILVOD_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010100>; 846 847 class ILVR_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010100>; 848 class ILVR_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010100>; 849 class ILVR_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010100>; 850 class ILVR_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010100>; 851 852 class INSERT_B_ENC : MSA_ELM_INSERT_B_FMT<0b0100, 0b011001>; 853 class INSERT_H_ENC : MSA_ELM_INSERT_H_FMT<0b0100, 0b011001>; 854 class INSERT_W_ENC : MSA_ELM_INSERT_W_FMT<0b0100, 0b011001>; 855 class INSERT_D_ENC : MSA_ELM_INSERT_D_FMT<0b0100, 0b011001>; 856 857 class INSVE_B_ENC : MSA_ELM_B_FMT<0b0101, 0b011001>; 858 class INSVE_H_ENC : MSA_ELM_H_FMT<0b0101, 0b011001>; 859 class INSVE_W_ENC : MSA_ELM_W_FMT<0b0101, 0b011001>; 860 class INSVE_D_ENC : MSA_ELM_D_FMT<0b0101, 0b011001>; 861 862 class LD_B_ENC : MSA_MI10_FMT<0b00, 0b1000>; 863 class LD_H_ENC : MSA_MI10_FMT<0b01, 0b1000>; 864 class LD_W_ENC : MSA_MI10_FMT<0b10, 0b1000>; 865 class LD_D_ENC : MSA_MI10_FMT<0b11, 0b1000>; 866 867 class LDI_B_ENC : MSA_I10_FMT<0b110, 0b00, 0b000111>; 868 class LDI_H_ENC : MSA_I10_FMT<0b110, 0b01, 0b000111>; 869 class LDI_W_ENC : MSA_I10_FMT<0b110, 0b10, 0b000111>; 870 class LDI_D_ENC : MSA_I10_FMT<0b110, 0b11, 0b000111>; 871 872 class LSA_ENC : SPECIAL_LSA_FMT<0b000101>; 873 class DLSA_ENC : SPECIAL_DLSA_FMT<0b010101>; 874 875 class MADD_Q_H_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011100>; 876 class MADD_Q_W_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011100>; 877 878 class MADDR_Q_H_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011100>; 879 class MADDR_Q_W_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011100>; 880 881 class MADDV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010010>; 882 class MADDV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010010>; 883 class MADDV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010010>; 884 class MADDV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010010>; 885 886 class MAX_A_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001110>; 887 class MAX_A_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001110>; 888 class MAX_A_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001110>; 889 class MAX_A_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001110>; 890 891 class MAX_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001110>; 892 class MAX_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001110>; 893 class MAX_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001110>; 894 class MAX_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001110>; 895 896 class MAX_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001110>; 897 class MAX_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001110>; 898 class MAX_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001110>; 899 class MAX_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001110>; 900 901 class MAXI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000110>; 902 class MAXI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000110>; 903 class MAXI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000110>; 904 class MAXI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000110>; 905 906 class MAXI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000110>; 907 class MAXI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000110>; 908 class MAXI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000110>; 909 class MAXI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000110>; 910 911 class MIN_A_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001110>; 912 class MIN_A_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001110>; 913 class MIN_A_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001110>; 914 class MIN_A_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001110>; 915 916 class MIN_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001110>; 917 class MIN_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001110>; 918 class MIN_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001110>; 919 class MIN_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001110>; 920 921 class MIN_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001110>; 922 class MIN_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001110>; 923 class MIN_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001110>; 924 class MIN_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001110>; 925 926 class MINI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000110>; 927 class MINI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000110>; 928 class MINI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000110>; 929 class MINI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000110>; 930 931 class MINI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000110>; 932 class MINI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000110>; 933 class MINI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000110>; 934 class MINI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000110>; 935 936 class MOD_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010010>; 937 class MOD_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010010>; 938 class MOD_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010010>; 939 class MOD_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010010>; 940 941 class MOD_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010010>; 942 class MOD_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010010>; 943 class MOD_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010010>; 944 class MOD_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010010>; 945 946 class MOVE_V_ENC : MSA_ELM_FMT<0b0010111110, 0b011001>; 947 948 class MSUB_Q_H_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011100>; 949 class MSUB_Q_W_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011100>; 950 951 class MSUBR_Q_H_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011100>; 952 class MSUBR_Q_W_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011100>; 953 954 class MSUBV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010010>; 955 class MSUBV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010010>; 956 class MSUBV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010010>; 957 class MSUBV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010010>; 958 959 class MUL_Q_H_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011100>; 960 class MUL_Q_W_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011100>; 961 962 class MULR_Q_H_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011100>; 963 class MULR_Q_W_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011100>; 964 965 class MULV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010010>; 966 class MULV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010010>; 967 class MULV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010010>; 968 class MULV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010010>; 969 970 class NLOC_B_ENC : MSA_2R_FMT<0b11000010, 0b00, 0b011110>; 971 class NLOC_H_ENC : MSA_2R_FMT<0b11000010, 0b01, 0b011110>; 972 class NLOC_W_ENC : MSA_2R_FMT<0b11000010, 0b10, 0b011110>; 973 class NLOC_D_ENC : MSA_2R_FMT<0b11000010, 0b11, 0b011110>; 974 975 class NLZC_B_ENC : MSA_2R_FMT<0b11000011, 0b00, 0b011110>; 976 class NLZC_H_ENC : MSA_2R_FMT<0b11000011, 0b01, 0b011110>; 977 class NLZC_W_ENC : MSA_2R_FMT<0b11000011, 0b10, 0b011110>; 978 class NLZC_D_ENC : MSA_2R_FMT<0b11000011, 0b11, 0b011110>; 979 980 class NOR_V_ENC : MSA_VEC_FMT<0b00010, 0b011110>; 981 982 class NORI_B_ENC : MSA_I8_FMT<0b10, 0b000000>; 983 984 class OR_V_ENC : MSA_VEC_FMT<0b00001, 0b011110>; 985 986 class ORI_B_ENC : MSA_I8_FMT<0b01, 0b000000>; 987 988 class PCKEV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010100>; 989 class PCKEV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010100>; 990 class PCKEV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010100>; 991 class PCKEV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010100>; 992 993 class PCKOD_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010100>; 994 class PCKOD_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010100>; 995 class PCKOD_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010100>; 996 class PCKOD_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010100>; 997 998 class PCNT_B_ENC : MSA_2R_FMT<0b11000001, 0b00, 0b011110>; 999 class PCNT_H_ENC : MSA_2R_FMT<0b11000001, 0b01, 0b011110>; 1000 class PCNT_W_ENC : MSA_2R_FMT<0b11000001, 0b10, 0b011110>; 1001 class PCNT_D_ENC : MSA_2R_FMT<0b11000001, 0b11, 0b011110>; 1002 1003 class SAT_S_B_ENC : MSA_BIT_B_FMT<0b000, 0b001010>; 1004 class SAT_S_H_ENC : MSA_BIT_H_FMT<0b000, 0b001010>; 1005 class SAT_S_W_ENC : MSA_BIT_W_FMT<0b000, 0b001010>; 1006 class SAT_S_D_ENC : MSA_BIT_D_FMT<0b000, 0b001010>; 1007 1008 class SAT_U_B_ENC : MSA_BIT_B_FMT<0b001, 0b001010>; 1009 class SAT_U_H_ENC : MSA_BIT_H_FMT<0b001, 0b001010>; 1010 class SAT_U_W_ENC : MSA_BIT_W_FMT<0b001, 0b001010>; 1011 class SAT_U_D_ENC : MSA_BIT_D_FMT<0b001, 0b001010>; 1012 1013 class SHF_B_ENC : MSA_I8_FMT<0b00, 0b000010>; 1014 class SHF_H_ENC : MSA_I8_FMT<0b01, 0b000010>; 1015 class SHF_W_ENC : MSA_I8_FMT<0b10, 0b000010>; 1016 1017 class SLD_B_ENC : MSA_3R_INDEX_FMT<0b000, 0b00, 0b010100>; 1018 class SLD_H_ENC : MSA_3R_INDEX_FMT<0b000, 0b01, 0b010100>; 1019 class SLD_W_ENC : MSA_3R_INDEX_FMT<0b000, 0b10, 0b010100>; 1020 class SLD_D_ENC : MSA_3R_INDEX_FMT<0b000, 0b11, 0b010100>; 1021 1022 class SLDI_B_ENC : MSA_ELM_B_FMT<0b0000, 0b011001>; 1023 class SLDI_H_ENC : MSA_ELM_H_FMT<0b0000, 0b011001>; 1024 class SLDI_W_ENC : MSA_ELM_W_FMT<0b0000, 0b011001>; 1025 class SLDI_D_ENC : MSA_ELM_D_FMT<0b0000, 0b011001>; 1026 1027 class SLL_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001101>; 1028 class SLL_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001101>; 1029 class SLL_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001101>; 1030 class SLL_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001101>; 1031 1032 class SLLI_B_ENC : MSA_BIT_B_FMT<0b000, 0b001001>; 1033 class SLLI_H_ENC : MSA_BIT_H_FMT<0b000, 0b001001>; 1034 class SLLI_W_ENC : MSA_BIT_W_FMT<0b000, 0b001001>; 1035 class SLLI_D_ENC : MSA_BIT_D_FMT<0b000, 0b001001>; 1036 1037 class SPLAT_B_ENC : MSA_3R_INDEX_FMT<0b001, 0b00, 0b010100>; 1038 class SPLAT_H_ENC : MSA_3R_INDEX_FMT<0b001, 0b01, 0b010100>; 1039 class SPLAT_W_ENC : MSA_3R_INDEX_FMT<0b001, 0b10, 0b010100>; 1040 class SPLAT_D_ENC : MSA_3R_INDEX_FMT<0b001, 0b11, 0b010100>; 1041 1042 class SPLATI_B_ENC : MSA_ELM_B_FMT<0b0001, 0b011001>; 1043 class SPLATI_H_ENC : MSA_ELM_H_FMT<0b0001, 0b011001>; 1044 class SPLATI_W_ENC : MSA_ELM_W_FMT<0b0001, 0b011001>; 1045 class SPLATI_D_ENC : MSA_ELM_D_FMT<0b0001, 0b011001>; 1046 1047 class SRA_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001101>; 1048 class SRA_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001101>; 1049 class SRA_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001101>; 1050 class SRA_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001101>; 1051 1052 class SRAI_B_ENC : MSA_BIT_B_FMT<0b001, 0b001001>; 1053 class SRAI_H_ENC : MSA_BIT_H_FMT<0b001, 0b001001>; 1054 class SRAI_W_ENC : MSA_BIT_W_FMT<0b001, 0b001001>; 1055 class SRAI_D_ENC : MSA_BIT_D_FMT<0b001, 0b001001>; 1056 1057 class SRAR_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010101>; 1058 class SRAR_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010101>; 1059 class SRAR_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010101>; 1060 class SRAR_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010101>; 1061 1062 class SRARI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001010>; 1063 class SRARI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001010>; 1064 class SRARI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001010>; 1065 class SRARI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001010>; 1066 1067 class SRL_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001101>; 1068 class SRL_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001101>; 1069 class SRL_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001101>; 1070 class SRL_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001101>; 1071 1072 class SRLI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001001>; 1073 class SRLI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001001>; 1074 class SRLI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001001>; 1075 class SRLI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001001>; 1076 1077 class SRLR_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010101>; 1078 class SRLR_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010101>; 1079 class SRLR_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010101>; 1080 class SRLR_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010101>; 1081 1082 class SRLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001010>; 1083 class SRLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001010>; 1084 class SRLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001010>; 1085 class SRLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001010>; 1086 1087 class ST_B_ENC : MSA_MI10_FMT<0b00, 0b1001>; 1088 class ST_H_ENC : MSA_MI10_FMT<0b01, 0b1001>; 1089 class ST_W_ENC : MSA_MI10_FMT<0b10, 0b1001>; 1090 class ST_D_ENC : MSA_MI10_FMT<0b11, 0b1001>; 1091 1092 class SUBS_S_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010001>; 1093 class SUBS_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010001>; 1094 class SUBS_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010001>; 1095 class SUBS_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010001>; 1096 1097 class SUBS_U_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010001>; 1098 class SUBS_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010001>; 1099 class SUBS_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010001>; 1100 class SUBS_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010001>; 1101 1102 class SUBSUS_U_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010001>; 1103 class SUBSUS_U_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010001>; 1104 class SUBSUS_U_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010001>; 1105 class SUBSUS_U_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010001>; 1106 1107 class SUBSUU_S_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010001>; 1108 class SUBSUU_S_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010001>; 1109 class SUBSUU_S_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010001>; 1110 class SUBSUU_S_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010001>; 1111 1112 class SUBV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001110>; 1113 class SUBV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001110>; 1114 class SUBV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001110>; 1115 class SUBV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001110>; 1116 1117 class SUBVI_B_ENC : MSA_I5_FMT<0b001, 0b00, 0b000110>; 1118 class SUBVI_H_ENC : MSA_I5_FMT<0b001, 0b01, 0b000110>; 1119 class SUBVI_W_ENC : MSA_I5_FMT<0b001, 0b10, 0b000110>; 1120 class SUBVI_D_ENC : MSA_I5_FMT<0b001, 0b11, 0b000110>; 1121 1122 class VSHF_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010101>; 1123 class VSHF_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010101>; 1124 class VSHF_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010101>; 1125 class VSHF_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010101>; 1126 1127 class XOR_V_ENC : MSA_VEC_FMT<0b00011, 0b011110>; 1128 1129 class XORI_B_ENC : MSA_I8_FMT<0b11, 0b000000>; 1130 1131 // Instruction desc. 1132 class MSA_BIT_B_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1133 ComplexPattern Imm, RegisterOperand ROWD, 1134 RegisterOperand ROWS = ROWD, 1135 InstrItinClass itin = NoItinerary> { 1136 dag OutOperandList = (outs ROWD:$wd); 1137 dag InOperandList = (ins ROWS:$ws, vsplat_uimm3:$m); 1138 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1139 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1140 InstrItinClass Itinerary = itin; 1141 } 1142 1143 class MSA_BIT_H_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1144 ComplexPattern Imm, RegisterOperand ROWD, 1145 RegisterOperand ROWS = ROWD, 1146 InstrItinClass itin = NoItinerary> { 1147 dag OutOperandList = (outs ROWD:$wd); 1148 dag InOperandList = (ins ROWS:$ws, vsplat_uimm4:$m); 1149 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1150 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1151 InstrItinClass Itinerary = itin; 1152 } 1153 1154 class MSA_BIT_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1155 ComplexPattern Imm, RegisterOperand ROWD, 1156 RegisterOperand ROWS = ROWD, 1157 InstrItinClass itin = NoItinerary> { 1158 dag OutOperandList = (outs ROWD:$wd); 1159 dag InOperandList = (ins ROWS:$ws, vsplat_uimm5:$m); 1160 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1161 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1162 InstrItinClass Itinerary = itin; 1163 } 1164 1165 class MSA_BIT_D_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1166 ComplexPattern Imm, RegisterOperand ROWD, 1167 RegisterOperand ROWS = ROWD, 1168 InstrItinClass itin = NoItinerary> { 1169 dag OutOperandList = (outs ROWD:$wd); 1170 dag InOperandList = (ins ROWS:$ws, vsplat_uimm6:$m); 1171 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1172 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1173 InstrItinClass Itinerary = itin; 1174 } 1175 1176 class MSA_BIT_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1177 Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD, 1178 RegisterOperand ROWS = ROWD, 1179 InstrItinClass itin = NoItinerary> { 1180 dag OutOperandList = (outs ROWD:$wd); 1181 dag InOperandList = (ins ROWS:$ws, ImmOp:$m); 1182 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1183 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1184 InstrItinClass Itinerary = itin; 1185 } 1186 1187 class MSA_BIT_BINSXI_DESC_BASE<string instr_asm, ValueType Ty, 1188 ComplexPattern Mask, RegisterOperand ROWD, 1189 RegisterOperand ROWS = ROWD, 1190 InstrItinClass itin = NoItinerary> { 1191 dag OutOperandList = (outs ROWD:$wd); 1192 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, vsplat_uimm8:$m); 1193 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1194 // Note that binsxi and vselect treat the condition operand the opposite 1195 // way to each other. 1196 // (vselect cond, if_set, if_clear) 1197 // (BSEL_V cond, if_clear, if_set) 1198 list<dag> Pattern = [(set ROWD:$wd, (vselect (Ty Mask:$m), (Ty ROWD:$ws), 1199 ROWS:$wd_in))]; 1200 InstrItinClass Itinerary = itin; 1201 string Constraints = "$wd = $wd_in"; 1202 } 1203 1204 class MSA_BIT_BINSLI_DESC_BASE<string instr_asm, ValueType Ty, 1205 RegisterOperand ROWD, 1206 RegisterOperand ROWS = ROWD, 1207 InstrItinClass itin = NoItinerary> : 1208 MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, vsplat_maskl_bits, ROWD, ROWS, itin>; 1209 1210 class MSA_BIT_BINSRI_DESC_BASE<string instr_asm, ValueType Ty, 1211 RegisterOperand ROWD, 1212 RegisterOperand ROWS = ROWD, 1213 InstrItinClass itin = NoItinerary> : 1214 MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, vsplat_maskr_bits, ROWD, ROWS, itin>; 1215 1216 class MSA_BIT_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1217 SplatComplexPattern SplatImm, 1218 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1219 InstrItinClass itin = NoItinerary> { 1220 dag OutOperandList = (outs ROWD:$wd); 1221 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$m); 1222 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1223 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$m))]; 1224 InstrItinClass Itinerary = itin; 1225 } 1226 1227 class MSA_COPY_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1228 ValueType VecTy, RegisterOperand ROD, 1229 RegisterOperand ROWS, 1230 InstrItinClass itin = NoItinerary> { 1231 dag OutOperandList = (outs ROD:$rd); 1232 dag InOperandList = (ins ROWS:$ws, uimm4_ptr:$n); 1233 string AsmString = !strconcat(instr_asm, "\t$rd, $ws[$n]"); 1234 list<dag> Pattern = [(set ROD:$rd, (OpNode (VecTy ROWS:$ws), immZExt4Ptr:$n))]; 1235 InstrItinClass Itinerary = itin; 1236 } 1237 1238 class MSA_ELM_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1239 RegisterOperand ROWD, RegisterOperand ROWS, 1240 Operand ImmOp, ImmLeaf Imm, 1241 InstrItinClass itin = NoItinerary> { 1242 dag OutOperandList = (outs ROWD:$wd); 1243 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ImmOp:$n); 1244 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]"); 1245 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, 1246 Imm:$n))]; 1247 string Constraints = "$wd = $wd_in"; 1248 InstrItinClass Itinerary = itin; 1249 } 1250 1251 class MSA_COPY_PSEUDO_BASE<SDPatternOperator OpNode, ValueType VecTy, 1252 RegisterClass RCD, RegisterClass RCWS> : 1253 MSAPseudo<(outs RCD:$wd), (ins RCWS:$ws, uimm4_ptr:$n), 1254 [(set RCD:$wd, (OpNode (VecTy RCWS:$ws), immZExt4Ptr:$n))]> { 1255 bit usesCustomInserter = 1; 1256 } 1257 1258 class MSA_I5_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1259 SplatComplexPattern SplatImm, RegisterOperand ROWD, 1260 RegisterOperand ROWS = ROWD, 1261 InstrItinClass itin = NoItinerary> { 1262 dag OutOperandList = (outs ROWD:$wd); 1263 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$imm); 1264 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $imm"); 1265 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$imm))]; 1266 InstrItinClass Itinerary = itin; 1267 } 1268 1269 class MSA_I8_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1270 SplatComplexPattern SplatImm, RegisterOperand ROWD, 1271 RegisterOperand ROWS = ROWD, 1272 InstrItinClass itin = NoItinerary> { 1273 dag OutOperandList = (outs ROWD:$wd); 1274 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$u8); 1275 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8"); 1276 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$u8))]; 1277 InstrItinClass Itinerary = itin; 1278 } 1279 1280 class MSA_I8_SHF_DESC_BASE<string instr_asm, RegisterOperand ROWD, 1281 RegisterOperand ROWS = ROWD, 1282 InstrItinClass itin = NoItinerary> { 1283 dag OutOperandList = (outs ROWD:$wd); 1284 dag InOperandList = (ins ROWS:$ws, uimm8:$u8); 1285 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8"); 1286 list<dag> Pattern = [(set ROWD:$wd, (MipsSHF immZExt8:$u8, ROWS:$ws))]; 1287 InstrItinClass Itinerary = itin; 1288 } 1289 1290 class MSA_I10_LDI_DESC_BASE<string instr_asm, RegisterOperand ROWD, 1291 InstrItinClass itin = NoItinerary> { 1292 dag OutOperandList = (outs ROWD:$wd); 1293 dag InOperandList = (ins vsplat_simm10:$s10); 1294 string AsmString = !strconcat(instr_asm, "\t$wd, $s10"); 1295 // LDI is matched using custom matching code in MipsSEISelDAGToDAG.cpp 1296 list<dag> Pattern = []; 1297 bit hasSideEffects = 0; 1298 InstrItinClass Itinerary = itin; 1299 } 1300 1301 class MSA_2R_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1302 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1303 InstrItinClass itin = NoItinerary> { 1304 dag OutOperandList = (outs ROWD:$wd); 1305 dag InOperandList = (ins ROWS:$ws); 1306 string AsmString = !strconcat(instr_asm, "\t$wd, $ws"); 1307 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))]; 1308 InstrItinClass Itinerary = itin; 1309 } 1310 1311 class MSA_2R_FILL_DESC_BASE<string instr_asm, ValueType VT, 1312 SDPatternOperator OpNode, RegisterOperand ROWD, 1313 RegisterOperand ROS = ROWD, 1314 InstrItinClass itin = NoItinerary> { 1315 dag OutOperandList = (outs ROWD:$wd); 1316 dag InOperandList = (ins ROS:$rs); 1317 string AsmString = !strconcat(instr_asm, "\t$wd, $rs"); 1318 list<dag> Pattern = [(set ROWD:$wd, (VT (OpNode ROS:$rs)))]; 1319 InstrItinClass Itinerary = itin; 1320 } 1321 1322 class MSA_2R_FILL_PSEUDO_BASE<ValueType VT, SDPatternOperator OpNode, 1323 RegisterClass RCWD, RegisterClass RCWS = RCWD> : 1324 MSAPseudo<(outs RCWD:$wd), (ins RCWS:$fs), 1325 [(set RCWD:$wd, (OpNode RCWS:$fs))]> { 1326 let usesCustomInserter = 1; 1327 } 1328 1329 class MSA_2RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1330 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1331 InstrItinClass itin = NoItinerary> { 1332 dag OutOperandList = (outs ROWD:$wd); 1333 dag InOperandList = (ins ROWS:$ws); 1334 string AsmString = !strconcat(instr_asm, "\t$wd, $ws"); 1335 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))]; 1336 InstrItinClass Itinerary = itin; 1337 } 1338 1339 class MSA_3R_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1340 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1341 RegisterOperand ROWT = ROWD, 1342 InstrItinClass itin = NoItinerary> { 1343 dag OutOperandList = (outs ROWD:$wd); 1344 dag InOperandList = (ins ROWS:$ws, ROWT:$wt); 1345 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1346 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]; 1347 InstrItinClass Itinerary = itin; 1348 } 1349 1350 class MSA_3R_BINSX_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1351 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1352 RegisterOperand ROWT = ROWD, 1353 InstrItinClass itin = NoItinerary> { 1354 dag OutOperandList = (outs ROWD:$wd); 1355 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt); 1356 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1357 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, 1358 ROWT:$wt))]; 1359 string Constraints = "$wd = $wd_in"; 1360 InstrItinClass Itinerary = itin; 1361 } 1362 1363 class MSA_3R_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1364 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1365 InstrItinClass itin = NoItinerary> { 1366 dag OutOperandList = (outs ROWD:$wd); 1367 dag InOperandList = (ins ROWS:$ws, GPR32Opnd:$rt); 1368 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]"); 1369 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, GPR32Opnd:$rt))]; 1370 InstrItinClass Itinerary = itin; 1371 } 1372 1373 class MSA_3R_VSHF_DESC_BASE<string instr_asm, RegisterOperand ROWD, 1374 RegisterOperand ROWS = ROWD, 1375 RegisterOperand ROWT = ROWD, 1376 InstrItinClass itin = NoItinerary> { 1377 dag OutOperandList = (outs ROWD:$wd); 1378 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt); 1379 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1380 list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF ROWD:$wd_in, ROWS:$ws, 1381 ROWT:$wt))]; 1382 string Constraints = "$wd = $wd_in"; 1383 InstrItinClass Itinerary = itin; 1384 } 1385 1386 class MSA_3R_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1387 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1388 InstrItinClass itin = NoItinerary> { 1389 dag OutOperandList = (outs ROWD:$wd); 1390 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, GPR32Opnd:$rt); 1391 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]"); 1392 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, 1393 GPR32Opnd:$rt))]; 1394 InstrItinClass Itinerary = itin; 1395 string Constraints = "$wd = $wd_in"; 1396 } 1397 1398 class MSA_3R_4R_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1399 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1400 RegisterOperand ROWT = ROWD, 1401 InstrItinClass itin = NoItinerary> { 1402 dag OutOperandList = (outs ROWD:$wd); 1403 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt); 1404 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1405 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, 1406 ROWT:$wt))]; 1407 InstrItinClass Itinerary = itin; 1408 string Constraints = "$wd = $wd_in"; 1409 } 1410 1411 class MSA_3RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1412 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1413 RegisterOperand ROWT = ROWD, 1414 InstrItinClass itin = NoItinerary> : 1415 MSA_3R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>; 1416 1417 class MSA_3RF_4RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1418 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1419 RegisterOperand ROWT = ROWD, 1420 InstrItinClass itin = NoItinerary> : 1421 MSA_3R_4R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>; 1422 1423 class MSA_CBRANCH_DESC_BASE<string instr_asm, RegisterOperand ROWD> { 1424 dag OutOperandList = (outs); 1425 dag InOperandList = (ins ROWD:$wt, brtarget:$offset); 1426 string AsmString = !strconcat(instr_asm, "\t$wt, $offset"); 1427 list<dag> Pattern = []; 1428 InstrItinClass Itinerary = NoItinerary; 1429 bit isBranch = 1; 1430 bit isTerminator = 1; 1431 bit hasDelaySlot = 1; 1432 list<Register> Defs = [AT]; 1433 } 1434 1435 class MSA_INSERT_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1436 RegisterOperand ROWD, RegisterOperand ROS, 1437 InstrItinClass itin = NoItinerary> { 1438 dag OutOperandList = (outs ROWD:$wd); 1439 dag InOperandList = (ins ROWD:$wd_in, ROS:$rs, uimm6_ptr:$n); 1440 string AsmString = !strconcat(instr_asm, "\t$wd[$n], $rs"); 1441 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, 1442 ROS:$rs, 1443 immZExt6Ptr:$n))]; 1444 InstrItinClass Itinerary = itin; 1445 string Constraints = "$wd = $wd_in"; 1446 } 1447 1448 class MSA_INSERT_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty, 1449 RegisterOperand ROWD, RegisterOperand ROFS> : 1450 MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, uimm6_ptr:$n, ROFS:$fs), 1451 [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs, 1452 immZExt6Ptr:$n))]> { 1453 bit usesCustomInserter = 1; 1454 string Constraints = "$wd = $wd_in"; 1455 } 1456 1457 class MSA_INSERT_VIDX_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty, 1458 RegisterOperand ROWD, RegisterOperand ROFS, 1459 RegisterOperand ROIdx> : 1460 MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, ROIdx:$n, ROFS:$fs), 1461 [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs, 1462 ROIdx:$n))]> { 1463 bit usesCustomInserter = 1; 1464 string Constraints = "$wd = $wd_in"; 1465 } 1466 1467 class MSA_INSVE_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1468 Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD, 1469 RegisterOperand ROWS = ROWD, 1470 InstrItinClass itin = NoItinerary> { 1471 dag OutOperandList = (outs ROWD:$wd); 1472 dag InOperandList = (ins ROWD:$wd_in, ImmOp:$n, ROWS:$ws, uimmz:$n2); 1473 string AsmString = !strconcat(instr_asm, "\t$wd[$n], $ws[$n2]"); 1474 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, 1475 Imm:$n, 1476 ROWS:$ws, 1477 immz:$n2))]; 1478 InstrItinClass Itinerary = itin; 1479 string Constraints = "$wd = $wd_in"; 1480 } 1481 1482 class MSA_VEC_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1483 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1484 RegisterOperand ROWT = ROWD, 1485 InstrItinClass itin = NoItinerary> { 1486 dag OutOperandList = (outs ROWD:$wd); 1487 dag InOperandList = (ins ROWS:$ws, ROWT:$wt); 1488 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1489 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]; 1490 InstrItinClass Itinerary = itin; 1491 } 1492 1493 class MSA_ELM_SPLAT_DESC_BASE<string instr_asm, SplatComplexPattern SplatImm, 1494 RegisterOperand ROWD, 1495 RegisterOperand ROWS = ROWD, 1496 InstrItinClass itin = NoItinerary> { 1497 dag OutOperandList = (outs ROWD:$wd); 1498 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$n); 1499 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]"); 1500 list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF SplatImm:$n, ROWS:$ws, 1501 ROWS:$ws))]; 1502 InstrItinClass Itinerary = itin; 1503 } 1504 1505 class MSA_VEC_PSEUDO_BASE<SDPatternOperator OpNode, RegisterOperand ROWD, 1506 RegisterOperand ROWS = ROWD, 1507 RegisterOperand ROWT = ROWD> : 1508 MSAPseudo<(outs ROWD:$wd), (ins ROWS:$ws, ROWT:$wt), 1509 [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]>; 1510 1511 class ADD_A_B_DESC : MSA_3R_DESC_BASE<"add_a.b", int_mips_add_a_b, MSA128BOpnd>, 1512 IsCommutable; 1513 class ADD_A_H_DESC : MSA_3R_DESC_BASE<"add_a.h", int_mips_add_a_h, MSA128HOpnd>, 1514 IsCommutable; 1515 class ADD_A_W_DESC : MSA_3R_DESC_BASE<"add_a.w", int_mips_add_a_w, MSA128WOpnd>, 1516 IsCommutable; 1517 class ADD_A_D_DESC : MSA_3R_DESC_BASE<"add_a.d", int_mips_add_a_d, MSA128DOpnd>, 1518 IsCommutable; 1519 1520 class ADDS_A_B_DESC : MSA_3R_DESC_BASE<"adds_a.b", int_mips_adds_a_b, 1521 MSA128BOpnd>, IsCommutable; 1522 class ADDS_A_H_DESC : MSA_3R_DESC_BASE<"adds_a.h", int_mips_adds_a_h, 1523 MSA128HOpnd>, IsCommutable; 1524 class ADDS_A_W_DESC : MSA_3R_DESC_BASE<"adds_a.w", int_mips_adds_a_w, 1525 MSA128WOpnd>, IsCommutable; 1526 class ADDS_A_D_DESC : MSA_3R_DESC_BASE<"adds_a.d", int_mips_adds_a_d, 1527 MSA128DOpnd>, IsCommutable; 1528 1529 class ADDS_S_B_DESC : MSA_3R_DESC_BASE<"adds_s.b", int_mips_adds_s_b, 1530 MSA128BOpnd>, IsCommutable; 1531 class ADDS_S_H_DESC : MSA_3R_DESC_BASE<"adds_s.h", int_mips_adds_s_h, 1532 MSA128HOpnd>, IsCommutable; 1533 class ADDS_S_W_DESC : MSA_3R_DESC_BASE<"adds_s.w", int_mips_adds_s_w, 1534 MSA128WOpnd>, IsCommutable; 1535 class ADDS_S_D_DESC : MSA_3R_DESC_BASE<"adds_s.d", int_mips_adds_s_d, 1536 MSA128DOpnd>, IsCommutable; 1537 1538 class ADDS_U_B_DESC : MSA_3R_DESC_BASE<"adds_u.b", int_mips_adds_u_b, 1539 MSA128BOpnd>, IsCommutable; 1540 class ADDS_U_H_DESC : MSA_3R_DESC_BASE<"adds_u.h", int_mips_adds_u_h, 1541 MSA128HOpnd>, IsCommutable; 1542 class ADDS_U_W_DESC : MSA_3R_DESC_BASE<"adds_u.w", int_mips_adds_u_w, 1543 MSA128WOpnd>, IsCommutable; 1544 class ADDS_U_D_DESC : MSA_3R_DESC_BASE<"adds_u.d", int_mips_adds_u_d, 1545 MSA128DOpnd>, IsCommutable; 1546 1547 class ADDV_B_DESC : MSA_3R_DESC_BASE<"addv.b", add, MSA128BOpnd>, IsCommutable; 1548 class ADDV_H_DESC : MSA_3R_DESC_BASE<"addv.h", add, MSA128HOpnd>, IsCommutable; 1549 class ADDV_W_DESC : MSA_3R_DESC_BASE<"addv.w", add, MSA128WOpnd>, IsCommutable; 1550 class ADDV_D_DESC : MSA_3R_DESC_BASE<"addv.d", add, MSA128DOpnd>, IsCommutable; 1551 1552 class ADDVI_B_DESC : MSA_I5_DESC_BASE<"addvi.b", add, vsplati8_uimm5, 1553 MSA128BOpnd>; 1554 class ADDVI_H_DESC : MSA_I5_DESC_BASE<"addvi.h", add, vsplati16_uimm5, 1555 MSA128HOpnd>; 1556 class ADDVI_W_DESC : MSA_I5_DESC_BASE<"addvi.w", add, vsplati32_uimm5, 1557 MSA128WOpnd>; 1558 class ADDVI_D_DESC : MSA_I5_DESC_BASE<"addvi.d", add, vsplati64_uimm5, 1559 MSA128DOpnd>; 1560 1561 class AND_V_DESC : MSA_VEC_DESC_BASE<"and.v", and, MSA128BOpnd>; 1562 class AND_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128HOpnd>; 1563 class AND_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128WOpnd>; 1564 class AND_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128DOpnd>; 1565 1566 class ANDI_B_DESC : MSA_I8_DESC_BASE<"andi.b", and, vsplati8_uimm8, 1567 MSA128BOpnd>; 1568 1569 class ASUB_S_B_DESC : MSA_3R_DESC_BASE<"asub_s.b", int_mips_asub_s_b, 1570 MSA128BOpnd>; 1571 class ASUB_S_H_DESC : MSA_3R_DESC_BASE<"asub_s.h", int_mips_asub_s_h, 1572 MSA128HOpnd>; 1573 class ASUB_S_W_DESC : MSA_3R_DESC_BASE<"asub_s.w", int_mips_asub_s_w, 1574 MSA128WOpnd>; 1575 class ASUB_S_D_DESC : MSA_3R_DESC_BASE<"asub_s.d", int_mips_asub_s_d, 1576 MSA128DOpnd>; 1577 1578 class ASUB_U_B_DESC : MSA_3R_DESC_BASE<"asub_u.b", int_mips_asub_u_b, 1579 MSA128BOpnd>; 1580 class ASUB_U_H_DESC : MSA_3R_DESC_BASE<"asub_u.h", int_mips_asub_u_h, 1581 MSA128HOpnd>; 1582 class ASUB_U_W_DESC : MSA_3R_DESC_BASE<"asub_u.w", int_mips_asub_u_w, 1583 MSA128WOpnd>; 1584 class ASUB_U_D_DESC : MSA_3R_DESC_BASE<"asub_u.d", int_mips_asub_u_d, 1585 MSA128DOpnd>; 1586 1587 class AVE_S_B_DESC : MSA_3R_DESC_BASE<"ave_s.b", int_mips_ave_s_b, MSA128BOpnd>, 1588 IsCommutable; 1589 class AVE_S_H_DESC : MSA_3R_DESC_BASE<"ave_s.h", int_mips_ave_s_h, MSA128HOpnd>, 1590 IsCommutable; 1591 class AVE_S_W_DESC : MSA_3R_DESC_BASE<"ave_s.w", int_mips_ave_s_w, MSA128WOpnd>, 1592 IsCommutable; 1593 class AVE_S_D_DESC : MSA_3R_DESC_BASE<"ave_s.d", int_mips_ave_s_d, MSA128DOpnd>, 1594 IsCommutable; 1595 1596 class AVE_U_B_DESC : MSA_3R_DESC_BASE<"ave_u.b", int_mips_ave_u_b, MSA128BOpnd>, 1597 IsCommutable; 1598 class AVE_U_H_DESC : MSA_3R_DESC_BASE<"ave_u.h", int_mips_ave_u_h, MSA128HOpnd>, 1599 IsCommutable; 1600 class AVE_U_W_DESC : MSA_3R_DESC_BASE<"ave_u.w", int_mips_ave_u_w, MSA128WOpnd>, 1601 IsCommutable; 1602 class AVE_U_D_DESC : MSA_3R_DESC_BASE<"ave_u.d", int_mips_ave_u_d, MSA128DOpnd>, 1603 IsCommutable; 1604 1605 class AVER_S_B_DESC : MSA_3R_DESC_BASE<"aver_s.b", int_mips_aver_s_b, 1606 MSA128BOpnd>, IsCommutable; 1607 class AVER_S_H_DESC : MSA_3R_DESC_BASE<"aver_s.h", int_mips_aver_s_h, 1608 MSA128HOpnd>, IsCommutable; 1609 class AVER_S_W_DESC : MSA_3R_DESC_BASE<"aver_s.w", int_mips_aver_s_w, 1610 MSA128WOpnd>, IsCommutable; 1611 class AVER_S_D_DESC : MSA_3R_DESC_BASE<"aver_s.d", int_mips_aver_s_d, 1612 MSA128DOpnd>, IsCommutable; 1613 1614 class AVER_U_B_DESC : MSA_3R_DESC_BASE<"aver_u.b", int_mips_aver_u_b, 1615 MSA128BOpnd>, IsCommutable; 1616 class AVER_U_H_DESC : MSA_3R_DESC_BASE<"aver_u.h", int_mips_aver_u_h, 1617 MSA128HOpnd>, IsCommutable; 1618 class AVER_U_W_DESC : MSA_3R_DESC_BASE<"aver_u.w", int_mips_aver_u_w, 1619 MSA128WOpnd>, IsCommutable; 1620 class AVER_U_D_DESC : MSA_3R_DESC_BASE<"aver_u.d", int_mips_aver_u_d, 1621 MSA128DOpnd>, IsCommutable; 1622 1623 class BCLR_B_DESC : MSA_3R_DESC_BASE<"bclr.b", vbclr_b, MSA128BOpnd>; 1624 class BCLR_H_DESC : MSA_3R_DESC_BASE<"bclr.h", vbclr_h, MSA128HOpnd>; 1625 class BCLR_W_DESC : MSA_3R_DESC_BASE<"bclr.w", vbclr_w, MSA128WOpnd>; 1626 class BCLR_D_DESC : MSA_3R_DESC_BASE<"bclr.d", vbclr_d, MSA128DOpnd>; 1627 1628 class BCLRI_B_DESC : MSA_BIT_B_DESC_BASE<"bclri.b", and, vsplat_uimm_inv_pow2, 1629 MSA128BOpnd>; 1630 class BCLRI_H_DESC : MSA_BIT_H_DESC_BASE<"bclri.h", and, vsplat_uimm_inv_pow2, 1631 MSA128HOpnd>; 1632 class BCLRI_W_DESC : MSA_BIT_W_DESC_BASE<"bclri.w", and, vsplat_uimm_inv_pow2, 1633 MSA128WOpnd>; 1634 class BCLRI_D_DESC : MSA_BIT_D_DESC_BASE<"bclri.d", and, vsplat_uimm_inv_pow2, 1635 MSA128DOpnd>; 1636 1637 class BINSL_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.b", int_mips_binsl_b, 1638 MSA128BOpnd>; 1639 class BINSL_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.h", int_mips_binsl_h, 1640 MSA128HOpnd>; 1641 class BINSL_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.w", int_mips_binsl_w, 1642 MSA128WOpnd>; 1643 class BINSL_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.d", int_mips_binsl_d, 1644 MSA128DOpnd>; 1645 1646 class BINSLI_B_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.b", v16i8, MSA128BOpnd>; 1647 class BINSLI_H_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.h", v8i16, MSA128HOpnd>; 1648 class BINSLI_W_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.w", v4i32, MSA128WOpnd>; 1649 class BINSLI_D_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.d", v2i64, MSA128DOpnd>; 1650 1651 class BINSR_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.b", int_mips_binsr_b, 1652 MSA128BOpnd>; 1653 class BINSR_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.h", int_mips_binsr_h, 1654 MSA128HOpnd>; 1655 class BINSR_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.w", int_mips_binsr_w, 1656 MSA128WOpnd>; 1657 class BINSR_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.d", int_mips_binsr_d, 1658 MSA128DOpnd>; 1659 1660 class BINSRI_B_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.b", v16i8, MSA128BOpnd>; 1661 class BINSRI_H_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.h", v8i16, MSA128HOpnd>; 1662 class BINSRI_W_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.w", v4i32, MSA128WOpnd>; 1663 class BINSRI_D_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.d", v2i64, MSA128DOpnd>; 1664 1665 class BMNZ_V_DESC { 1666 dag OutOperandList = (outs MSA128BOpnd:$wd); 1667 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1668 MSA128BOpnd:$wt); 1669 string AsmString = "bmnz.v\t$wd, $ws, $wt"; 1670 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt, 1671 MSA128BOpnd:$ws, 1672 MSA128BOpnd:$wd_in))]; 1673 InstrItinClass Itinerary = NoItinerary; 1674 string Constraints = "$wd = $wd_in"; 1675 } 1676 1677 class BMNZI_B_DESC { 1678 dag OutOperandList = (outs MSA128BOpnd:$wd); 1679 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1680 vsplat_uimm8:$u8); 1681 string AsmString = "bmnzi.b\t$wd, $ws, $u8"; 1682 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8, 1683 MSA128BOpnd:$ws, 1684 MSA128BOpnd:$wd_in))]; 1685 InstrItinClass Itinerary = NoItinerary; 1686 string Constraints = "$wd = $wd_in"; 1687 } 1688 1689 class BMZ_V_DESC { 1690 dag OutOperandList = (outs MSA128BOpnd:$wd); 1691 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1692 MSA128BOpnd:$wt); 1693 string AsmString = "bmz.v\t$wd, $ws, $wt"; 1694 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt, 1695 MSA128BOpnd:$wd_in, 1696 MSA128BOpnd:$ws))]; 1697 InstrItinClass Itinerary = NoItinerary; 1698 string Constraints = "$wd = $wd_in"; 1699 } 1700 1701 class BMZI_B_DESC { 1702 dag OutOperandList = (outs MSA128BOpnd:$wd); 1703 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1704 vsplat_uimm8:$u8); 1705 string AsmString = "bmzi.b\t$wd, $ws, $u8"; 1706 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8, 1707 MSA128BOpnd:$wd_in, 1708 MSA128BOpnd:$ws))]; 1709 InstrItinClass Itinerary = NoItinerary; 1710 string Constraints = "$wd = $wd_in"; 1711 } 1712 1713 class BNEG_B_DESC : MSA_3R_DESC_BASE<"bneg.b", vbneg_b, MSA128BOpnd>; 1714 class BNEG_H_DESC : MSA_3R_DESC_BASE<"bneg.h", vbneg_h, MSA128HOpnd>; 1715 class BNEG_W_DESC : MSA_3R_DESC_BASE<"bneg.w", vbneg_w, MSA128WOpnd>; 1716 class BNEG_D_DESC : MSA_3R_DESC_BASE<"bneg.d", vbneg_d, MSA128DOpnd>; 1717 1718 class BNEGI_B_DESC : MSA_BIT_B_DESC_BASE<"bnegi.b", xor, vsplat_uimm_pow2, 1719 MSA128BOpnd>; 1720 class BNEGI_H_DESC : MSA_BIT_H_DESC_BASE<"bnegi.h", xor, vsplat_uimm_pow2, 1721 MSA128HOpnd>; 1722 class BNEGI_W_DESC : MSA_BIT_W_DESC_BASE<"bnegi.w", xor, vsplat_uimm_pow2, 1723 MSA128WOpnd>; 1724 class BNEGI_D_DESC : MSA_BIT_D_DESC_BASE<"bnegi.d", xor, vsplat_uimm_pow2, 1725 MSA128DOpnd>; 1726 1727 class BNZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bnz.b", MSA128BOpnd>; 1728 class BNZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bnz.h", MSA128HOpnd>; 1729 class BNZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bnz.w", MSA128WOpnd>; 1730 class BNZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bnz.d", MSA128DOpnd>; 1731 1732 class BNZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bnz.v", MSA128BOpnd>; 1733 1734 class BSEL_V_DESC { 1735 dag OutOperandList = (outs MSA128BOpnd:$wd); 1736 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1737 MSA128BOpnd:$wt); 1738 string AsmString = "bsel.v\t$wd, $ws, $wt"; 1739 // Note that vselect and BSEL_V treat the condition operand the opposite way 1740 // from each other. 1741 // (vselect cond, if_set, if_clear) 1742 // (BSEL_V cond, if_clear, if_set) 1743 list<dag> Pattern = [(set MSA128BOpnd:$wd, 1744 (vselect MSA128BOpnd:$wd_in, MSA128BOpnd:$wt, 1745 MSA128BOpnd:$ws))]; 1746 InstrItinClass Itinerary = NoItinerary; 1747 string Constraints = "$wd = $wd_in"; 1748 } 1749 1750 class BSELI_B_DESC { 1751 dag OutOperandList = (outs MSA128BOpnd:$wd); 1752 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1753 vsplat_uimm8:$u8); 1754 string AsmString = "bseli.b\t$wd, $ws, $u8"; 1755 // Note that vselect and BSEL_V treat the condition operand the opposite way 1756 // from each other. 1757 // (vselect cond, if_set, if_clear) 1758 // (BSEL_V cond, if_clear, if_set) 1759 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wd_in, 1760 vsplati8_uimm8:$u8, 1761 MSA128BOpnd:$ws))]; 1762 InstrItinClass Itinerary = NoItinerary; 1763 string Constraints = "$wd = $wd_in"; 1764 } 1765 1766 class BSET_B_DESC : MSA_3R_DESC_BASE<"bset.b", vbset_b, MSA128BOpnd>; 1767 class BSET_H_DESC : MSA_3R_DESC_BASE<"bset.h", vbset_h, MSA128HOpnd>; 1768 class BSET_W_DESC : MSA_3R_DESC_BASE<"bset.w", vbset_w, MSA128WOpnd>; 1769 class BSET_D_DESC : MSA_3R_DESC_BASE<"bset.d", vbset_d, MSA128DOpnd>; 1770 1771 class BSETI_B_DESC : MSA_BIT_B_DESC_BASE<"bseti.b", or, vsplat_uimm_pow2, 1772 MSA128BOpnd>; 1773 class BSETI_H_DESC : MSA_BIT_H_DESC_BASE<"bseti.h", or, vsplat_uimm_pow2, 1774 MSA128HOpnd>; 1775 class BSETI_W_DESC : MSA_BIT_W_DESC_BASE<"bseti.w", or, vsplat_uimm_pow2, 1776 MSA128WOpnd>; 1777 class BSETI_D_DESC : MSA_BIT_D_DESC_BASE<"bseti.d", or, vsplat_uimm_pow2, 1778 MSA128DOpnd>; 1779 1780 class BZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bz.b", MSA128BOpnd>; 1781 class BZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bz.h", MSA128HOpnd>; 1782 class BZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bz.w", MSA128WOpnd>; 1783 class BZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bz.d", MSA128DOpnd>; 1784 1785 class BZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bz.v", MSA128BOpnd>; 1786 1787 class CEQ_B_DESC : MSA_3R_DESC_BASE<"ceq.b", vseteq_v16i8, MSA128BOpnd>, 1788 IsCommutable; 1789 class CEQ_H_DESC : MSA_3R_DESC_BASE<"ceq.h", vseteq_v8i16, MSA128HOpnd>, 1790 IsCommutable; 1791 class CEQ_W_DESC : MSA_3R_DESC_BASE<"ceq.w", vseteq_v4i32, MSA128WOpnd>, 1792 IsCommutable; 1793 class CEQ_D_DESC : MSA_3R_DESC_BASE<"ceq.d", vseteq_v2i64, MSA128DOpnd>, 1794 IsCommutable; 1795 1796 class CEQI_B_DESC : MSA_I5_DESC_BASE<"ceqi.b", vseteq_v16i8, vsplati8_simm5, 1797 MSA128BOpnd>; 1798 class CEQI_H_DESC : MSA_I5_DESC_BASE<"ceqi.h", vseteq_v8i16, vsplati16_simm5, 1799 MSA128HOpnd>; 1800 class CEQI_W_DESC : MSA_I5_DESC_BASE<"ceqi.w", vseteq_v4i32, vsplati32_simm5, 1801 MSA128WOpnd>; 1802 class CEQI_D_DESC : MSA_I5_DESC_BASE<"ceqi.d", vseteq_v2i64, vsplati64_simm5, 1803 MSA128DOpnd>; 1804 1805 class CFCMSA_DESC { 1806 dag OutOperandList = (outs GPR32Opnd:$rd); 1807 dag InOperandList = (ins MSA128CROpnd:$cs); 1808 string AsmString = "cfcmsa\t$rd, $cs"; 1809 InstrItinClass Itinerary = NoItinerary; 1810 bit hasSideEffects = 1; 1811 } 1812 1813 class CLE_S_B_DESC : MSA_3R_DESC_BASE<"cle_s.b", vsetle_v16i8, MSA128BOpnd>; 1814 class CLE_S_H_DESC : MSA_3R_DESC_BASE<"cle_s.h", vsetle_v8i16, MSA128HOpnd>; 1815 class CLE_S_W_DESC : MSA_3R_DESC_BASE<"cle_s.w", vsetle_v4i32, MSA128WOpnd>; 1816 class CLE_S_D_DESC : MSA_3R_DESC_BASE<"cle_s.d", vsetle_v2i64, MSA128DOpnd>; 1817 1818 class CLE_U_B_DESC : MSA_3R_DESC_BASE<"cle_u.b", vsetule_v16i8, MSA128BOpnd>; 1819 class CLE_U_H_DESC : MSA_3R_DESC_BASE<"cle_u.h", vsetule_v8i16, MSA128HOpnd>; 1820 class CLE_U_W_DESC : MSA_3R_DESC_BASE<"cle_u.w", vsetule_v4i32, MSA128WOpnd>; 1821 class CLE_U_D_DESC : MSA_3R_DESC_BASE<"cle_u.d", vsetule_v2i64, MSA128DOpnd>; 1822 1823 class CLEI_S_B_DESC : MSA_I5_DESC_BASE<"clei_s.b", vsetle_v16i8, 1824 vsplati8_simm5, MSA128BOpnd>; 1825 class CLEI_S_H_DESC : MSA_I5_DESC_BASE<"clei_s.h", vsetle_v8i16, 1826 vsplati16_simm5, MSA128HOpnd>; 1827 class CLEI_S_W_DESC : MSA_I5_DESC_BASE<"clei_s.w", vsetle_v4i32, 1828 vsplati32_simm5, MSA128WOpnd>; 1829 class CLEI_S_D_DESC : MSA_I5_DESC_BASE<"clei_s.d", vsetle_v2i64, 1830 vsplati64_simm5, MSA128DOpnd>; 1831 1832 class CLEI_U_B_DESC : MSA_I5_DESC_BASE<"clei_u.b", vsetule_v16i8, 1833 vsplati8_uimm5, MSA128BOpnd>; 1834 class CLEI_U_H_DESC : MSA_I5_DESC_BASE<"clei_u.h", vsetule_v8i16, 1835 vsplati16_uimm5, MSA128HOpnd>; 1836 class CLEI_U_W_DESC : MSA_I5_DESC_BASE<"clei_u.w", vsetule_v4i32, 1837 vsplati32_uimm5, MSA128WOpnd>; 1838 class CLEI_U_D_DESC : MSA_I5_DESC_BASE<"clei_u.d", vsetule_v2i64, 1839 vsplati64_uimm5, MSA128DOpnd>; 1840 1841 class CLT_S_B_DESC : MSA_3R_DESC_BASE<"clt_s.b", vsetlt_v16i8, MSA128BOpnd>; 1842 class CLT_S_H_DESC : MSA_3R_DESC_BASE<"clt_s.h", vsetlt_v8i16, MSA128HOpnd>; 1843 class CLT_S_W_DESC : MSA_3R_DESC_BASE<"clt_s.w", vsetlt_v4i32, MSA128WOpnd>; 1844 class CLT_S_D_DESC : MSA_3R_DESC_BASE<"clt_s.d", vsetlt_v2i64, MSA128DOpnd>; 1845 1846 class CLT_U_B_DESC : MSA_3R_DESC_BASE<"clt_u.b", vsetult_v16i8, MSA128BOpnd>; 1847 class CLT_U_H_DESC : MSA_3R_DESC_BASE<"clt_u.h", vsetult_v8i16, MSA128HOpnd>; 1848 class CLT_U_W_DESC : MSA_3R_DESC_BASE<"clt_u.w", vsetult_v4i32, MSA128WOpnd>; 1849 class CLT_U_D_DESC : MSA_3R_DESC_BASE<"clt_u.d", vsetult_v2i64, MSA128DOpnd>; 1850 1851 class CLTI_S_B_DESC : MSA_I5_DESC_BASE<"clti_s.b", vsetlt_v16i8, 1852 vsplati8_simm5, MSA128BOpnd>; 1853 class CLTI_S_H_DESC : MSA_I5_DESC_BASE<"clti_s.h", vsetlt_v8i16, 1854 vsplati16_simm5, MSA128HOpnd>; 1855 class CLTI_S_W_DESC : MSA_I5_DESC_BASE<"clti_s.w", vsetlt_v4i32, 1856 vsplati32_simm5, MSA128WOpnd>; 1857 class CLTI_S_D_DESC : MSA_I5_DESC_BASE<"clti_s.d", vsetlt_v2i64, 1858 vsplati64_simm5, MSA128DOpnd>; 1859 1860 class CLTI_U_B_DESC : MSA_I5_DESC_BASE<"clti_u.b", vsetult_v16i8, 1861 vsplati8_uimm5, MSA128BOpnd>; 1862 class CLTI_U_H_DESC : MSA_I5_DESC_BASE<"clti_u.h", vsetult_v8i16, 1863 vsplati16_uimm5, MSA128HOpnd>; 1864 class CLTI_U_W_DESC : MSA_I5_DESC_BASE<"clti_u.w", vsetult_v4i32, 1865 vsplati32_uimm5, MSA128WOpnd>; 1866 class CLTI_U_D_DESC : MSA_I5_DESC_BASE<"clti_u.d", vsetult_v2i64, 1867 vsplati64_uimm5, MSA128DOpnd>; 1868 1869 class COPY_S_B_DESC : MSA_COPY_DESC_BASE<"copy_s.b", vextract_sext_i8, v16i8, 1870 GPR32Opnd, MSA128BOpnd>; 1871 class COPY_S_H_DESC : MSA_COPY_DESC_BASE<"copy_s.h", vextract_sext_i16, v8i16, 1872 GPR32Opnd, MSA128HOpnd>; 1873 class COPY_S_W_DESC : MSA_COPY_DESC_BASE<"copy_s.w", vextract_sext_i32, v4i32, 1874 GPR32Opnd, MSA128WOpnd>; 1875 class COPY_S_D_DESC : MSA_COPY_DESC_BASE<"copy_s.d", vextract_sext_i64, v2i64, 1876 GPR64Opnd, MSA128DOpnd>; 1877 1878 class COPY_U_B_DESC : MSA_COPY_DESC_BASE<"copy_u.b", vextract_zext_i8, v16i8, 1879 GPR32Opnd, MSA128BOpnd>; 1880 class COPY_U_H_DESC : MSA_COPY_DESC_BASE<"copy_u.h", vextract_zext_i16, v8i16, 1881 GPR32Opnd, MSA128HOpnd>; 1882 class COPY_U_W_DESC : MSA_COPY_DESC_BASE<"copy_u.w", vextract_zext_i32, v4i32, 1883 GPR32Opnd, MSA128WOpnd>; 1884 1885 class COPY_FW_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v4f32, FGR32, 1886 MSA128W>; 1887 class COPY_FD_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v2f64, FGR64, 1888 MSA128D>; 1889 1890 class CTCMSA_DESC { 1891 dag OutOperandList = (outs); 1892 dag InOperandList = (ins MSA128CROpnd:$cd, GPR32Opnd:$rs); 1893 string AsmString = "ctcmsa\t$cd, $rs"; 1894 InstrItinClass Itinerary = NoItinerary; 1895 bit hasSideEffects = 1; 1896 } 1897 1898 class DIV_S_B_DESC : MSA_3R_DESC_BASE<"div_s.b", sdiv, MSA128BOpnd>; 1899 class DIV_S_H_DESC : MSA_3R_DESC_BASE<"div_s.h", sdiv, MSA128HOpnd>; 1900 class DIV_S_W_DESC : MSA_3R_DESC_BASE<"div_s.w", sdiv, MSA128WOpnd>; 1901 class DIV_S_D_DESC : MSA_3R_DESC_BASE<"div_s.d", sdiv, MSA128DOpnd>; 1902 1903 class DIV_U_B_DESC : MSA_3R_DESC_BASE<"div_u.b", udiv, MSA128BOpnd>; 1904 class DIV_U_H_DESC : MSA_3R_DESC_BASE<"div_u.h", udiv, MSA128HOpnd>; 1905 class DIV_U_W_DESC : MSA_3R_DESC_BASE<"div_u.w", udiv, MSA128WOpnd>; 1906 class DIV_U_D_DESC : MSA_3R_DESC_BASE<"div_u.d", udiv, MSA128DOpnd>; 1907 1908 class DOTP_S_H_DESC : MSA_3R_DESC_BASE<"dotp_s.h", int_mips_dotp_s_h, 1909 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>, 1910 IsCommutable; 1911 class DOTP_S_W_DESC : MSA_3R_DESC_BASE<"dotp_s.w", int_mips_dotp_s_w, 1912 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>, 1913 IsCommutable; 1914 class DOTP_S_D_DESC : MSA_3R_DESC_BASE<"dotp_s.d", int_mips_dotp_s_d, 1915 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>, 1916 IsCommutable; 1917 1918 class DOTP_U_H_DESC : MSA_3R_DESC_BASE<"dotp_u.h", int_mips_dotp_u_h, 1919 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>, 1920 IsCommutable; 1921 class DOTP_U_W_DESC : MSA_3R_DESC_BASE<"dotp_u.w", int_mips_dotp_u_w, 1922 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>, 1923 IsCommutable; 1924 class DOTP_U_D_DESC : MSA_3R_DESC_BASE<"dotp_u.d", int_mips_dotp_u_d, 1925 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>, 1926 IsCommutable; 1927 1928 class DPADD_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.h", int_mips_dpadd_s_h, 1929 MSA128HOpnd, MSA128BOpnd, 1930 MSA128BOpnd>, IsCommutable; 1931 class DPADD_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.w", int_mips_dpadd_s_w, 1932 MSA128WOpnd, MSA128HOpnd, 1933 MSA128HOpnd>, IsCommutable; 1934 class DPADD_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.d", int_mips_dpadd_s_d, 1935 MSA128DOpnd, MSA128WOpnd, 1936 MSA128WOpnd>, IsCommutable; 1937 1938 class DPADD_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.h", int_mips_dpadd_u_h, 1939 MSA128HOpnd, MSA128BOpnd, 1940 MSA128BOpnd>, IsCommutable; 1941 class DPADD_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.w", int_mips_dpadd_u_w, 1942 MSA128WOpnd, MSA128HOpnd, 1943 MSA128HOpnd>, IsCommutable; 1944 class DPADD_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.d", int_mips_dpadd_u_d, 1945 MSA128DOpnd, MSA128WOpnd, 1946 MSA128WOpnd>, IsCommutable; 1947 1948 class DPSUB_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.h", int_mips_dpsub_s_h, 1949 MSA128HOpnd, MSA128BOpnd, 1950 MSA128BOpnd>; 1951 class DPSUB_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.w", int_mips_dpsub_s_w, 1952 MSA128WOpnd, MSA128HOpnd, 1953 MSA128HOpnd>; 1954 class DPSUB_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.d", int_mips_dpsub_s_d, 1955 MSA128DOpnd, MSA128WOpnd, 1956 MSA128WOpnd>; 1957 1958 class DPSUB_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.h", int_mips_dpsub_u_h, 1959 MSA128HOpnd, MSA128BOpnd, 1960 MSA128BOpnd>; 1961 class DPSUB_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.w", int_mips_dpsub_u_w, 1962 MSA128WOpnd, MSA128HOpnd, 1963 MSA128HOpnd>; 1964 class DPSUB_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.d", int_mips_dpsub_u_d, 1965 MSA128DOpnd, MSA128WOpnd, 1966 MSA128WOpnd>; 1967 1968 class FADD_W_DESC : MSA_3RF_DESC_BASE<"fadd.w", fadd, MSA128WOpnd>, 1969 IsCommutable; 1970 class FADD_D_DESC : MSA_3RF_DESC_BASE<"fadd.d", fadd, MSA128DOpnd>, 1971 IsCommutable; 1972 1973 class FCAF_W_DESC : MSA_3RF_DESC_BASE<"fcaf.w", int_mips_fcaf_w, MSA128WOpnd>, 1974 IsCommutable; 1975 class FCAF_D_DESC : MSA_3RF_DESC_BASE<"fcaf.d", int_mips_fcaf_d, MSA128DOpnd>, 1976 IsCommutable; 1977 1978 class FCEQ_W_DESC : MSA_3RF_DESC_BASE<"fceq.w", vfsetoeq_v4f32, MSA128WOpnd>, 1979 IsCommutable; 1980 class FCEQ_D_DESC : MSA_3RF_DESC_BASE<"fceq.d", vfsetoeq_v2f64, MSA128DOpnd>, 1981 IsCommutable; 1982 1983 class FCLASS_W_DESC : MSA_2RF_DESC_BASE<"fclass.w", int_mips_fclass_w, 1984 MSA128WOpnd>; 1985 class FCLASS_D_DESC : MSA_2RF_DESC_BASE<"fclass.d", int_mips_fclass_d, 1986 MSA128DOpnd>; 1987 1988 class FCLE_W_DESC : MSA_3RF_DESC_BASE<"fcle.w", vfsetole_v4f32, MSA128WOpnd>; 1989 class FCLE_D_DESC : MSA_3RF_DESC_BASE<"fcle.d", vfsetole_v2f64, MSA128DOpnd>; 1990 1991 class FCLT_W_DESC : MSA_3RF_DESC_BASE<"fclt.w", vfsetolt_v4f32, MSA128WOpnd>; 1992 class FCLT_D_DESC : MSA_3RF_DESC_BASE<"fclt.d", vfsetolt_v2f64, MSA128DOpnd>; 1993 1994 class FCNE_W_DESC : MSA_3RF_DESC_BASE<"fcne.w", vfsetone_v4f32, MSA128WOpnd>, 1995 IsCommutable; 1996 class FCNE_D_DESC : MSA_3RF_DESC_BASE<"fcne.d", vfsetone_v2f64, MSA128DOpnd>, 1997 IsCommutable; 1998 1999 class FCOR_W_DESC : MSA_3RF_DESC_BASE<"fcor.w", vfsetord_v4f32, MSA128WOpnd>, 2000 IsCommutable; 2001 class FCOR_D_DESC : MSA_3RF_DESC_BASE<"fcor.d", vfsetord_v2f64, MSA128DOpnd>, 2002 IsCommutable; 2003 2004 class FCUEQ_W_DESC : MSA_3RF_DESC_BASE<"fcueq.w", vfsetueq_v4f32, MSA128WOpnd>, 2005 IsCommutable; 2006 class FCUEQ_D_DESC : MSA_3RF_DESC_BASE<"fcueq.d", vfsetueq_v2f64, MSA128DOpnd>, 2007 IsCommutable; 2008 2009 class FCULE_W_DESC : MSA_3RF_DESC_BASE<"fcule.w", vfsetule_v4f32, MSA128WOpnd>, 2010 IsCommutable; 2011 class FCULE_D_DESC : MSA_3RF_DESC_BASE<"fcule.d", vfsetule_v2f64, MSA128DOpnd>, 2012 IsCommutable; 2013 2014 class FCULT_W_DESC : MSA_3RF_DESC_BASE<"fcult.w", vfsetult_v4f32, MSA128WOpnd>, 2015 IsCommutable; 2016 class FCULT_D_DESC : MSA_3RF_DESC_BASE<"fcult.d", vfsetult_v2f64, MSA128DOpnd>, 2017 IsCommutable; 2018 2019 class FCUN_W_DESC : MSA_3RF_DESC_BASE<"fcun.w", vfsetun_v4f32, MSA128WOpnd>, 2020 IsCommutable; 2021 class FCUN_D_DESC : MSA_3RF_DESC_BASE<"fcun.d", vfsetun_v2f64, MSA128DOpnd>, 2022 IsCommutable; 2023 2024 class FCUNE_W_DESC : MSA_3RF_DESC_BASE<"fcune.w", vfsetune_v4f32, MSA128WOpnd>, 2025 IsCommutable; 2026 class FCUNE_D_DESC : MSA_3RF_DESC_BASE<"fcune.d", vfsetune_v2f64, MSA128DOpnd>, 2027 IsCommutable; 2028 2029 class FDIV_W_DESC : MSA_3RF_DESC_BASE<"fdiv.w", fdiv, MSA128WOpnd>; 2030 class FDIV_D_DESC : MSA_3RF_DESC_BASE<"fdiv.d", fdiv, MSA128DOpnd>; 2031 2032 class FEXDO_H_DESC : MSA_3RF_DESC_BASE<"fexdo.h", int_mips_fexdo_h, 2033 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>; 2034 class FEXDO_W_DESC : MSA_3RF_DESC_BASE<"fexdo.w", int_mips_fexdo_w, 2035 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>; 2036 2037 // The fexp2.df instruction multiplies the first operand by 2 to the power of 2038 // the second operand. We therefore need a pseudo-insn in order to invent the 2039 // 1.0 when we only need to match ISD::FEXP2. 2040 class FEXP2_W_DESC : MSA_3RF_DESC_BASE<"fexp2.w", mul_fexp2, MSA128WOpnd>; 2041 class FEXP2_D_DESC : MSA_3RF_DESC_BASE<"fexp2.d", mul_fexp2, MSA128DOpnd>; 2042 let usesCustomInserter = 1 in { 2043 class FEXP2_W_1_PSEUDO_DESC : 2044 MSAPseudo<(outs MSA128W:$wd), (ins MSA128W:$ws), 2045 [(set MSA128W:$wd, (fexp2 MSA128W:$ws))]>; 2046 class FEXP2_D_1_PSEUDO_DESC : 2047 MSAPseudo<(outs MSA128D:$wd), (ins MSA128D:$ws), 2048 [(set MSA128D:$wd, (fexp2 MSA128D:$ws))]>; 2049 } 2050 2051 class FEXUPL_W_DESC : MSA_2RF_DESC_BASE<"fexupl.w", int_mips_fexupl_w, 2052 MSA128WOpnd, MSA128HOpnd>; 2053 class FEXUPL_D_DESC : MSA_2RF_DESC_BASE<"fexupl.d", int_mips_fexupl_d, 2054 MSA128DOpnd, MSA128WOpnd>; 2055 2056 class FEXUPR_W_DESC : MSA_2RF_DESC_BASE<"fexupr.w", int_mips_fexupr_w, 2057 MSA128WOpnd, MSA128HOpnd>; 2058 class FEXUPR_D_DESC : MSA_2RF_DESC_BASE<"fexupr.d", int_mips_fexupr_d, 2059 MSA128DOpnd, MSA128WOpnd>; 2060 2061 class FFINT_S_W_DESC : MSA_2RF_DESC_BASE<"ffint_s.w", sint_to_fp, MSA128WOpnd>; 2062 class FFINT_S_D_DESC : MSA_2RF_DESC_BASE<"ffint_s.d", sint_to_fp, MSA128DOpnd>; 2063 2064 class FFINT_U_W_DESC : MSA_2RF_DESC_BASE<"ffint_u.w", uint_to_fp, MSA128WOpnd>; 2065 class FFINT_U_D_DESC : MSA_2RF_DESC_BASE<"ffint_u.d", uint_to_fp, MSA128DOpnd>; 2066 2067 class FFQL_W_DESC : MSA_2RF_DESC_BASE<"ffql.w", int_mips_ffql_w, 2068 MSA128WOpnd, MSA128HOpnd>; 2069 class FFQL_D_DESC : MSA_2RF_DESC_BASE<"ffql.d", int_mips_ffql_d, 2070 MSA128DOpnd, MSA128WOpnd>; 2071 2072 class FFQR_W_DESC : MSA_2RF_DESC_BASE<"ffqr.w", int_mips_ffqr_w, 2073 MSA128WOpnd, MSA128HOpnd>; 2074 class FFQR_D_DESC : MSA_2RF_DESC_BASE<"ffqr.d", int_mips_ffqr_d, 2075 MSA128DOpnd, MSA128WOpnd>; 2076 2077 class FILL_B_DESC : MSA_2R_FILL_DESC_BASE<"fill.b", v16i8, vsplati8, 2078 MSA128BOpnd, GPR32Opnd>; 2079 class FILL_H_DESC : MSA_2R_FILL_DESC_BASE<"fill.h", v8i16, vsplati16, 2080 MSA128HOpnd, GPR32Opnd>; 2081 class FILL_W_DESC : MSA_2R_FILL_DESC_BASE<"fill.w", v4i32, vsplati32, 2082 MSA128WOpnd, GPR32Opnd>; 2083 class FILL_D_DESC : MSA_2R_FILL_DESC_BASE<"fill.d", v2i64, vsplati64, 2084 MSA128DOpnd, GPR64Opnd>; 2085 2086 class FILL_FW_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v4f32, vsplatf32, MSA128W, 2087 FGR32>; 2088 class FILL_FD_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v2f64, vsplatf64, MSA128D, 2089 FGR64>; 2090 2091 class FLOG2_W_DESC : MSA_2RF_DESC_BASE<"flog2.w", flog2, MSA128WOpnd>; 2092 class FLOG2_D_DESC : MSA_2RF_DESC_BASE<"flog2.d", flog2, MSA128DOpnd>; 2093 2094 class FMADD_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.w", fma, MSA128WOpnd>; 2095 class FMADD_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.d", fma, MSA128DOpnd>; 2096 2097 class FMAX_W_DESC : MSA_3RF_DESC_BASE<"fmax.w", int_mips_fmax_w, MSA128WOpnd>; 2098 class FMAX_D_DESC : MSA_3RF_DESC_BASE<"fmax.d", int_mips_fmax_d, MSA128DOpnd>; 2099 2100 class FMAX_A_W_DESC : MSA_3RF_DESC_BASE<"fmax_a.w", int_mips_fmax_a_w, 2101 MSA128WOpnd>; 2102 class FMAX_A_D_DESC : MSA_3RF_DESC_BASE<"fmax_a.d", int_mips_fmax_a_d, 2103 MSA128DOpnd>; 2104 2105 class FMIN_W_DESC : MSA_3RF_DESC_BASE<"fmin.w", int_mips_fmin_w, MSA128WOpnd>; 2106 class FMIN_D_DESC : MSA_3RF_DESC_BASE<"fmin.d", int_mips_fmin_d, MSA128DOpnd>; 2107 2108 class FMIN_A_W_DESC : MSA_3RF_DESC_BASE<"fmin_a.w", int_mips_fmin_a_w, 2109 MSA128WOpnd>; 2110 class FMIN_A_D_DESC : MSA_3RF_DESC_BASE<"fmin_a.d", int_mips_fmin_a_d, 2111 MSA128DOpnd>; 2112 2113 class FMSUB_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.w", fms, MSA128WOpnd>; 2114 class FMSUB_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.d", fms, MSA128DOpnd>; 2115 2116 class FMUL_W_DESC : MSA_3RF_DESC_BASE<"fmul.w", fmul, MSA128WOpnd>; 2117 class FMUL_D_DESC : MSA_3RF_DESC_BASE<"fmul.d", fmul, MSA128DOpnd>; 2118 2119 class FRINT_W_DESC : MSA_2RF_DESC_BASE<"frint.w", frint, MSA128WOpnd>; 2120 class FRINT_D_DESC : MSA_2RF_DESC_BASE<"frint.d", frint, MSA128DOpnd>; 2121 2122 class FRCP_W_DESC : MSA_2RF_DESC_BASE<"frcp.w", int_mips_frcp_w, MSA128WOpnd>; 2123 class FRCP_D_DESC : MSA_2RF_DESC_BASE<"frcp.d", int_mips_frcp_d, MSA128DOpnd>; 2124 2125 class FRSQRT_W_DESC : MSA_2RF_DESC_BASE<"frsqrt.w", int_mips_frsqrt_w, 2126 MSA128WOpnd>; 2127 class FRSQRT_D_DESC : MSA_2RF_DESC_BASE<"frsqrt.d", int_mips_frsqrt_d, 2128 MSA128DOpnd>; 2129 2130 class FSAF_W_DESC : MSA_3RF_DESC_BASE<"fsaf.w", int_mips_fsaf_w, MSA128WOpnd>; 2131 class FSAF_D_DESC : MSA_3RF_DESC_BASE<"fsaf.d", int_mips_fsaf_d, MSA128DOpnd>; 2132 2133 class FSEQ_W_DESC : MSA_3RF_DESC_BASE<"fseq.w", int_mips_fseq_w, MSA128WOpnd>; 2134 class FSEQ_D_DESC : MSA_3RF_DESC_BASE<"fseq.d", int_mips_fseq_d, MSA128DOpnd>; 2135 2136 class FSLE_W_DESC : MSA_3RF_DESC_BASE<"fsle.w", int_mips_fsle_w, MSA128WOpnd>; 2137 class FSLE_D_DESC : MSA_3RF_DESC_BASE<"fsle.d", int_mips_fsle_d, MSA128DOpnd>; 2138 2139 class FSLT_W_DESC : MSA_3RF_DESC_BASE<"fslt.w", int_mips_fslt_w, MSA128WOpnd>; 2140 class FSLT_D_DESC : MSA_3RF_DESC_BASE<"fslt.d", int_mips_fslt_d, MSA128DOpnd>; 2141 2142 class FSNE_W_DESC : MSA_3RF_DESC_BASE<"fsne.w", int_mips_fsne_w, MSA128WOpnd>; 2143 class FSNE_D_DESC : MSA_3RF_DESC_BASE<"fsne.d", int_mips_fsne_d, MSA128DOpnd>; 2144 2145 class FSOR_W_DESC : MSA_3RF_DESC_BASE<"fsor.w", int_mips_fsor_w, MSA128WOpnd>; 2146 class FSOR_D_DESC : MSA_3RF_DESC_BASE<"fsor.d", int_mips_fsor_d, MSA128DOpnd>; 2147 2148 class FSQRT_W_DESC : MSA_2RF_DESC_BASE<"fsqrt.w", fsqrt, MSA128WOpnd>; 2149 class FSQRT_D_DESC : MSA_2RF_DESC_BASE<"fsqrt.d", fsqrt, MSA128DOpnd>; 2150 2151 class FSUB_W_DESC : MSA_3RF_DESC_BASE<"fsub.w", fsub, MSA128WOpnd>; 2152 class FSUB_D_DESC : MSA_3RF_DESC_BASE<"fsub.d", fsub, MSA128DOpnd>; 2153 2154 class FSUEQ_W_DESC : MSA_3RF_DESC_BASE<"fsueq.w", int_mips_fsueq_w, 2155 MSA128WOpnd>; 2156 class FSUEQ_D_DESC : MSA_3RF_DESC_BASE<"fsueq.d", int_mips_fsueq_d, 2157 MSA128DOpnd>; 2158 2159 class FSULE_W_DESC : MSA_3RF_DESC_BASE<"fsule.w", int_mips_fsule_w, 2160 MSA128WOpnd>; 2161 class FSULE_D_DESC : MSA_3RF_DESC_BASE<"fsule.d", int_mips_fsule_d, 2162 MSA128DOpnd>; 2163 2164 class FSULT_W_DESC : MSA_3RF_DESC_BASE<"fsult.w", int_mips_fsult_w, 2165 MSA128WOpnd>; 2166 class FSULT_D_DESC : MSA_3RF_DESC_BASE<"fsult.d", int_mips_fsult_d, 2167 MSA128DOpnd>; 2168 2169 class FSUN_W_DESC : MSA_3RF_DESC_BASE<"fsun.w", int_mips_fsun_w, 2170 MSA128WOpnd>; 2171 class FSUN_D_DESC : MSA_3RF_DESC_BASE<"fsun.d", int_mips_fsun_d, 2172 MSA128DOpnd>; 2173 2174 class FSUNE_W_DESC : MSA_3RF_DESC_BASE<"fsune.w", int_mips_fsune_w, 2175 MSA128WOpnd>; 2176 class FSUNE_D_DESC : MSA_3RF_DESC_BASE<"fsune.d", int_mips_fsune_d, 2177 MSA128DOpnd>; 2178 2179 class FTINT_S_W_DESC : MSA_2RF_DESC_BASE<"ftint_s.w", int_mips_ftint_s_w, 2180 MSA128WOpnd>; 2181 class FTINT_S_D_DESC : MSA_2RF_DESC_BASE<"ftint_s.d", int_mips_ftint_s_d, 2182 MSA128DOpnd>; 2183 2184 class FTINT_U_W_DESC : MSA_2RF_DESC_BASE<"ftint_u.w", int_mips_ftint_u_w, 2185 MSA128WOpnd>; 2186 class FTINT_U_D_DESC : MSA_2RF_DESC_BASE<"ftint_u.d", int_mips_ftint_u_d, 2187 MSA128DOpnd>; 2188 2189 class FTQ_H_DESC : MSA_3RF_DESC_BASE<"ftq.h", int_mips_ftq_h, 2190 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>; 2191 class FTQ_W_DESC : MSA_3RF_DESC_BASE<"ftq.w", int_mips_ftq_w, 2192 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>; 2193 2194 class FTRUNC_S_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.w", fp_to_sint, 2195 MSA128WOpnd>; 2196 class FTRUNC_S_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.d", fp_to_sint, 2197 MSA128DOpnd>; 2198 2199 class FTRUNC_U_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.w", fp_to_uint, 2200 MSA128WOpnd>; 2201 class FTRUNC_U_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.d", fp_to_uint, 2202 MSA128DOpnd>; 2203 2204 class HADD_S_H_DESC : MSA_3R_DESC_BASE<"hadd_s.h", int_mips_hadd_s_h, 2205 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; 2206 class HADD_S_W_DESC : MSA_3R_DESC_BASE<"hadd_s.w", int_mips_hadd_s_w, 2207 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; 2208 class HADD_S_D_DESC : MSA_3R_DESC_BASE<"hadd_s.d", int_mips_hadd_s_d, 2209 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; 2210 2211 class HADD_U_H_DESC : MSA_3R_DESC_BASE<"hadd_u.h", int_mips_hadd_u_h, 2212 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; 2213 class HADD_U_W_DESC : MSA_3R_DESC_BASE<"hadd_u.w", int_mips_hadd_u_w, 2214 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; 2215 class HADD_U_D_DESC : MSA_3R_DESC_BASE<"hadd_u.d", int_mips_hadd_u_d, 2216 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; 2217 2218 class HSUB_S_H_DESC : MSA_3R_DESC_BASE<"hsub_s.h", int_mips_hsub_s_h, 2219 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; 2220 class HSUB_S_W_DESC : MSA_3R_DESC_BASE<"hsub_s.w", int_mips_hsub_s_w, 2221 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; 2222 class HSUB_S_D_DESC : MSA_3R_DESC_BASE<"hsub_s.d", int_mips_hsub_s_d, 2223 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; 2224 2225 class HSUB_U_H_DESC : MSA_3R_DESC_BASE<"hsub_u.h", int_mips_hsub_u_h, 2226 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; 2227 class HSUB_U_W_DESC : MSA_3R_DESC_BASE<"hsub_u.w", int_mips_hsub_u_w, 2228 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; 2229 class HSUB_U_D_DESC : MSA_3R_DESC_BASE<"hsub_u.d", int_mips_hsub_u_d, 2230 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; 2231 2232 class ILVEV_B_DESC : MSA_3R_DESC_BASE<"ilvev.b", MipsILVEV, MSA128BOpnd>; 2233 class ILVEV_H_DESC : MSA_3R_DESC_BASE<"ilvev.h", MipsILVEV, MSA128HOpnd>; 2234 class ILVEV_W_DESC : MSA_3R_DESC_BASE<"ilvev.w", MipsILVEV, MSA128WOpnd>; 2235 class ILVEV_D_DESC : MSA_3R_DESC_BASE<"ilvev.d", MipsILVEV, MSA128DOpnd>; 2236 2237 class ILVL_B_DESC : MSA_3R_DESC_BASE<"ilvl.b", MipsILVL, MSA128BOpnd>; 2238 class ILVL_H_DESC : MSA_3R_DESC_BASE<"ilvl.h", MipsILVL, MSA128HOpnd>; 2239 class ILVL_W_DESC : MSA_3R_DESC_BASE<"ilvl.w", MipsILVL, MSA128WOpnd>; 2240 class ILVL_D_DESC : MSA_3R_DESC_BASE<"ilvl.d", MipsILVL, MSA128DOpnd>; 2241 2242 class ILVOD_B_DESC : MSA_3R_DESC_BASE<"ilvod.b", MipsILVOD, MSA128BOpnd>; 2243 class ILVOD_H_DESC : MSA_3R_DESC_BASE<"ilvod.h", MipsILVOD, MSA128HOpnd>; 2244 class ILVOD_W_DESC : MSA_3R_DESC_BASE<"ilvod.w", MipsILVOD, MSA128WOpnd>; 2245 class ILVOD_D_DESC : MSA_3R_DESC_BASE<"ilvod.d", MipsILVOD, MSA128DOpnd>; 2246 2247 class ILVR_B_DESC : MSA_3R_DESC_BASE<"ilvr.b", MipsILVR, MSA128BOpnd>; 2248 class ILVR_H_DESC : MSA_3R_DESC_BASE<"ilvr.h", MipsILVR, MSA128HOpnd>; 2249 class ILVR_W_DESC : MSA_3R_DESC_BASE<"ilvr.w", MipsILVR, MSA128WOpnd>; 2250 class ILVR_D_DESC : MSA_3R_DESC_BASE<"ilvr.d", MipsILVR, MSA128DOpnd>; 2251 2252 class INSERT_B_DESC : MSA_INSERT_DESC_BASE<"insert.b", vinsert_v16i8, 2253 MSA128BOpnd, GPR32Opnd>; 2254 class INSERT_H_DESC : MSA_INSERT_DESC_BASE<"insert.h", vinsert_v8i16, 2255 MSA128HOpnd, GPR32Opnd>; 2256 class INSERT_W_DESC : MSA_INSERT_DESC_BASE<"insert.w", vinsert_v4i32, 2257 MSA128WOpnd, GPR32Opnd>; 2258 class INSERT_D_DESC : MSA_INSERT_DESC_BASE<"insert.d", vinsert_v2i64, 2259 MSA128DOpnd, GPR64Opnd>; 2260 2261 class INSERT_B_VIDX_PSEUDO_DESC : 2262 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v16i8, MSA128BOpnd, GPR32Opnd, GPR32Opnd>; 2263 class INSERT_H_VIDX_PSEUDO_DESC : 2264 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v8i16, MSA128HOpnd, GPR32Opnd, GPR32Opnd>; 2265 class INSERT_W_VIDX_PSEUDO_DESC : 2266 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4i32, MSA128WOpnd, GPR32Opnd, GPR32Opnd>; 2267 class INSERT_D_VIDX_PSEUDO_DESC : 2268 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd, GPR32Opnd>; 2269 2270 class INSERT_FW_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v4f32, 2271 MSA128WOpnd, FGR32Opnd>; 2272 class INSERT_FD_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v2f64, 2273 MSA128DOpnd, FGR64Opnd>; 2274 2275 class INSERT_FW_VIDX_PSEUDO_DESC : 2276 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4f32, MSA128WOpnd, FGR32Opnd, GPR32Opnd>; 2277 class INSERT_FD_VIDX_PSEUDO_DESC : 2278 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2f64, MSA128DOpnd, FGR64Opnd, GPR32Opnd>; 2279 2280 class INSERT_B_VIDX64_PSEUDO_DESC : 2281 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v16i8, MSA128BOpnd, GPR32Opnd, GPR64Opnd>; 2282 class INSERT_H_VIDX64_PSEUDO_DESC : 2283 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v8i16, MSA128HOpnd, GPR32Opnd, GPR64Opnd>; 2284 class INSERT_W_VIDX64_PSEUDO_DESC : 2285 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4i32, MSA128WOpnd, GPR32Opnd, GPR64Opnd>; 2286 class INSERT_D_VIDX64_PSEUDO_DESC : 2287 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd, GPR64Opnd>; 2288 2289 class INSERT_FW_VIDX64_PSEUDO_DESC : 2290 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4f32, MSA128WOpnd, FGR32Opnd, GPR64Opnd>; 2291 class INSERT_FD_VIDX64_PSEUDO_DESC : 2292 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2f64, MSA128DOpnd, FGR64Opnd, GPR64Opnd>; 2293 2294 class INSVE_B_DESC : MSA_INSVE_DESC_BASE<"insve.b", insve_v16i8, uimm4, immZExt4, 2295 MSA128BOpnd>; 2296 class INSVE_H_DESC : MSA_INSVE_DESC_BASE<"insve.h", insve_v8i16, uimm3, immZExt3, 2297 MSA128HOpnd>; 2298 class INSVE_W_DESC : MSA_INSVE_DESC_BASE<"insve.w", insve_v4i32, uimm2, immZExt2, 2299 MSA128WOpnd>; 2300 class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", insve_v2i64, uimm1, immZExt1, 2301 MSA128DOpnd>; 2302 2303 class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 2304 ValueType TyNode, RegisterOperand ROWD, 2305 Operand MemOpnd = mem_msa, ComplexPattern Addr = addrimm10, 2306 InstrItinClass itin = NoItinerary> { 2307 dag OutOperandList = (outs ROWD:$wd); 2308 dag InOperandList = (ins MemOpnd:$addr); 2309 string AsmString = !strconcat(instr_asm, "\t$wd, $addr"); 2310 list<dag> Pattern = [(set ROWD:$wd, (TyNode (OpNode Addr:$addr)))]; 2311 InstrItinClass Itinerary = itin; 2312 string DecoderMethod = "DecodeMSA128Mem"; 2313 } 2314 2315 class LD_B_DESC : LD_DESC_BASE<"ld.b", load, v16i8, MSA128BOpnd>; 2316 class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, MSA128HOpnd>; 2317 class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, MSA128WOpnd>; 2318 class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, MSA128DOpnd>; 2319 2320 class LDI_B_DESC : MSA_I10_LDI_DESC_BASE<"ldi.b", MSA128BOpnd>; 2321 class LDI_H_DESC : MSA_I10_LDI_DESC_BASE<"ldi.h", MSA128HOpnd>; 2322 class LDI_W_DESC : MSA_I10_LDI_DESC_BASE<"ldi.w", MSA128WOpnd>; 2323 class LDI_D_DESC : MSA_I10_LDI_DESC_BASE<"ldi.d", MSA128DOpnd>; 2324 2325 class LSA_DESC_BASE<string instr_asm, RegisterOperand RORD, 2326 RegisterOperand RORS = RORD, RegisterOperand RORT = RORD, 2327 InstrItinClass itin = NoItinerary > { 2328 dag OutOperandList = (outs RORD:$rd); 2329 dag InOperandList = (ins RORS:$rs, RORT:$rt, uimm2_plus1:$sa); 2330 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $sa"); 2331 list<dag> Pattern = [(set RORD:$rd, (add RORT:$rt, 2332 (shl RORS:$rs, 2333 immZExt2Lsa:$sa)))]; 2334 InstrItinClass Itinerary = itin; 2335 } 2336 2337 class LSA_DESC : LSA_DESC_BASE<"lsa", GPR32Opnd>; 2338 class DLSA_DESC : LSA_DESC_BASE<"dlsa", GPR64Opnd>; 2339 2340 class MADD_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.h", int_mips_madd_q_h, 2341 MSA128HOpnd>; 2342 class MADD_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.w", int_mips_madd_q_w, 2343 MSA128WOpnd>; 2344 2345 class MADDR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.h", int_mips_maddr_q_h, 2346 MSA128HOpnd>; 2347 class MADDR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.w", int_mips_maddr_q_w, 2348 MSA128WOpnd>; 2349 2350 class MADDV_B_DESC : MSA_3R_4R_DESC_BASE<"maddv.b", muladd, MSA128BOpnd>; 2351 class MADDV_H_DESC : MSA_3R_4R_DESC_BASE<"maddv.h", muladd, MSA128HOpnd>; 2352 class MADDV_W_DESC : MSA_3R_4R_DESC_BASE<"maddv.w", muladd, MSA128WOpnd>; 2353 class MADDV_D_DESC : MSA_3R_4R_DESC_BASE<"maddv.d", muladd, MSA128DOpnd>; 2354 2355 class MAX_A_B_DESC : MSA_3R_DESC_BASE<"max_a.b", int_mips_max_a_b, MSA128BOpnd>; 2356 class MAX_A_H_DESC : MSA_3R_DESC_BASE<"max_a.h", int_mips_max_a_h, MSA128HOpnd>; 2357 class MAX_A_W_DESC : MSA_3R_DESC_BASE<"max_a.w", int_mips_max_a_w, MSA128WOpnd>; 2358 class MAX_A_D_DESC : MSA_3R_DESC_BASE<"max_a.d", int_mips_max_a_d, MSA128DOpnd>; 2359 2360 class MAX_S_B_DESC : MSA_3R_DESC_BASE<"max_s.b", MipsVSMax, MSA128BOpnd>; 2361 class MAX_S_H_DESC : MSA_3R_DESC_BASE<"max_s.h", MipsVSMax, MSA128HOpnd>; 2362 class MAX_S_W_DESC : MSA_3R_DESC_BASE<"max_s.w", MipsVSMax, MSA128WOpnd>; 2363 class MAX_S_D_DESC : MSA_3R_DESC_BASE<"max_s.d", MipsVSMax, MSA128DOpnd>; 2364 2365 class MAX_U_B_DESC : MSA_3R_DESC_BASE<"max_u.b", MipsVUMax, MSA128BOpnd>; 2366 class MAX_U_H_DESC : MSA_3R_DESC_BASE<"max_u.h", MipsVUMax, MSA128HOpnd>; 2367 class MAX_U_W_DESC : MSA_3R_DESC_BASE<"max_u.w", MipsVUMax, MSA128WOpnd>; 2368 class MAX_U_D_DESC : MSA_3R_DESC_BASE<"max_u.d", MipsVUMax, MSA128DOpnd>; 2369 2370 class MAXI_S_B_DESC : MSA_I5_DESC_BASE<"maxi_s.b", MipsVSMax, vsplati8_simm5, 2371 MSA128BOpnd>; 2372 class MAXI_S_H_DESC : MSA_I5_DESC_BASE<"maxi_s.h", MipsVSMax, vsplati16_simm5, 2373 MSA128HOpnd>; 2374 class MAXI_S_W_DESC : MSA_I5_DESC_BASE<"maxi_s.w", MipsVSMax, vsplati32_simm5, 2375 MSA128WOpnd>; 2376 class MAXI_S_D_DESC : MSA_I5_DESC_BASE<"maxi_s.d", MipsVSMax, vsplati64_simm5, 2377 MSA128DOpnd>; 2378 2379 class MAXI_U_B_DESC : MSA_I5_DESC_BASE<"maxi_u.b", MipsVUMax, vsplati8_uimm5, 2380 MSA128BOpnd>; 2381 class MAXI_U_H_DESC : MSA_I5_DESC_BASE<"maxi_u.h", MipsVUMax, vsplati16_uimm5, 2382 MSA128HOpnd>; 2383 class MAXI_U_W_DESC : MSA_I5_DESC_BASE<"maxi_u.w", MipsVUMax, vsplati32_uimm5, 2384 MSA128WOpnd>; 2385 class MAXI_U_D_DESC : MSA_I5_DESC_BASE<"maxi_u.d", MipsVUMax, vsplati64_uimm5, 2386 MSA128DOpnd>; 2387 2388 class MIN_A_B_DESC : MSA_3R_DESC_BASE<"min_a.b", int_mips_min_a_b, MSA128BOpnd>; 2389 class MIN_A_H_DESC : MSA_3R_DESC_BASE<"min_a.h", int_mips_min_a_h, MSA128HOpnd>; 2390 class MIN_A_W_DESC : MSA_3R_DESC_BASE<"min_a.w", int_mips_min_a_w, MSA128WOpnd>; 2391 class MIN_A_D_DESC : MSA_3R_DESC_BASE<"min_a.d", int_mips_min_a_d, MSA128DOpnd>; 2392 2393 class MIN_S_B_DESC : MSA_3R_DESC_BASE<"min_s.b", MipsVSMin, MSA128BOpnd>; 2394 class MIN_S_H_DESC : MSA_3R_DESC_BASE<"min_s.h", MipsVSMin, MSA128HOpnd>; 2395 class MIN_S_W_DESC : MSA_3R_DESC_BASE<"min_s.w", MipsVSMin, MSA128WOpnd>; 2396 class MIN_S_D_DESC : MSA_3R_DESC_BASE<"min_s.d", MipsVSMin, MSA128DOpnd>; 2397 2398 class MIN_U_B_DESC : MSA_3R_DESC_BASE<"min_u.b", MipsVUMin, MSA128BOpnd>; 2399 class MIN_U_H_DESC : MSA_3R_DESC_BASE<"min_u.h", MipsVUMin, MSA128HOpnd>; 2400 class MIN_U_W_DESC : MSA_3R_DESC_BASE<"min_u.w", MipsVUMin, MSA128WOpnd>; 2401 class MIN_U_D_DESC : MSA_3R_DESC_BASE<"min_u.d", MipsVUMin, MSA128DOpnd>; 2402 2403 class MINI_S_B_DESC : MSA_I5_DESC_BASE<"mini_s.b", MipsVSMin, vsplati8_simm5, 2404 MSA128BOpnd>; 2405 class MINI_S_H_DESC : MSA_I5_DESC_BASE<"mini_s.h", MipsVSMin, vsplati16_simm5, 2406 MSA128HOpnd>; 2407 class MINI_S_W_DESC : MSA_I5_DESC_BASE<"mini_s.w", MipsVSMin, vsplati32_simm5, 2408 MSA128WOpnd>; 2409 class MINI_S_D_DESC : MSA_I5_DESC_BASE<"mini_s.d", MipsVSMin, vsplati64_simm5, 2410 MSA128DOpnd>; 2411 2412 class MINI_U_B_DESC : MSA_I5_DESC_BASE<"mini_u.b", MipsVUMin, vsplati8_uimm5, 2413 MSA128BOpnd>; 2414 class MINI_U_H_DESC : MSA_I5_DESC_BASE<"mini_u.h", MipsVUMin, vsplati16_uimm5, 2415 MSA128HOpnd>; 2416 class MINI_U_W_DESC : MSA_I5_DESC_BASE<"mini_u.w", MipsVUMin, vsplati32_uimm5, 2417 MSA128WOpnd>; 2418 class MINI_U_D_DESC : MSA_I5_DESC_BASE<"mini_u.d", MipsVUMin, vsplati64_uimm5, 2419 MSA128DOpnd>; 2420 2421 class MOD_S_B_DESC : MSA_3R_DESC_BASE<"mod_s.b", srem, MSA128BOpnd>; 2422 class MOD_S_H_DESC : MSA_3R_DESC_BASE<"mod_s.h", srem, MSA128HOpnd>; 2423 class MOD_S_W_DESC : MSA_3R_DESC_BASE<"mod_s.w", srem, MSA128WOpnd>; 2424 class MOD_S_D_DESC : MSA_3R_DESC_BASE<"mod_s.d", srem, MSA128DOpnd>; 2425 2426 class MOD_U_B_DESC : MSA_3R_DESC_BASE<"mod_u.b", urem, MSA128BOpnd>; 2427 class MOD_U_H_DESC : MSA_3R_DESC_BASE<"mod_u.h", urem, MSA128HOpnd>; 2428 class MOD_U_W_DESC : MSA_3R_DESC_BASE<"mod_u.w", urem, MSA128WOpnd>; 2429 class MOD_U_D_DESC : MSA_3R_DESC_BASE<"mod_u.d", urem, MSA128DOpnd>; 2430 2431 class MOVE_V_DESC { 2432 dag OutOperandList = (outs MSA128BOpnd:$wd); 2433 dag InOperandList = (ins MSA128BOpnd:$ws); 2434 string AsmString = "move.v\t$wd, $ws"; 2435 list<dag> Pattern = []; 2436 InstrItinClass Itinerary = NoItinerary; 2437 } 2438 2439 class MSUB_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.h", int_mips_msub_q_h, 2440 MSA128HOpnd>; 2441 class MSUB_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.w", int_mips_msub_q_w, 2442 MSA128WOpnd>; 2443 2444 class MSUBR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.h", int_mips_msubr_q_h, 2445 MSA128HOpnd>; 2446 class MSUBR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.w", int_mips_msubr_q_w, 2447 MSA128WOpnd>; 2448 2449 class MSUBV_B_DESC : MSA_3R_4R_DESC_BASE<"msubv.b", mulsub, MSA128BOpnd>; 2450 class MSUBV_H_DESC : MSA_3R_4R_DESC_BASE<"msubv.h", mulsub, MSA128HOpnd>; 2451 class MSUBV_W_DESC : MSA_3R_4R_DESC_BASE<"msubv.w", mulsub, MSA128WOpnd>; 2452 class MSUBV_D_DESC : MSA_3R_4R_DESC_BASE<"msubv.d", mulsub, MSA128DOpnd>; 2453 2454 class MUL_Q_H_DESC : MSA_3RF_DESC_BASE<"mul_q.h", int_mips_mul_q_h, 2455 MSA128HOpnd>; 2456 class MUL_Q_W_DESC : MSA_3RF_DESC_BASE<"mul_q.w", int_mips_mul_q_w, 2457 MSA128WOpnd>; 2458 2459 class MULR_Q_H_DESC : MSA_3RF_DESC_BASE<"mulr_q.h", int_mips_mulr_q_h, 2460 MSA128HOpnd>; 2461 class MULR_Q_W_DESC : MSA_3RF_DESC_BASE<"mulr_q.w", int_mips_mulr_q_w, 2462 MSA128WOpnd>; 2463 2464 class MULV_B_DESC : MSA_3R_DESC_BASE<"mulv.b", mul, MSA128BOpnd>; 2465 class MULV_H_DESC : MSA_3R_DESC_BASE<"mulv.h", mul, MSA128HOpnd>; 2466 class MULV_W_DESC : MSA_3R_DESC_BASE<"mulv.w", mul, MSA128WOpnd>; 2467 class MULV_D_DESC : MSA_3R_DESC_BASE<"mulv.d", mul, MSA128DOpnd>; 2468 2469 class NLOC_B_DESC : MSA_2R_DESC_BASE<"nloc.b", int_mips_nloc_b, MSA128BOpnd>; 2470 class NLOC_H_DESC : MSA_2R_DESC_BASE<"nloc.h", int_mips_nloc_h, MSA128HOpnd>; 2471 class NLOC_W_DESC : MSA_2R_DESC_BASE<"nloc.w", int_mips_nloc_w, MSA128WOpnd>; 2472 class NLOC_D_DESC : MSA_2R_DESC_BASE<"nloc.d", int_mips_nloc_d, MSA128DOpnd>; 2473 2474 class NLZC_B_DESC : MSA_2R_DESC_BASE<"nlzc.b", ctlz, MSA128BOpnd>; 2475 class NLZC_H_DESC : MSA_2R_DESC_BASE<"nlzc.h", ctlz, MSA128HOpnd>; 2476 class NLZC_W_DESC : MSA_2R_DESC_BASE<"nlzc.w", ctlz, MSA128WOpnd>; 2477 class NLZC_D_DESC : MSA_2R_DESC_BASE<"nlzc.d", ctlz, MSA128DOpnd>; 2478 2479 class NOR_V_DESC : MSA_VEC_DESC_BASE<"nor.v", MipsVNOR, MSA128BOpnd>; 2480 class NOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128HOpnd>; 2481 class NOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128WOpnd>; 2482 class NOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128DOpnd>; 2483 2484 class NORI_B_DESC : MSA_I8_DESC_BASE<"nori.b", MipsVNOR, vsplati8_uimm8, 2485 MSA128BOpnd>; 2486 2487 class OR_V_DESC : MSA_VEC_DESC_BASE<"or.v", or, MSA128BOpnd>; 2488 class OR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128HOpnd>; 2489 class OR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128WOpnd>; 2490 class OR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128DOpnd>; 2491 2492 class ORI_B_DESC : MSA_I8_DESC_BASE<"ori.b", or, vsplati8_uimm8, MSA128BOpnd>; 2493 2494 class PCKEV_B_DESC : MSA_3R_DESC_BASE<"pckev.b", MipsPCKEV, MSA128BOpnd>; 2495 class PCKEV_H_DESC : MSA_3R_DESC_BASE<"pckev.h", MipsPCKEV, MSA128HOpnd>; 2496 class PCKEV_W_DESC : MSA_3R_DESC_BASE<"pckev.w", MipsPCKEV, MSA128WOpnd>; 2497 class PCKEV_D_DESC : MSA_3R_DESC_BASE<"pckev.d", MipsPCKEV, MSA128DOpnd>; 2498 2499 class PCKOD_B_DESC : MSA_3R_DESC_BASE<"pckod.b", MipsPCKOD, MSA128BOpnd>; 2500 class PCKOD_H_DESC : MSA_3R_DESC_BASE<"pckod.h", MipsPCKOD, MSA128HOpnd>; 2501 class PCKOD_W_DESC : MSA_3R_DESC_BASE<"pckod.w", MipsPCKOD, MSA128WOpnd>; 2502 class PCKOD_D_DESC : MSA_3R_DESC_BASE<"pckod.d", MipsPCKOD, MSA128DOpnd>; 2503 2504 class PCNT_B_DESC : MSA_2R_DESC_BASE<"pcnt.b", ctpop, MSA128BOpnd>; 2505 class PCNT_H_DESC : MSA_2R_DESC_BASE<"pcnt.h", ctpop, MSA128HOpnd>; 2506 class PCNT_W_DESC : MSA_2R_DESC_BASE<"pcnt.w", ctpop, MSA128WOpnd>; 2507 class PCNT_D_DESC : MSA_2R_DESC_BASE<"pcnt.d", ctpop, MSA128DOpnd>; 2508 2509 class SAT_S_B_DESC : MSA_BIT_X_DESC_BASE<"sat_s.b", int_mips_sat_s_b, uimm3, 2510 immZExt3, MSA128BOpnd>; 2511 class SAT_S_H_DESC : MSA_BIT_X_DESC_BASE<"sat_s.h", int_mips_sat_s_h, uimm4, 2512 immZExt4, MSA128HOpnd>; 2513 class SAT_S_W_DESC : MSA_BIT_X_DESC_BASE<"sat_s.w", int_mips_sat_s_w, uimm5, 2514 immZExt5, MSA128WOpnd>; 2515 class SAT_S_D_DESC : MSA_BIT_X_DESC_BASE<"sat_s.d", int_mips_sat_s_d, uimm6, 2516 immZExt6, MSA128DOpnd>; 2517 2518 class SAT_U_B_DESC : MSA_BIT_X_DESC_BASE<"sat_u.b", int_mips_sat_u_b, uimm3, 2519 immZExt3, MSA128BOpnd>; 2520 class SAT_U_H_DESC : MSA_BIT_X_DESC_BASE<"sat_u.h", int_mips_sat_u_h, uimm4, 2521 immZExt4, MSA128HOpnd>; 2522 class SAT_U_W_DESC : MSA_BIT_X_DESC_BASE<"sat_u.w", int_mips_sat_u_w, uimm5, 2523 immZExt5, MSA128WOpnd>; 2524 class SAT_U_D_DESC : MSA_BIT_X_DESC_BASE<"sat_u.d", int_mips_sat_u_d, uimm6, 2525 immZExt6, MSA128DOpnd>; 2526 2527 class SHF_B_DESC : MSA_I8_SHF_DESC_BASE<"shf.b", MSA128BOpnd>; 2528 class SHF_H_DESC : MSA_I8_SHF_DESC_BASE<"shf.h", MSA128HOpnd>; 2529 class SHF_W_DESC : MSA_I8_SHF_DESC_BASE<"shf.w", MSA128WOpnd>; 2530 2531 class SLD_B_DESC : MSA_3R_SLD_DESC_BASE<"sld.b", int_mips_sld_b, MSA128BOpnd>; 2532 class SLD_H_DESC : MSA_3R_SLD_DESC_BASE<"sld.h", int_mips_sld_h, MSA128HOpnd>; 2533 class SLD_W_DESC : MSA_3R_SLD_DESC_BASE<"sld.w", int_mips_sld_w, MSA128WOpnd>; 2534 class SLD_D_DESC : MSA_3R_SLD_DESC_BASE<"sld.d", int_mips_sld_d, MSA128DOpnd>; 2535 2536 class SLDI_B_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.b", int_mips_sldi_b, 2537 MSA128BOpnd, MSA128BOpnd, uimm4, 2538 immZExt4>; 2539 class SLDI_H_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.h", int_mips_sldi_h, 2540 MSA128HOpnd, MSA128HOpnd, uimm3, 2541 immZExt3>; 2542 class SLDI_W_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.w", int_mips_sldi_w, 2543 MSA128WOpnd, MSA128WOpnd, uimm2, 2544 immZExt2>; 2545 class SLDI_D_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.d", int_mips_sldi_d, 2546 MSA128DOpnd, MSA128DOpnd, uimm1, 2547 immZExt1>; 2548 2549 class SLL_B_DESC : MSA_3R_DESC_BASE<"sll.b", shl, MSA128BOpnd>; 2550 class SLL_H_DESC : MSA_3R_DESC_BASE<"sll.h", shl, MSA128HOpnd>; 2551 class SLL_W_DESC : MSA_3R_DESC_BASE<"sll.w", shl, MSA128WOpnd>; 2552 class SLL_D_DESC : MSA_3R_DESC_BASE<"sll.d", shl, MSA128DOpnd>; 2553 2554 class SLLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.b", shl, vsplati8_uimm3, 2555 MSA128BOpnd>; 2556 class SLLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.h", shl, vsplati16_uimm4, 2557 MSA128HOpnd>; 2558 class SLLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.w", shl, vsplati32_uimm5, 2559 MSA128WOpnd>; 2560 class SLLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.d", shl, vsplati64_uimm6, 2561 MSA128DOpnd>; 2562 2563 class SPLAT_B_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.b", vsplati8_elt, 2564 MSA128BOpnd>; 2565 class SPLAT_H_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.h", vsplati16_elt, 2566 MSA128HOpnd>; 2567 class SPLAT_W_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.w", vsplati32_elt, 2568 MSA128WOpnd>; 2569 class SPLAT_D_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.d", vsplati64_elt, 2570 MSA128DOpnd>; 2571 2572 class SPLATI_B_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.b", vsplati8_uimm4, 2573 MSA128BOpnd>; 2574 class SPLATI_H_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.h", vsplati16_uimm3, 2575 MSA128HOpnd>; 2576 class SPLATI_W_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.w", vsplati32_uimm2, 2577 MSA128WOpnd>; 2578 class SPLATI_D_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.d", vsplati64_uimm1, 2579 MSA128DOpnd>; 2580 2581 class SRA_B_DESC : MSA_3R_DESC_BASE<"sra.b", sra, MSA128BOpnd>; 2582 class SRA_H_DESC : MSA_3R_DESC_BASE<"sra.h", sra, MSA128HOpnd>; 2583 class SRA_W_DESC : MSA_3R_DESC_BASE<"sra.w", sra, MSA128WOpnd>; 2584 class SRA_D_DESC : MSA_3R_DESC_BASE<"sra.d", sra, MSA128DOpnd>; 2585 2586 class SRAI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.b", sra, vsplati8_uimm3, 2587 MSA128BOpnd>; 2588 class SRAI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.h", sra, vsplati16_uimm4, 2589 MSA128HOpnd>; 2590 class SRAI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.w", sra, vsplati32_uimm5, 2591 MSA128WOpnd>; 2592 class SRAI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.d", sra, vsplati64_uimm6, 2593 MSA128DOpnd>; 2594 2595 class SRAR_B_DESC : MSA_3R_DESC_BASE<"srar.b", int_mips_srar_b, MSA128BOpnd>; 2596 class SRAR_H_DESC : MSA_3R_DESC_BASE<"srar.h", int_mips_srar_h, MSA128HOpnd>; 2597 class SRAR_W_DESC : MSA_3R_DESC_BASE<"srar.w", int_mips_srar_w, MSA128WOpnd>; 2598 class SRAR_D_DESC : MSA_3R_DESC_BASE<"srar.d", int_mips_srar_d, MSA128DOpnd>; 2599 2600 class SRARI_B_DESC : MSA_BIT_X_DESC_BASE<"srari.b", int_mips_srari_b, uimm3, 2601 immZExt3, MSA128BOpnd>; 2602 class SRARI_H_DESC : MSA_BIT_X_DESC_BASE<"srari.h", int_mips_srari_h, uimm4, 2603 immZExt4, MSA128HOpnd>; 2604 class SRARI_W_DESC : MSA_BIT_X_DESC_BASE<"srari.w", int_mips_srari_w, uimm5, 2605 immZExt5, MSA128WOpnd>; 2606 class SRARI_D_DESC : MSA_BIT_X_DESC_BASE<"srari.d", int_mips_srari_d, uimm6, 2607 immZExt6, MSA128DOpnd>; 2608 2609 class SRL_B_DESC : MSA_3R_DESC_BASE<"srl.b", srl, MSA128BOpnd>; 2610 class SRL_H_DESC : MSA_3R_DESC_BASE<"srl.h", srl, MSA128HOpnd>; 2611 class SRL_W_DESC : MSA_3R_DESC_BASE<"srl.w", srl, MSA128WOpnd>; 2612 class SRL_D_DESC : MSA_3R_DESC_BASE<"srl.d", srl, MSA128DOpnd>; 2613 2614 class SRLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.b", srl, vsplati8_uimm3, 2615 MSA128BOpnd>; 2616 class SRLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.h", srl, vsplati16_uimm4, 2617 MSA128HOpnd>; 2618 class SRLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.w", srl, vsplati32_uimm5, 2619 MSA128WOpnd>; 2620 class SRLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.d", srl, vsplati64_uimm6, 2621 MSA128DOpnd>; 2622 2623 class SRLR_B_DESC : MSA_3R_DESC_BASE<"srlr.b", int_mips_srlr_b, MSA128BOpnd>; 2624 class SRLR_H_DESC : MSA_3R_DESC_BASE<"srlr.h", int_mips_srlr_h, MSA128HOpnd>; 2625 class SRLR_W_DESC : MSA_3R_DESC_BASE<"srlr.w", int_mips_srlr_w, MSA128WOpnd>; 2626 class SRLR_D_DESC : MSA_3R_DESC_BASE<"srlr.d", int_mips_srlr_d, MSA128DOpnd>; 2627 2628 class SRLRI_B_DESC : MSA_BIT_X_DESC_BASE<"srlri.b", int_mips_srlri_b, uimm3, 2629 immZExt3, MSA128BOpnd>; 2630 class SRLRI_H_DESC : MSA_BIT_X_DESC_BASE<"srlri.h", int_mips_srlri_h, uimm4, 2631 immZExt4, MSA128HOpnd>; 2632 class SRLRI_W_DESC : MSA_BIT_X_DESC_BASE<"srlri.w", int_mips_srlri_w, uimm5, 2633 immZExt5, MSA128WOpnd>; 2634 class SRLRI_D_DESC : MSA_BIT_X_DESC_BASE<"srlri.d", int_mips_srlri_d, uimm6, 2635 immZExt6, MSA128DOpnd>; 2636 2637 class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 2638 ValueType TyNode, RegisterOperand ROWD, 2639 Operand MemOpnd = mem_msa, ComplexPattern Addr = addrimm10, 2640 InstrItinClass itin = NoItinerary> { 2641 dag OutOperandList = (outs); 2642 dag InOperandList = (ins ROWD:$wd, MemOpnd:$addr); 2643 string AsmString = !strconcat(instr_asm, "\t$wd, $addr"); 2644 list<dag> Pattern = [(OpNode (TyNode ROWD:$wd), Addr:$addr)]; 2645 InstrItinClass Itinerary = itin; 2646 string DecoderMethod = "DecodeMSA128Mem"; 2647 } 2648 2649 class ST_B_DESC : ST_DESC_BASE<"st.b", store, v16i8, MSA128BOpnd>; 2650 class ST_H_DESC : ST_DESC_BASE<"st.h", store, v8i16, MSA128HOpnd>; 2651 class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, MSA128WOpnd>; 2652 class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, MSA128DOpnd>; 2653 2654 class SUBS_S_B_DESC : MSA_3R_DESC_BASE<"subs_s.b", int_mips_subs_s_b, 2655 MSA128BOpnd>; 2656 class SUBS_S_H_DESC : MSA_3R_DESC_BASE<"subs_s.h", int_mips_subs_s_h, 2657 MSA128HOpnd>; 2658 class SUBS_S_W_DESC : MSA_3R_DESC_BASE<"subs_s.w", int_mips_subs_s_w, 2659 MSA128WOpnd>; 2660 class SUBS_S_D_DESC : MSA_3R_DESC_BASE<"subs_s.d", int_mips_subs_s_d, 2661 MSA128DOpnd>; 2662 2663 class SUBS_U_B_DESC : MSA_3R_DESC_BASE<"subs_u.b", int_mips_subs_u_b, 2664 MSA128BOpnd>; 2665 class SUBS_U_H_DESC : MSA_3R_DESC_BASE<"subs_u.h", int_mips_subs_u_h, 2666 MSA128HOpnd>; 2667 class SUBS_U_W_DESC : MSA_3R_DESC_BASE<"subs_u.w", int_mips_subs_u_w, 2668 MSA128WOpnd>; 2669 class SUBS_U_D_DESC : MSA_3R_DESC_BASE<"subs_u.d", int_mips_subs_u_d, 2670 MSA128DOpnd>; 2671 2672 class SUBSUS_U_B_DESC : MSA_3R_DESC_BASE<"subsus_u.b", int_mips_subsus_u_b, 2673 MSA128BOpnd>; 2674 class SUBSUS_U_H_DESC : MSA_3R_DESC_BASE<"subsus_u.h", int_mips_subsus_u_h, 2675 MSA128HOpnd>; 2676 class SUBSUS_U_W_DESC : MSA_3R_DESC_BASE<"subsus_u.w", int_mips_subsus_u_w, 2677 MSA128WOpnd>; 2678 class SUBSUS_U_D_DESC : MSA_3R_DESC_BASE<"subsus_u.d", int_mips_subsus_u_d, 2679 MSA128DOpnd>; 2680 2681 class SUBSUU_S_B_DESC : MSA_3R_DESC_BASE<"subsuu_s.b", int_mips_subsuu_s_b, 2682 MSA128BOpnd>; 2683 class SUBSUU_S_H_DESC : MSA_3R_DESC_BASE<"subsuu_s.h", int_mips_subsuu_s_h, 2684 MSA128HOpnd>; 2685 class SUBSUU_S_W_DESC : MSA_3R_DESC_BASE<"subsuu_s.w", int_mips_subsuu_s_w, 2686 MSA128WOpnd>; 2687 class SUBSUU_S_D_DESC : MSA_3R_DESC_BASE<"subsuu_s.d", int_mips_subsuu_s_d, 2688 MSA128DOpnd>; 2689 2690 class SUBV_B_DESC : MSA_3R_DESC_BASE<"subv.b", sub, MSA128BOpnd>; 2691 class SUBV_H_DESC : MSA_3R_DESC_BASE<"subv.h", sub, MSA128HOpnd>; 2692 class SUBV_W_DESC : MSA_3R_DESC_BASE<"subv.w", sub, MSA128WOpnd>; 2693 class SUBV_D_DESC : MSA_3R_DESC_BASE<"subv.d", sub, MSA128DOpnd>; 2694 2695 class SUBVI_B_DESC : MSA_I5_DESC_BASE<"subvi.b", sub, vsplati8_uimm5, 2696 MSA128BOpnd>; 2697 class SUBVI_H_DESC : MSA_I5_DESC_BASE<"subvi.h", sub, vsplati16_uimm5, 2698 MSA128HOpnd>; 2699 class SUBVI_W_DESC : MSA_I5_DESC_BASE<"subvi.w", sub, vsplati32_uimm5, 2700 MSA128WOpnd>; 2701 class SUBVI_D_DESC : MSA_I5_DESC_BASE<"subvi.d", sub, vsplati64_uimm5, 2702 MSA128DOpnd>; 2703 2704 class VSHF_B_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.b", MSA128BOpnd>; 2705 class VSHF_H_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.h", MSA128HOpnd>; 2706 class VSHF_W_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.w", MSA128WOpnd>; 2707 class VSHF_D_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.d", MSA128DOpnd>; 2708 2709 class XOR_V_DESC : MSA_VEC_DESC_BASE<"xor.v", xor, MSA128BOpnd>; 2710 class XOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128HOpnd>; 2711 class XOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128WOpnd>; 2712 class XOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128DOpnd>; 2713 2714 class XORI_B_DESC : MSA_I8_DESC_BASE<"xori.b", xor, vsplati8_uimm8, 2715 MSA128BOpnd>; 2716 2717 // Instruction defs. 2718 def ADD_A_B : ADD_A_B_ENC, ADD_A_B_DESC; 2719 def ADD_A_H : ADD_A_H_ENC, ADD_A_H_DESC; 2720 def ADD_A_W : ADD_A_W_ENC, ADD_A_W_DESC; 2721 def ADD_A_D : ADD_A_D_ENC, ADD_A_D_DESC; 2722 2723 def ADDS_A_B : ADDS_A_B_ENC, ADDS_A_B_DESC; 2724 def ADDS_A_H : ADDS_A_H_ENC, ADDS_A_H_DESC; 2725 def ADDS_A_W : ADDS_A_W_ENC, ADDS_A_W_DESC; 2726 def ADDS_A_D : ADDS_A_D_ENC, ADDS_A_D_DESC; 2727 2728 def ADDS_S_B : ADDS_S_B_ENC, ADDS_S_B_DESC; 2729 def ADDS_S_H : ADDS_S_H_ENC, ADDS_S_H_DESC; 2730 def ADDS_S_W : ADDS_S_W_ENC, ADDS_S_W_DESC; 2731 def ADDS_S_D : ADDS_S_D_ENC, ADDS_S_D_DESC; 2732 2733 def ADDS_U_B : ADDS_U_B_ENC, ADDS_U_B_DESC; 2734 def ADDS_U_H : ADDS_U_H_ENC, ADDS_U_H_DESC; 2735 def ADDS_U_W : ADDS_U_W_ENC, ADDS_U_W_DESC; 2736 def ADDS_U_D : ADDS_U_D_ENC, ADDS_U_D_DESC; 2737 2738 def ADDV_B : ADDV_B_ENC, ADDV_B_DESC; 2739 def ADDV_H : ADDV_H_ENC, ADDV_H_DESC; 2740 def ADDV_W : ADDV_W_ENC, ADDV_W_DESC; 2741 def ADDV_D : ADDV_D_ENC, ADDV_D_DESC; 2742 2743 def ADDVI_B : ADDVI_B_ENC, ADDVI_B_DESC; 2744 def ADDVI_H : ADDVI_H_ENC, ADDVI_H_DESC; 2745 def ADDVI_W : ADDVI_W_ENC, ADDVI_W_DESC; 2746 def ADDVI_D : ADDVI_D_ENC, ADDVI_D_DESC; 2747 2748 def AND_V : AND_V_ENC, AND_V_DESC; 2749 def AND_V_H_PSEUDO : AND_V_H_PSEUDO_DESC, 2750 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd, 2751 MSA128BOpnd:$ws, 2752 MSA128BOpnd:$wt)>; 2753 def AND_V_W_PSEUDO : AND_V_W_PSEUDO_DESC, 2754 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd, 2755 MSA128BOpnd:$ws, 2756 MSA128BOpnd:$wt)>; 2757 def AND_V_D_PSEUDO : AND_V_D_PSEUDO_DESC, 2758 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd, 2759 MSA128BOpnd:$ws, 2760 MSA128BOpnd:$wt)>; 2761 2762 def ANDI_B : ANDI_B_ENC, ANDI_B_DESC; 2763 2764 def ASUB_S_B : ASUB_S_B_ENC, ASUB_S_B_DESC; 2765 def ASUB_S_H : ASUB_S_H_ENC, ASUB_S_H_DESC; 2766 def ASUB_S_W : ASUB_S_W_ENC, ASUB_S_W_DESC; 2767 def ASUB_S_D : ASUB_S_D_ENC, ASUB_S_D_DESC; 2768 2769 def ASUB_U_B : ASUB_U_B_ENC, ASUB_U_B_DESC; 2770 def ASUB_U_H : ASUB_U_H_ENC, ASUB_U_H_DESC; 2771 def ASUB_U_W : ASUB_U_W_ENC, ASUB_U_W_DESC; 2772 def ASUB_U_D : ASUB_U_D_ENC, ASUB_U_D_DESC; 2773 2774 def AVE_S_B : AVE_S_B_ENC, AVE_S_B_DESC; 2775 def AVE_S_H : AVE_S_H_ENC, AVE_S_H_DESC; 2776 def AVE_S_W : AVE_S_W_ENC, AVE_S_W_DESC; 2777 def AVE_S_D : AVE_S_D_ENC, AVE_S_D_DESC; 2778 2779 def AVE_U_B : AVE_U_B_ENC, AVE_U_B_DESC; 2780 def AVE_U_H : AVE_U_H_ENC, AVE_U_H_DESC; 2781 def AVE_U_W : AVE_U_W_ENC, AVE_U_W_DESC; 2782 def AVE_U_D : AVE_U_D_ENC, AVE_U_D_DESC; 2783 2784 def AVER_S_B : AVER_S_B_ENC, AVER_S_B_DESC; 2785 def AVER_S_H : AVER_S_H_ENC, AVER_S_H_DESC; 2786 def AVER_S_W : AVER_S_W_ENC, AVER_S_W_DESC; 2787 def AVER_S_D : AVER_S_D_ENC, AVER_S_D_DESC; 2788 2789 def AVER_U_B : AVER_U_B_ENC, AVER_U_B_DESC; 2790 def AVER_U_H : AVER_U_H_ENC, AVER_U_H_DESC; 2791 def AVER_U_W : AVER_U_W_ENC, AVER_U_W_DESC; 2792 def AVER_U_D : AVER_U_D_ENC, AVER_U_D_DESC; 2793 2794 def BCLR_B : BCLR_B_ENC, BCLR_B_DESC; 2795 def BCLR_H : BCLR_H_ENC, BCLR_H_DESC; 2796 def BCLR_W : BCLR_W_ENC, BCLR_W_DESC; 2797 def BCLR_D : BCLR_D_ENC, BCLR_D_DESC; 2798 2799 def BCLRI_B : BCLRI_B_ENC, BCLRI_B_DESC; 2800 def BCLRI_H : BCLRI_H_ENC, BCLRI_H_DESC; 2801 def BCLRI_W : BCLRI_W_ENC, BCLRI_W_DESC; 2802 def BCLRI_D : BCLRI_D_ENC, BCLRI_D_DESC; 2803 2804 def BINSL_B : BINSL_B_ENC, BINSL_B_DESC; 2805 def BINSL_H : BINSL_H_ENC, BINSL_H_DESC; 2806 def BINSL_W : BINSL_W_ENC, BINSL_W_DESC; 2807 def BINSL_D : BINSL_D_ENC, BINSL_D_DESC; 2808 2809 def BINSLI_B : BINSLI_B_ENC, BINSLI_B_DESC; 2810 def BINSLI_H : BINSLI_H_ENC, BINSLI_H_DESC; 2811 def BINSLI_W : BINSLI_W_ENC, BINSLI_W_DESC; 2812 def BINSLI_D : BINSLI_D_ENC, BINSLI_D_DESC; 2813 2814 def BINSR_B : BINSR_B_ENC, BINSR_B_DESC; 2815 def BINSR_H : BINSR_H_ENC, BINSR_H_DESC; 2816 def BINSR_W : BINSR_W_ENC, BINSR_W_DESC; 2817 def BINSR_D : BINSR_D_ENC, BINSR_D_DESC; 2818 2819 def BINSRI_B : BINSRI_B_ENC, BINSRI_B_DESC; 2820 def BINSRI_H : BINSRI_H_ENC, BINSRI_H_DESC; 2821 def BINSRI_W : BINSRI_W_ENC, BINSRI_W_DESC; 2822 def BINSRI_D : BINSRI_D_ENC, BINSRI_D_DESC; 2823 2824 def BMNZ_V : BMNZ_V_ENC, BMNZ_V_DESC; 2825 2826 def BMNZI_B : BMNZI_B_ENC, BMNZI_B_DESC; 2827 2828 def BMZ_V : BMZ_V_ENC, BMZ_V_DESC; 2829 2830 def BMZI_B : BMZI_B_ENC, BMZI_B_DESC; 2831 2832 def BNEG_B : BNEG_B_ENC, BNEG_B_DESC; 2833 def BNEG_H : BNEG_H_ENC, BNEG_H_DESC; 2834 def BNEG_W : BNEG_W_ENC, BNEG_W_DESC; 2835 def BNEG_D : BNEG_D_ENC, BNEG_D_DESC; 2836 2837 def BNEGI_B : BNEGI_B_ENC, BNEGI_B_DESC; 2838 def BNEGI_H : BNEGI_H_ENC, BNEGI_H_DESC; 2839 def BNEGI_W : BNEGI_W_ENC, BNEGI_W_DESC; 2840 def BNEGI_D : BNEGI_D_ENC, BNEGI_D_DESC; 2841 2842 def BNZ_B : BNZ_B_ENC, BNZ_B_DESC; 2843 def BNZ_H : BNZ_H_ENC, BNZ_H_DESC; 2844 def BNZ_W : BNZ_W_ENC, BNZ_W_DESC; 2845 def BNZ_D : BNZ_D_ENC, BNZ_D_DESC; 2846 2847 def BNZ_V : BNZ_V_ENC, BNZ_V_DESC; 2848 2849 def BSEL_V : BSEL_V_ENC, BSEL_V_DESC; 2850 2851 class MSA_BSEL_PSEUDO_BASE<RegisterOperand RO, ValueType Ty> : 2852 MSAPseudo<(outs RO:$wd), (ins RO:$wd_in, RO:$ws, RO:$wt), 2853 [(set RO:$wd, (Ty (vselect RO:$wd_in, RO:$wt, RO:$ws)))]>, 2854 // Note that vselect and BSEL_V treat the condition operand the opposite way 2855 // from each other. 2856 // (vselect cond, if_set, if_clear) 2857 // (BSEL_V cond, if_clear, if_set) 2858 PseudoInstExpansion<(BSEL_V MSA128BOpnd:$wd, MSA128BOpnd:$wd_in, 2859 MSA128BOpnd:$ws, MSA128BOpnd:$wt)> { 2860 let Constraints = "$wd_in = $wd"; 2861 } 2862 2863 def BSEL_H_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128HOpnd, v8i16>; 2864 def BSEL_W_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4i32>; 2865 def BSEL_D_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2i64>; 2866 def BSEL_FW_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4f32>; 2867 def BSEL_FD_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2f64>; 2868 2869 def BSELI_B : BSELI_B_ENC, BSELI_B_DESC; 2870 2871 def BSET_B : BSET_B_ENC, BSET_B_DESC; 2872 def BSET_H : BSET_H_ENC, BSET_H_DESC; 2873 def BSET_W : BSET_W_ENC, BSET_W_DESC; 2874 def BSET_D : BSET_D_ENC, BSET_D_DESC; 2875 2876 def BSETI_B : BSETI_B_ENC, BSETI_B_DESC; 2877 def BSETI_H : BSETI_H_ENC, BSETI_H_DESC; 2878 def BSETI_W : BSETI_W_ENC, BSETI_W_DESC; 2879 def BSETI_D : BSETI_D_ENC, BSETI_D_DESC; 2880 2881 def BZ_B : BZ_B_ENC, BZ_B_DESC; 2882 def BZ_H : BZ_H_ENC, BZ_H_DESC; 2883 def BZ_W : BZ_W_ENC, BZ_W_DESC; 2884 def BZ_D : BZ_D_ENC, BZ_D_DESC; 2885 2886 def BZ_V : BZ_V_ENC, BZ_V_DESC; 2887 2888 def CEQ_B : CEQ_B_ENC, CEQ_B_DESC; 2889 def CEQ_H : CEQ_H_ENC, CEQ_H_DESC; 2890 def CEQ_W : CEQ_W_ENC, CEQ_W_DESC; 2891 def CEQ_D : CEQ_D_ENC, CEQ_D_DESC; 2892 2893 def CEQI_B : CEQI_B_ENC, CEQI_B_DESC; 2894 def CEQI_H : CEQI_H_ENC, CEQI_H_DESC; 2895 def CEQI_W : CEQI_W_ENC, CEQI_W_DESC; 2896 def CEQI_D : CEQI_D_ENC, CEQI_D_DESC; 2897 2898 def CFCMSA : CFCMSA_ENC, CFCMSA_DESC; 2899 2900 def CLE_S_B : CLE_S_B_ENC, CLE_S_B_DESC; 2901 def CLE_S_H : CLE_S_H_ENC, CLE_S_H_DESC; 2902 def CLE_S_W : CLE_S_W_ENC, CLE_S_W_DESC; 2903 def CLE_S_D : CLE_S_D_ENC, CLE_S_D_DESC; 2904 2905 def CLE_U_B : CLE_U_B_ENC, CLE_U_B_DESC; 2906 def CLE_U_H : CLE_U_H_ENC, CLE_U_H_DESC; 2907 def CLE_U_W : CLE_U_W_ENC, CLE_U_W_DESC; 2908 def CLE_U_D : CLE_U_D_ENC, CLE_U_D_DESC; 2909 2910 def CLEI_S_B : CLEI_S_B_ENC, CLEI_S_B_DESC; 2911 def CLEI_S_H : CLEI_S_H_ENC, CLEI_S_H_DESC; 2912 def CLEI_S_W : CLEI_S_W_ENC, CLEI_S_W_DESC; 2913 def CLEI_S_D : CLEI_S_D_ENC, CLEI_S_D_DESC; 2914 2915 def CLEI_U_B : CLEI_U_B_ENC, CLEI_U_B_DESC; 2916 def CLEI_U_H : CLEI_U_H_ENC, CLEI_U_H_DESC; 2917 def CLEI_U_W : CLEI_U_W_ENC, CLEI_U_W_DESC; 2918 def CLEI_U_D : CLEI_U_D_ENC, CLEI_U_D_DESC; 2919 2920 def CLT_S_B : CLT_S_B_ENC, CLT_S_B_DESC; 2921 def CLT_S_H : CLT_S_H_ENC, CLT_S_H_DESC; 2922 def CLT_S_W : CLT_S_W_ENC, CLT_S_W_DESC; 2923 def CLT_S_D : CLT_S_D_ENC, CLT_S_D_DESC; 2924 2925 def CLT_U_B : CLT_U_B_ENC, CLT_U_B_DESC; 2926 def CLT_U_H : CLT_U_H_ENC, CLT_U_H_DESC; 2927 def CLT_U_W : CLT_U_W_ENC, CLT_U_W_DESC; 2928 def CLT_U_D : CLT_U_D_ENC, CLT_U_D_DESC; 2929 2930 def CLTI_S_B : CLTI_S_B_ENC, CLTI_S_B_DESC; 2931 def CLTI_S_H : CLTI_S_H_ENC, CLTI_S_H_DESC; 2932 def CLTI_S_W : CLTI_S_W_ENC, CLTI_S_W_DESC; 2933 def CLTI_S_D : CLTI_S_D_ENC, CLTI_S_D_DESC; 2934 2935 def CLTI_U_B : CLTI_U_B_ENC, CLTI_U_B_DESC; 2936 def CLTI_U_H : CLTI_U_H_ENC, CLTI_U_H_DESC; 2937 def CLTI_U_W : CLTI_U_W_ENC, CLTI_U_W_DESC; 2938 def CLTI_U_D : CLTI_U_D_ENC, CLTI_U_D_DESC; 2939 2940 def COPY_S_B : COPY_S_B_ENC, COPY_S_B_DESC; 2941 def COPY_S_H : COPY_S_H_ENC, COPY_S_H_DESC; 2942 def COPY_S_W : COPY_S_W_ENC, COPY_S_W_DESC; 2943 def COPY_S_D : COPY_S_D_ENC, COPY_S_D_DESC, ASE_MSA64; 2944 2945 def COPY_U_B : COPY_U_B_ENC, COPY_U_B_DESC; 2946 def COPY_U_H : COPY_U_H_ENC, COPY_U_H_DESC; 2947 def COPY_U_W : COPY_U_W_ENC, COPY_U_W_DESC, ASE_MSA64; 2948 2949 def COPY_FW_PSEUDO : COPY_FW_PSEUDO_DESC; 2950 def COPY_FD_PSEUDO : COPY_FD_PSEUDO_DESC; 2951 2952 def CTCMSA : CTCMSA_ENC, CTCMSA_DESC; 2953 2954 def DIV_S_B : DIV_S_B_ENC, DIV_S_B_DESC; 2955 def DIV_S_H : DIV_S_H_ENC, DIV_S_H_DESC; 2956 def DIV_S_W : DIV_S_W_ENC, DIV_S_W_DESC; 2957 def DIV_S_D : DIV_S_D_ENC, DIV_S_D_DESC; 2958 2959 def DIV_U_B : DIV_U_B_ENC, DIV_U_B_DESC; 2960 def DIV_U_H : DIV_U_H_ENC, DIV_U_H_DESC; 2961 def DIV_U_W : DIV_U_W_ENC, DIV_U_W_DESC; 2962 def DIV_U_D : DIV_U_D_ENC, DIV_U_D_DESC; 2963 2964 def DOTP_S_H : DOTP_S_H_ENC, DOTP_S_H_DESC; 2965 def DOTP_S_W : DOTP_S_W_ENC, DOTP_S_W_DESC; 2966 def DOTP_S_D : DOTP_S_D_ENC, DOTP_S_D_DESC; 2967 2968 def DOTP_U_H : DOTP_U_H_ENC, DOTP_U_H_DESC; 2969 def DOTP_U_W : DOTP_U_W_ENC, DOTP_U_W_DESC; 2970 def DOTP_U_D : DOTP_U_D_ENC, DOTP_U_D_DESC; 2971 2972 def DPADD_S_H : DPADD_S_H_ENC, DPADD_S_H_DESC; 2973 def DPADD_S_W : DPADD_S_W_ENC, DPADD_S_W_DESC; 2974 def DPADD_S_D : DPADD_S_D_ENC, DPADD_S_D_DESC; 2975 2976 def DPADD_U_H : DPADD_U_H_ENC, DPADD_U_H_DESC; 2977 def DPADD_U_W : DPADD_U_W_ENC, DPADD_U_W_DESC; 2978 def DPADD_U_D : DPADD_U_D_ENC, DPADD_U_D_DESC; 2979 2980 def DPSUB_S_H : DPSUB_S_H_ENC, DPSUB_S_H_DESC; 2981 def DPSUB_S_W : DPSUB_S_W_ENC, DPSUB_S_W_DESC; 2982 def DPSUB_S_D : DPSUB_S_D_ENC, DPSUB_S_D_DESC; 2983 2984 def DPSUB_U_H : DPSUB_U_H_ENC, DPSUB_U_H_DESC; 2985 def DPSUB_U_W : DPSUB_U_W_ENC, DPSUB_U_W_DESC; 2986 def DPSUB_U_D : DPSUB_U_D_ENC, DPSUB_U_D_DESC; 2987 2988 def FADD_W : FADD_W_ENC, FADD_W_DESC; 2989 def FADD_D : FADD_D_ENC, FADD_D_DESC; 2990 2991 def FCAF_W : FCAF_W_ENC, FCAF_W_DESC; 2992 def FCAF_D : FCAF_D_ENC, FCAF_D_DESC; 2993 2994 def FCEQ_W : FCEQ_W_ENC, FCEQ_W_DESC; 2995 def FCEQ_D : FCEQ_D_ENC, FCEQ_D_DESC; 2996 2997 def FCLE_W : FCLE_W_ENC, FCLE_W_DESC; 2998 def FCLE_D : FCLE_D_ENC, FCLE_D_DESC; 2999 3000 def FCLT_W : FCLT_W_ENC, FCLT_W_DESC; 3001 def FCLT_D : FCLT_D_ENC, FCLT_D_DESC; 3002 3003 def FCLASS_W : FCLASS_W_ENC, FCLASS_W_DESC; 3004 def FCLASS_D : FCLASS_D_ENC, FCLASS_D_DESC; 3005 3006 def FCNE_W : FCNE_W_ENC, FCNE_W_DESC; 3007 def FCNE_D : FCNE_D_ENC, FCNE_D_DESC; 3008 3009 def FCOR_W : FCOR_W_ENC, FCOR_W_DESC; 3010 def FCOR_D : FCOR_D_ENC, FCOR_D_DESC; 3011 3012 def FCUEQ_W : FCUEQ_W_ENC, FCUEQ_W_DESC; 3013 def FCUEQ_D : FCUEQ_D_ENC, FCUEQ_D_DESC; 3014 3015 def FCULE_W : FCULE_W_ENC, FCULE_W_DESC; 3016 def FCULE_D : FCULE_D_ENC, FCULE_D_DESC; 3017 3018 def FCULT_W : FCULT_W_ENC, FCULT_W_DESC; 3019 def FCULT_D : FCULT_D_ENC, FCULT_D_DESC; 3020 3021 def FCUN_W : FCUN_W_ENC, FCUN_W_DESC; 3022 def FCUN_D : FCUN_D_ENC, FCUN_D_DESC; 3023 3024 def FCUNE_W : FCUNE_W_ENC, FCUNE_W_DESC; 3025 def FCUNE_D : FCUNE_D_ENC, FCUNE_D_DESC; 3026 3027 def FDIV_W : FDIV_W_ENC, FDIV_W_DESC; 3028 def FDIV_D : FDIV_D_ENC, FDIV_D_DESC; 3029 3030 def FEXDO_H : FEXDO_H_ENC, FEXDO_H_DESC; 3031 def FEXDO_W : FEXDO_W_ENC, FEXDO_W_DESC; 3032 3033 def FEXP2_W : FEXP2_W_ENC, FEXP2_W_DESC; 3034 def FEXP2_D : FEXP2_D_ENC, FEXP2_D_DESC; 3035 def FEXP2_W_1_PSEUDO : FEXP2_W_1_PSEUDO_DESC; 3036 def FEXP2_D_1_PSEUDO : FEXP2_D_1_PSEUDO_DESC; 3037 3038 def FEXUPL_W : FEXUPL_W_ENC, FEXUPL_W_DESC; 3039 def FEXUPL_D : FEXUPL_D_ENC, FEXUPL_D_DESC; 3040 3041 def FEXUPR_W : FEXUPR_W_ENC, FEXUPR_W_DESC; 3042 def FEXUPR_D : FEXUPR_D_ENC, FEXUPR_D_DESC; 3043 3044 def FFINT_S_W : FFINT_S_W_ENC, FFINT_S_W_DESC; 3045 def FFINT_S_D : FFINT_S_D_ENC, FFINT_S_D_DESC; 3046 3047 def FFINT_U_W : FFINT_U_W_ENC, FFINT_U_W_DESC; 3048 def FFINT_U_D : FFINT_U_D_ENC, FFINT_U_D_DESC; 3049 3050 def FFQL_W : FFQL_W_ENC, FFQL_W_DESC; 3051 def FFQL_D : FFQL_D_ENC, FFQL_D_DESC; 3052 3053 def FFQR_W : FFQR_W_ENC, FFQR_W_DESC; 3054 def FFQR_D : FFQR_D_ENC, FFQR_D_DESC; 3055 3056 def FILL_B : FILL_B_ENC, FILL_B_DESC; 3057 def FILL_H : FILL_H_ENC, FILL_H_DESC; 3058 def FILL_W : FILL_W_ENC, FILL_W_DESC; 3059 def FILL_D : FILL_D_ENC, FILL_D_DESC, ASE_MSA64; 3060 def FILL_FW_PSEUDO : FILL_FW_PSEUDO_DESC; 3061 def FILL_FD_PSEUDO : FILL_FD_PSEUDO_DESC; 3062 3063 def FLOG2_W : FLOG2_W_ENC, FLOG2_W_DESC; 3064 def FLOG2_D : FLOG2_D_ENC, FLOG2_D_DESC; 3065 3066 def FMADD_W : FMADD_W_ENC, FMADD_W_DESC; 3067 def FMADD_D : FMADD_D_ENC, FMADD_D_DESC; 3068 3069 def FMAX_W : FMAX_W_ENC, FMAX_W_DESC; 3070 def FMAX_D : FMAX_D_ENC, FMAX_D_DESC; 3071 3072 def FMAX_A_W : FMAX_A_W_ENC, FMAX_A_W_DESC; 3073 def FMAX_A_D : FMAX_A_D_ENC, FMAX_A_D_DESC; 3074 3075 def FMIN_W : FMIN_W_ENC, FMIN_W_DESC; 3076 def FMIN_D : FMIN_D_ENC, FMIN_D_DESC; 3077 3078 def FMIN_A_W : FMIN_A_W_ENC, FMIN_A_W_DESC; 3079 def FMIN_A_D : FMIN_A_D_ENC, FMIN_A_D_DESC; 3080 3081 def FMSUB_W : FMSUB_W_ENC, FMSUB_W_DESC; 3082 def FMSUB_D : FMSUB_D_ENC, FMSUB_D_DESC; 3083 3084 def FMUL_W : FMUL_W_ENC, FMUL_W_DESC; 3085 def FMUL_D : FMUL_D_ENC, FMUL_D_DESC; 3086 3087 def FRINT_W : FRINT_W_ENC, FRINT_W_DESC; 3088 def FRINT_D : FRINT_D_ENC, FRINT_D_DESC; 3089 3090 def FRCP_W : FRCP_W_ENC, FRCP_W_DESC; 3091 def FRCP_D : FRCP_D_ENC, FRCP_D_DESC; 3092 3093 def FRSQRT_W : FRSQRT_W_ENC, FRSQRT_W_DESC; 3094 def FRSQRT_D : FRSQRT_D_ENC, FRSQRT_D_DESC; 3095 3096 def FSAF_W : FSAF_W_ENC, FSAF_W_DESC; 3097 def FSAF_D : FSAF_D_ENC, FSAF_D_DESC; 3098 3099 def FSEQ_W : FSEQ_W_ENC, FSEQ_W_DESC; 3100 def FSEQ_D : FSEQ_D_ENC, FSEQ_D_DESC; 3101 3102 def FSLE_W : FSLE_W_ENC, FSLE_W_DESC; 3103 def FSLE_D : FSLE_D_ENC, FSLE_D_DESC; 3104 3105 def FSLT_W : FSLT_W_ENC, FSLT_W_DESC; 3106 def FSLT_D : FSLT_D_ENC, FSLT_D_DESC; 3107 3108 def FSNE_W : FSNE_W_ENC, FSNE_W_DESC; 3109 def FSNE_D : FSNE_D_ENC, FSNE_D_DESC; 3110 3111 def FSOR_W : FSOR_W_ENC, FSOR_W_DESC; 3112 def FSOR_D : FSOR_D_ENC, FSOR_D_DESC; 3113 3114 def FSQRT_W : FSQRT_W_ENC, FSQRT_W_DESC; 3115 def FSQRT_D : FSQRT_D_ENC, FSQRT_D_DESC; 3116 3117 def FSUB_W : FSUB_W_ENC, FSUB_W_DESC; 3118 def FSUB_D : FSUB_D_ENC, FSUB_D_DESC; 3119 3120 def FSUEQ_W : FSUEQ_W_ENC, FSUEQ_W_DESC; 3121 def FSUEQ_D : FSUEQ_D_ENC, FSUEQ_D_DESC; 3122 3123 def FSULE_W : FSULE_W_ENC, FSULE_W_DESC; 3124 def FSULE_D : FSULE_D_ENC, FSULE_D_DESC; 3125 3126 def FSULT_W : FSULT_W_ENC, FSULT_W_DESC; 3127 def FSULT_D : FSULT_D_ENC, FSULT_D_DESC; 3128 3129 def FSUN_W : FSUN_W_ENC, FSUN_W_DESC; 3130 def FSUN_D : FSUN_D_ENC, FSUN_D_DESC; 3131 3132 def FSUNE_W : FSUNE_W_ENC, FSUNE_W_DESC; 3133 def FSUNE_D : FSUNE_D_ENC, FSUNE_D_DESC; 3134 3135 def FTINT_S_W : FTINT_S_W_ENC, FTINT_S_W_DESC; 3136 def FTINT_S_D : FTINT_S_D_ENC, FTINT_S_D_DESC; 3137 3138 def FTINT_U_W : FTINT_U_W_ENC, FTINT_U_W_DESC; 3139 def FTINT_U_D : FTINT_U_D_ENC, FTINT_U_D_DESC; 3140 3141 def FTQ_H : FTQ_H_ENC, FTQ_H_DESC; 3142 def FTQ_W : FTQ_W_ENC, FTQ_W_DESC; 3143 3144 def FTRUNC_S_W : FTRUNC_S_W_ENC, FTRUNC_S_W_DESC; 3145 def FTRUNC_S_D : FTRUNC_S_D_ENC, FTRUNC_S_D_DESC; 3146 3147 def FTRUNC_U_W : FTRUNC_U_W_ENC, FTRUNC_U_W_DESC; 3148 def FTRUNC_U_D : FTRUNC_U_D_ENC, FTRUNC_U_D_DESC; 3149 3150 def HADD_S_H : HADD_S_H_ENC, HADD_S_H_DESC; 3151 def HADD_S_W : HADD_S_W_ENC, HADD_S_W_DESC; 3152 def HADD_S_D : HADD_S_D_ENC, HADD_S_D_DESC; 3153 3154 def HADD_U_H : HADD_U_H_ENC, HADD_U_H_DESC; 3155 def HADD_U_W : HADD_U_W_ENC, HADD_U_W_DESC; 3156 def HADD_U_D : HADD_U_D_ENC, HADD_U_D_DESC; 3157 3158 def HSUB_S_H : HSUB_S_H_ENC, HSUB_S_H_DESC; 3159 def HSUB_S_W : HSUB_S_W_ENC, HSUB_S_W_DESC; 3160 def HSUB_S_D : HSUB_S_D_ENC, HSUB_S_D_DESC; 3161 3162 def HSUB_U_H : HSUB_U_H_ENC, HSUB_U_H_DESC; 3163 def HSUB_U_W : HSUB_U_W_ENC, HSUB_U_W_DESC; 3164 def HSUB_U_D : HSUB_U_D_ENC, HSUB_U_D_DESC; 3165 3166 def ILVEV_B : ILVEV_B_ENC, ILVEV_B_DESC; 3167 def ILVEV_H : ILVEV_H_ENC, ILVEV_H_DESC; 3168 def ILVEV_W : ILVEV_W_ENC, ILVEV_W_DESC; 3169 def ILVEV_D : ILVEV_D_ENC, ILVEV_D_DESC; 3170 3171 def ILVL_B : ILVL_B_ENC, ILVL_B_DESC; 3172 def ILVL_H : ILVL_H_ENC, ILVL_H_DESC; 3173 def ILVL_W : ILVL_W_ENC, ILVL_W_DESC; 3174 def ILVL_D : ILVL_D_ENC, ILVL_D_DESC; 3175 3176 def ILVOD_B : ILVOD_B_ENC, ILVOD_B_DESC; 3177 def ILVOD_H : ILVOD_H_ENC, ILVOD_H_DESC; 3178 def ILVOD_W : ILVOD_W_ENC, ILVOD_W_DESC; 3179 def ILVOD_D : ILVOD_D_ENC, ILVOD_D_DESC; 3180 3181 def ILVR_B : ILVR_B_ENC, ILVR_B_DESC; 3182 def ILVR_H : ILVR_H_ENC, ILVR_H_DESC; 3183 def ILVR_W : ILVR_W_ENC, ILVR_W_DESC; 3184 def ILVR_D : ILVR_D_ENC, ILVR_D_DESC; 3185 3186 def INSERT_B : INSERT_B_ENC, INSERT_B_DESC; 3187 def INSERT_H : INSERT_H_ENC, INSERT_H_DESC; 3188 def INSERT_W : INSERT_W_ENC, INSERT_W_DESC; 3189 def INSERT_D : INSERT_D_ENC, INSERT_D_DESC, ASE_MSA64; 3190 3191 // INSERT_FW_PSEUDO defined after INSVE_W 3192 // INSERT_FD_PSEUDO defined after INSVE_D 3193 3194 // There is a fourth operand that is not present in the encoding. Use a 3195 // custom decoder to get a chance to add it. 3196 let DecoderMethod = "DecodeINSVE_DF" in { 3197 def INSVE_B : INSVE_B_ENC, INSVE_B_DESC; 3198 def INSVE_H : INSVE_H_ENC, INSVE_H_DESC; 3199 def INSVE_W : INSVE_W_ENC, INSVE_W_DESC; 3200 def INSVE_D : INSVE_D_ENC, INSVE_D_DESC; 3201 } 3202 3203 def INSERT_FW_PSEUDO : INSERT_FW_PSEUDO_DESC; 3204 def INSERT_FD_PSEUDO : INSERT_FD_PSEUDO_DESC; 3205 3206 def INSERT_B_VIDX_PSEUDO : INSERT_B_VIDX_PSEUDO_DESC; 3207 def INSERT_H_VIDX_PSEUDO : INSERT_H_VIDX_PSEUDO_DESC; 3208 def INSERT_W_VIDX_PSEUDO : INSERT_W_VIDX_PSEUDO_DESC; 3209 def INSERT_D_VIDX_PSEUDO : INSERT_D_VIDX_PSEUDO_DESC; 3210 def INSERT_FW_VIDX_PSEUDO : INSERT_FW_VIDX_PSEUDO_DESC; 3211 def INSERT_FD_VIDX_PSEUDO : INSERT_FD_VIDX_PSEUDO_DESC; 3212 3213 def INSERT_B_VIDX64_PSEUDO : INSERT_B_VIDX64_PSEUDO_DESC; 3214 def INSERT_H_VIDX64_PSEUDO : INSERT_H_VIDX64_PSEUDO_DESC; 3215 def INSERT_W_VIDX64_PSEUDO : INSERT_W_VIDX64_PSEUDO_DESC; 3216 def INSERT_D_VIDX64_PSEUDO : INSERT_D_VIDX64_PSEUDO_DESC; 3217 def INSERT_FW_VIDX64_PSEUDO : INSERT_FW_VIDX64_PSEUDO_DESC; 3218 def INSERT_FD_VIDX64_PSEUDO : INSERT_FD_VIDX64_PSEUDO_DESC; 3219 3220 def LD_B: LD_B_ENC, LD_B_DESC; 3221 def LD_H: LD_H_ENC, LD_H_DESC; 3222 def LD_W: LD_W_ENC, LD_W_DESC; 3223 def LD_D: LD_D_ENC, LD_D_DESC; 3224 3225 def LDI_B : LDI_B_ENC, LDI_B_DESC; 3226 def LDI_H : LDI_H_ENC, LDI_H_DESC; 3227 def LDI_W : LDI_W_ENC, LDI_W_DESC; 3228 def LDI_D : LDI_D_ENC, LDI_D_DESC; 3229 3230 def LSA : LSA_ENC, LSA_DESC; 3231 def DLSA : DLSA_ENC, DLSA_DESC, ASE_MSA64; 3232 3233 def MADD_Q_H : MADD_Q_H_ENC, MADD_Q_H_DESC; 3234 def MADD_Q_W : MADD_Q_W_ENC, MADD_Q_W_DESC; 3235 3236 def MADDR_Q_H : MADDR_Q_H_ENC, MADDR_Q_H_DESC; 3237 def MADDR_Q_W : MADDR_Q_W_ENC, MADDR_Q_W_DESC; 3238 3239 def MADDV_B : MADDV_B_ENC, MADDV_B_DESC; 3240 def MADDV_H : MADDV_H_ENC, MADDV_H_DESC; 3241 def MADDV_W : MADDV_W_ENC, MADDV_W_DESC; 3242 def MADDV_D : MADDV_D_ENC, MADDV_D_DESC; 3243 3244 def MAX_A_B : MAX_A_B_ENC, MAX_A_B_DESC; 3245 def MAX_A_H : MAX_A_H_ENC, MAX_A_H_DESC; 3246 def MAX_A_W : MAX_A_W_ENC, MAX_A_W_DESC; 3247 def MAX_A_D : MAX_A_D_ENC, MAX_A_D_DESC; 3248 3249 def MAX_S_B : MAX_S_B_ENC, MAX_S_B_DESC; 3250 def MAX_S_H : MAX_S_H_ENC, MAX_S_H_DESC; 3251 def MAX_S_W : MAX_S_W_ENC, MAX_S_W_DESC; 3252 def MAX_S_D : MAX_S_D_ENC, MAX_S_D_DESC; 3253 3254 def MAX_U_B : MAX_U_B_ENC, MAX_U_B_DESC; 3255 def MAX_U_H : MAX_U_H_ENC, MAX_U_H_DESC; 3256 def MAX_U_W : MAX_U_W_ENC, MAX_U_W_DESC; 3257 def MAX_U_D : MAX_U_D_ENC, MAX_U_D_DESC; 3258 3259 def MAXI_S_B : MAXI_S_B_ENC, MAXI_S_B_DESC; 3260 def MAXI_S_H : MAXI_S_H_ENC, MAXI_S_H_DESC; 3261 def MAXI_S_W : MAXI_S_W_ENC, MAXI_S_W_DESC; 3262 def MAXI_S_D : MAXI_S_D_ENC, MAXI_S_D_DESC; 3263 3264 def MAXI_U_B : MAXI_U_B_ENC, MAXI_U_B_DESC; 3265 def MAXI_U_H : MAXI_U_H_ENC, MAXI_U_H_DESC; 3266 def MAXI_U_W : MAXI_U_W_ENC, MAXI_U_W_DESC; 3267 def MAXI_U_D : MAXI_U_D_ENC, MAXI_U_D_DESC; 3268 3269 def MIN_A_B : MIN_A_B_ENC, MIN_A_B_DESC; 3270 def MIN_A_H : MIN_A_H_ENC, MIN_A_H_DESC; 3271 def MIN_A_W : MIN_A_W_ENC, MIN_A_W_DESC; 3272 def MIN_A_D : MIN_A_D_ENC, MIN_A_D_DESC; 3273 3274 def MIN_S_B : MIN_S_B_ENC, MIN_S_B_DESC; 3275 def MIN_S_H : MIN_S_H_ENC, MIN_S_H_DESC; 3276 def MIN_S_W : MIN_S_W_ENC, MIN_S_W_DESC; 3277 def MIN_S_D : MIN_S_D_ENC, MIN_S_D_DESC; 3278 3279 def MIN_U_B : MIN_U_B_ENC, MIN_U_B_DESC; 3280 def MIN_U_H : MIN_U_H_ENC, MIN_U_H_DESC; 3281 def MIN_U_W : MIN_U_W_ENC, MIN_U_W_DESC; 3282 def MIN_U_D : MIN_U_D_ENC, MIN_U_D_DESC; 3283 3284 def MINI_S_B : MINI_S_B_ENC, MINI_S_B_DESC; 3285 def MINI_S_H : MINI_S_H_ENC, MINI_S_H_DESC; 3286 def MINI_S_W : MINI_S_W_ENC, MINI_S_W_DESC; 3287 def MINI_S_D : MINI_S_D_ENC, MINI_S_D_DESC; 3288 3289 def MINI_U_B : MINI_U_B_ENC, MINI_U_B_DESC; 3290 def MINI_U_H : MINI_U_H_ENC, MINI_U_H_DESC; 3291 def MINI_U_W : MINI_U_W_ENC, MINI_U_W_DESC; 3292 def MINI_U_D : MINI_U_D_ENC, MINI_U_D_DESC; 3293 3294 def MOD_S_B : MOD_S_B_ENC, MOD_S_B_DESC; 3295 def MOD_S_H : MOD_S_H_ENC, MOD_S_H_DESC; 3296 def MOD_S_W : MOD_S_W_ENC, MOD_S_W_DESC; 3297 def MOD_S_D : MOD_S_D_ENC, MOD_S_D_DESC; 3298 3299 def MOD_U_B : MOD_U_B_ENC, MOD_U_B_DESC; 3300 def MOD_U_H : MOD_U_H_ENC, MOD_U_H_DESC; 3301 def MOD_U_W : MOD_U_W_ENC, MOD_U_W_DESC; 3302 def MOD_U_D : MOD_U_D_ENC, MOD_U_D_DESC; 3303 3304 def MOVE_V : MOVE_V_ENC, MOVE_V_DESC; 3305 3306 def MSUB_Q_H : MSUB_Q_H_ENC, MSUB_Q_H_DESC; 3307 def MSUB_Q_W : MSUB_Q_W_ENC, MSUB_Q_W_DESC; 3308 3309 def MSUBR_Q_H : MSUBR_Q_H_ENC, MSUBR_Q_H_DESC; 3310 def MSUBR_Q_W : MSUBR_Q_W_ENC, MSUBR_Q_W_DESC; 3311 3312 def MSUBV_B : MSUBV_B_ENC, MSUBV_B_DESC; 3313 def MSUBV_H : MSUBV_H_ENC, MSUBV_H_DESC; 3314 def MSUBV_W : MSUBV_W_ENC, MSUBV_W_DESC; 3315 def MSUBV_D : MSUBV_D_ENC, MSUBV_D_DESC; 3316 3317 def MUL_Q_H : MUL_Q_H_ENC, MUL_Q_H_DESC; 3318 def MUL_Q_W : MUL_Q_W_ENC, MUL_Q_W_DESC; 3319 3320 def MULR_Q_H : MULR_Q_H_ENC, MULR_Q_H_DESC; 3321 def MULR_Q_W : MULR_Q_W_ENC, MULR_Q_W_DESC; 3322 3323 def MULV_B : MULV_B_ENC, MULV_B_DESC; 3324 def MULV_H : MULV_H_ENC, MULV_H_DESC; 3325 def MULV_W : MULV_W_ENC, MULV_W_DESC; 3326 def MULV_D : MULV_D_ENC, MULV_D_DESC; 3327 3328 def NLOC_B : NLOC_B_ENC, NLOC_B_DESC; 3329 def NLOC_H : NLOC_H_ENC, NLOC_H_DESC; 3330 def NLOC_W : NLOC_W_ENC, NLOC_W_DESC; 3331 def NLOC_D : NLOC_D_ENC, NLOC_D_DESC; 3332 3333 def NLZC_B : NLZC_B_ENC, NLZC_B_DESC; 3334 def NLZC_H : NLZC_H_ENC, NLZC_H_DESC; 3335 def NLZC_W : NLZC_W_ENC, NLZC_W_DESC; 3336 def NLZC_D : NLZC_D_ENC, NLZC_D_DESC; 3337 3338 def NOR_V : NOR_V_ENC, NOR_V_DESC; 3339 def NOR_V_H_PSEUDO : NOR_V_H_PSEUDO_DESC, 3340 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd, 3341 MSA128BOpnd:$ws, 3342 MSA128BOpnd:$wt)>; 3343 def NOR_V_W_PSEUDO : NOR_V_W_PSEUDO_DESC, 3344 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd, 3345 MSA128BOpnd:$ws, 3346 MSA128BOpnd:$wt)>; 3347 def NOR_V_D_PSEUDO : NOR_V_D_PSEUDO_DESC, 3348 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd, 3349 MSA128BOpnd:$ws, 3350 MSA128BOpnd:$wt)>; 3351 3352 def NORI_B : NORI_B_ENC, NORI_B_DESC; 3353 3354 def OR_V : OR_V_ENC, OR_V_DESC; 3355 def OR_V_H_PSEUDO : OR_V_H_PSEUDO_DESC, 3356 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd, 3357 MSA128BOpnd:$ws, 3358 MSA128BOpnd:$wt)>; 3359 def OR_V_W_PSEUDO : OR_V_W_PSEUDO_DESC, 3360 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd, 3361 MSA128BOpnd:$ws, 3362 MSA128BOpnd:$wt)>; 3363 def OR_V_D_PSEUDO : OR_V_D_PSEUDO_DESC, 3364 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd, 3365 MSA128BOpnd:$ws, 3366 MSA128BOpnd:$wt)>; 3367 3368 def ORI_B : ORI_B_ENC, ORI_B_DESC; 3369 3370 def PCKEV_B : PCKEV_B_ENC, PCKEV_B_DESC; 3371 def PCKEV_H : PCKEV_H_ENC, PCKEV_H_DESC; 3372 def PCKEV_W : PCKEV_W_ENC, PCKEV_W_DESC; 3373 def PCKEV_D : PCKEV_D_ENC, PCKEV_D_DESC; 3374 3375 def PCKOD_B : PCKOD_B_ENC, PCKOD_B_DESC; 3376 def PCKOD_H : PCKOD_H_ENC, PCKOD_H_DESC; 3377 def PCKOD_W : PCKOD_W_ENC, PCKOD_W_DESC; 3378 def PCKOD_D : PCKOD_D_ENC, PCKOD_D_DESC; 3379 3380 def PCNT_B : PCNT_B_ENC, PCNT_B_DESC; 3381 def PCNT_H : PCNT_H_ENC, PCNT_H_DESC; 3382 def PCNT_W : PCNT_W_ENC, PCNT_W_DESC; 3383 def PCNT_D : PCNT_D_ENC, PCNT_D_DESC; 3384 3385 def SAT_S_B : SAT_S_B_ENC, SAT_S_B_DESC; 3386 def SAT_S_H : SAT_S_H_ENC, SAT_S_H_DESC; 3387 def SAT_S_W : SAT_S_W_ENC, SAT_S_W_DESC; 3388 def SAT_S_D : SAT_S_D_ENC, SAT_S_D_DESC; 3389 3390 def SAT_U_B : SAT_U_B_ENC, SAT_U_B_DESC; 3391 def SAT_U_H : SAT_U_H_ENC, SAT_U_H_DESC; 3392 def SAT_U_W : SAT_U_W_ENC, SAT_U_W_DESC; 3393 def SAT_U_D : SAT_U_D_ENC, SAT_U_D_DESC; 3394 3395 def SHF_B : SHF_B_ENC, SHF_B_DESC; 3396 def SHF_H : SHF_H_ENC, SHF_H_DESC; 3397 def SHF_W : SHF_W_ENC, SHF_W_DESC; 3398 3399 def SLD_B : SLD_B_ENC, SLD_B_DESC; 3400 def SLD_H : SLD_H_ENC, SLD_H_DESC; 3401 def SLD_W : SLD_W_ENC, SLD_W_DESC; 3402 def SLD_D : SLD_D_ENC, SLD_D_DESC; 3403 3404 def SLDI_B : SLDI_B_ENC, SLDI_B_DESC; 3405 def SLDI_H : SLDI_H_ENC, SLDI_H_DESC; 3406 def SLDI_W : SLDI_W_ENC, SLDI_W_DESC; 3407 def SLDI_D : SLDI_D_ENC, SLDI_D_DESC; 3408 3409 def SLL_B : SLL_B_ENC, SLL_B_DESC; 3410 def SLL_H : SLL_H_ENC, SLL_H_DESC; 3411 def SLL_W : SLL_W_ENC, SLL_W_DESC; 3412 def SLL_D : SLL_D_ENC, SLL_D_DESC; 3413 3414 def SLLI_B : SLLI_B_ENC, SLLI_B_DESC; 3415 def SLLI_H : SLLI_H_ENC, SLLI_H_DESC; 3416 def SLLI_W : SLLI_W_ENC, SLLI_W_DESC; 3417 def SLLI_D : SLLI_D_ENC, SLLI_D_DESC; 3418 3419 def SPLAT_B : SPLAT_B_ENC, SPLAT_B_DESC; 3420 def SPLAT_H : SPLAT_H_ENC, SPLAT_H_DESC; 3421 def SPLAT_W : SPLAT_W_ENC, SPLAT_W_DESC; 3422 def SPLAT_D : SPLAT_D_ENC, SPLAT_D_DESC; 3423 3424 def SPLATI_B : SPLATI_B_ENC, SPLATI_B_DESC; 3425 def SPLATI_H : SPLATI_H_ENC, SPLATI_H_DESC; 3426 def SPLATI_W : SPLATI_W_ENC, SPLATI_W_DESC; 3427 def SPLATI_D : SPLATI_D_ENC, SPLATI_D_DESC; 3428 3429 def SRA_B : SRA_B_ENC, SRA_B_DESC; 3430 def SRA_H : SRA_H_ENC, SRA_H_DESC; 3431 def SRA_W : SRA_W_ENC, SRA_W_DESC; 3432 def SRA_D : SRA_D_ENC, SRA_D_DESC; 3433 3434 def SRAI_B : SRAI_B_ENC, SRAI_B_DESC; 3435 def SRAI_H : SRAI_H_ENC, SRAI_H_DESC; 3436 def SRAI_W : SRAI_W_ENC, SRAI_W_DESC; 3437 def SRAI_D : SRAI_D_ENC, SRAI_D_DESC; 3438 3439 def SRAR_B : SRAR_B_ENC, SRAR_B_DESC; 3440 def SRAR_H : SRAR_H_ENC, SRAR_H_DESC; 3441 def SRAR_W : SRAR_W_ENC, SRAR_W_DESC; 3442 def SRAR_D : SRAR_D_ENC, SRAR_D_DESC; 3443 3444 def SRARI_B : SRARI_B_ENC, SRARI_B_DESC; 3445 def SRARI_H : SRARI_H_ENC, SRARI_H_DESC; 3446 def SRARI_W : SRARI_W_ENC, SRARI_W_DESC; 3447 def SRARI_D : SRARI_D_ENC, SRARI_D_DESC; 3448 3449 def SRL_B : SRL_B_ENC, SRL_B_DESC; 3450 def SRL_H : SRL_H_ENC, SRL_H_DESC; 3451 def SRL_W : SRL_W_ENC, SRL_W_DESC; 3452 def SRL_D : SRL_D_ENC, SRL_D_DESC; 3453 3454 def SRLI_B : SRLI_B_ENC, SRLI_B_DESC; 3455 def SRLI_H : SRLI_H_ENC, SRLI_H_DESC; 3456 def SRLI_W : SRLI_W_ENC, SRLI_W_DESC; 3457 def SRLI_D : SRLI_D_ENC, SRLI_D_DESC; 3458 3459 def SRLR_B : SRLR_B_ENC, SRLR_B_DESC; 3460 def SRLR_H : SRLR_H_ENC, SRLR_H_DESC; 3461 def SRLR_W : SRLR_W_ENC, SRLR_W_DESC; 3462 def SRLR_D : SRLR_D_ENC, SRLR_D_DESC; 3463 3464 def SRLRI_B : SRLRI_B_ENC, SRLRI_B_DESC; 3465 def SRLRI_H : SRLRI_H_ENC, SRLRI_H_DESC; 3466 def SRLRI_W : SRLRI_W_ENC, SRLRI_W_DESC; 3467 def SRLRI_D : SRLRI_D_ENC, SRLRI_D_DESC; 3468 3469 def ST_B: ST_B_ENC, ST_B_DESC; 3470 def ST_H: ST_H_ENC, ST_H_DESC; 3471 def ST_W: ST_W_ENC, ST_W_DESC; 3472 def ST_D: ST_D_ENC, ST_D_DESC; 3473 3474 def SUBS_S_B : SUBS_S_B_ENC, SUBS_S_B_DESC; 3475 def SUBS_S_H : SUBS_S_H_ENC, SUBS_S_H_DESC; 3476 def SUBS_S_W : SUBS_S_W_ENC, SUBS_S_W_DESC; 3477 def SUBS_S_D : SUBS_S_D_ENC, SUBS_S_D_DESC; 3478 3479 def SUBS_U_B : SUBS_U_B_ENC, SUBS_U_B_DESC; 3480 def SUBS_U_H : SUBS_U_H_ENC, SUBS_U_H_DESC; 3481 def SUBS_U_W : SUBS_U_W_ENC, SUBS_U_W_DESC; 3482 def SUBS_U_D : SUBS_U_D_ENC, SUBS_U_D_DESC; 3483 3484 def SUBSUS_U_B : SUBSUS_U_B_ENC, SUBSUS_U_B_DESC; 3485 def SUBSUS_U_H : SUBSUS_U_H_ENC, SUBSUS_U_H_DESC; 3486 def SUBSUS_U_W : SUBSUS_U_W_ENC, SUBSUS_U_W_DESC; 3487 def SUBSUS_U_D : SUBSUS_U_D_ENC, SUBSUS_U_D_DESC; 3488 3489 def SUBSUU_S_B : SUBSUU_S_B_ENC, SUBSUU_S_B_DESC; 3490 def SUBSUU_S_H : SUBSUU_S_H_ENC, SUBSUU_S_H_DESC; 3491 def SUBSUU_S_W : SUBSUU_S_W_ENC, SUBSUU_S_W_DESC; 3492 def SUBSUU_S_D : SUBSUU_S_D_ENC, SUBSUU_S_D_DESC; 3493 3494 def SUBV_B : SUBV_B_ENC, SUBV_B_DESC; 3495 def SUBV_H : SUBV_H_ENC, SUBV_H_DESC; 3496 def SUBV_W : SUBV_W_ENC, SUBV_W_DESC; 3497 def SUBV_D : SUBV_D_ENC, SUBV_D_DESC; 3498 3499 def SUBVI_B : SUBVI_B_ENC, SUBVI_B_DESC; 3500 def SUBVI_H : SUBVI_H_ENC, SUBVI_H_DESC; 3501 def SUBVI_W : SUBVI_W_ENC, SUBVI_W_DESC; 3502 def SUBVI_D : SUBVI_D_ENC, SUBVI_D_DESC; 3503 3504 def VSHF_B : VSHF_B_ENC, VSHF_B_DESC; 3505 def VSHF_H : VSHF_H_ENC, VSHF_H_DESC; 3506 def VSHF_W : VSHF_W_ENC, VSHF_W_DESC; 3507 def VSHF_D : VSHF_D_ENC, VSHF_D_DESC; 3508 3509 def XOR_V : XOR_V_ENC, XOR_V_DESC; 3510 def XOR_V_H_PSEUDO : XOR_V_H_PSEUDO_DESC, 3511 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd, 3512 MSA128BOpnd:$ws, 3513 MSA128BOpnd:$wt)>; 3514 def XOR_V_W_PSEUDO : XOR_V_W_PSEUDO_DESC, 3515 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd, 3516 MSA128BOpnd:$ws, 3517 MSA128BOpnd:$wt)>; 3518 def XOR_V_D_PSEUDO : XOR_V_D_PSEUDO_DESC, 3519 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd, 3520 MSA128BOpnd:$ws, 3521 MSA128BOpnd:$wt)>; 3522 3523 def XORI_B : XORI_B_ENC, XORI_B_DESC; 3524 3525 // Patterns. 3526 class MSAPat<dag pattern, dag result, list<Predicate> pred = [HasMSA]> : 3527 Pat<pattern, result>, Requires<pred>; 3528 3529 def : MSAPat<(extractelt (v4i32 MSA128W:$ws), immZExt4:$idx), 3530 (COPY_S_W MSA128W:$ws, immZExt4:$idx)>; 3531 3532 def : MSAPat<(v8f16 (load addrimm10:$addr)), (LD_H addrimm10:$addr)>; 3533 def : MSAPat<(v4f32 (load addrimm10:$addr)), (LD_W addrimm10:$addr)>; 3534 def : MSAPat<(v2f64 (load addrimm10:$addr)), (LD_D addrimm10:$addr)>; 3535 3536 def ST_FH : MSAPat<(store (v8f16 MSA128H:$ws), addrimm10:$addr), 3537 (ST_H MSA128H:$ws, addrimm10:$addr)>; 3538 def ST_FW : MSAPat<(store (v4f32 MSA128W:$ws), addrimm10:$addr), 3539 (ST_W MSA128W:$ws, addrimm10:$addr)>; 3540 def ST_FD : MSAPat<(store (v2f64 MSA128D:$ws), addrimm10:$addr), 3541 (ST_D MSA128D:$ws, addrimm10:$addr)>; 3542 3543 class MSA_FABS_PSEUDO_DESC_BASE<RegisterOperand ROWD, 3544 RegisterOperand ROWS = ROWD, 3545 InstrItinClass itin = NoItinerary> : 3546 MSAPseudo<(outs ROWD:$wd), 3547 (ins ROWS:$ws), 3548 [(set ROWD:$wd, (fabs ROWS:$ws))]> { 3549 InstrItinClass Itinerary = itin; 3550 } 3551 def FABS_W : MSA_FABS_PSEUDO_DESC_BASE<MSA128WOpnd>, 3552 PseudoInstExpansion<(FMAX_A_W MSA128WOpnd:$wd, MSA128WOpnd:$ws, 3553 MSA128WOpnd:$ws)>; 3554 def FABS_D : MSA_FABS_PSEUDO_DESC_BASE<MSA128DOpnd>, 3555 PseudoInstExpansion<(FMAX_A_D MSA128DOpnd:$wd, MSA128DOpnd:$ws, 3556 MSA128DOpnd:$ws)>; 3557 3558 class MSABitconvertPat<ValueType DstVT, ValueType SrcVT, 3559 RegisterClass DstRC, list<Predicate> preds = [HasMSA]> : 3560 MSAPat<(DstVT (bitconvert SrcVT:$src)), 3561 (COPY_TO_REGCLASS SrcVT:$src, DstRC), preds>; 3562 3563 // These are endian-independent because the element size doesnt change 3564 def : MSABitconvertPat<v8i16, v8f16, MSA128H>; 3565 def : MSABitconvertPat<v4i32, v4f32, MSA128W>; 3566 def : MSABitconvertPat<v2i64, v2f64, MSA128D>; 3567 def : MSABitconvertPat<v8f16, v8i16, MSA128H>; 3568 def : MSABitconvertPat<v4f32, v4i32, MSA128W>; 3569 def : MSABitconvertPat<v2f64, v2i64, MSA128D>; 3570 3571 // Little endian bitcasts are always no-ops 3572 def : MSABitconvertPat<v16i8, v8i16, MSA128B, [HasMSA, IsLE]>; 3573 def : MSABitconvertPat<v16i8, v4i32, MSA128B, [HasMSA, IsLE]>; 3574 def : MSABitconvertPat<v16i8, v2i64, MSA128B, [HasMSA, IsLE]>; 3575 def : MSABitconvertPat<v16i8, v8f16, MSA128B, [HasMSA, IsLE]>; 3576 def : MSABitconvertPat<v16i8, v4f32, MSA128B, [HasMSA, IsLE]>; 3577 def : MSABitconvertPat<v16i8, v2f64, MSA128B, [HasMSA, IsLE]>; 3578 3579 def : MSABitconvertPat<v8i16, v16i8, MSA128H, [HasMSA, IsLE]>; 3580 def : MSABitconvertPat<v8i16, v4i32, MSA128H, [HasMSA, IsLE]>; 3581 def : MSABitconvertPat<v8i16, v2i64, MSA128H, [HasMSA, IsLE]>; 3582 def : MSABitconvertPat<v8i16, v4f32, MSA128H, [HasMSA, IsLE]>; 3583 def : MSABitconvertPat<v8i16, v2f64, MSA128H, [HasMSA, IsLE]>; 3584 3585 def : MSABitconvertPat<v4i32, v16i8, MSA128W, [HasMSA, IsLE]>; 3586 def : MSABitconvertPat<v4i32, v8i16, MSA128W, [HasMSA, IsLE]>; 3587 def : MSABitconvertPat<v4i32, v2i64, MSA128W, [HasMSA, IsLE]>; 3588 def : MSABitconvertPat<v4i32, v8f16, MSA128W, [HasMSA, IsLE]>; 3589 def : MSABitconvertPat<v4i32, v2f64, MSA128W, [HasMSA, IsLE]>; 3590 3591 def : MSABitconvertPat<v2i64, v16i8, MSA128D, [HasMSA, IsLE]>; 3592 def : MSABitconvertPat<v2i64, v8i16, MSA128D, [HasMSA, IsLE]>; 3593 def : MSABitconvertPat<v2i64, v4i32, MSA128D, [HasMSA, IsLE]>; 3594 def : MSABitconvertPat<v2i64, v8f16, MSA128D, [HasMSA, IsLE]>; 3595 def : MSABitconvertPat<v2i64, v4f32, MSA128D, [HasMSA, IsLE]>; 3596 3597 def : MSABitconvertPat<v4f32, v16i8, MSA128W, [HasMSA, IsLE]>; 3598 def : MSABitconvertPat<v4f32, v8i16, MSA128W, [HasMSA, IsLE]>; 3599 def : MSABitconvertPat<v4f32, v2i64, MSA128W, [HasMSA, IsLE]>; 3600 def : MSABitconvertPat<v4f32, v8f16, MSA128W, [HasMSA, IsLE]>; 3601 def : MSABitconvertPat<v4f32, v2f64, MSA128W, [HasMSA, IsLE]>; 3602 3603 def : MSABitconvertPat<v2f64, v16i8, MSA128D, [HasMSA, IsLE]>; 3604 def : MSABitconvertPat<v2f64, v8i16, MSA128D, [HasMSA, IsLE]>; 3605 def : MSABitconvertPat<v2f64, v4i32, MSA128D, [HasMSA, IsLE]>; 3606 def : MSABitconvertPat<v2f64, v8f16, MSA128D, [HasMSA, IsLE]>; 3607 def : MSABitconvertPat<v2f64, v4f32, MSA128D, [HasMSA, IsLE]>; 3608 3609 // Big endian bitcasts expand to shuffle instructions. 3610 // This is because bitcast is defined to be a store/load sequence and the 3611 // vector store/load instructions are mixed-endian with respect to the vector 3612 // as a whole (little endian with respect to element order, but big endian 3613 // elements). 3614 3615 class MSABitconvertReverseQuartersPat<ValueType DstVT, ValueType SrcVT, 3616 RegisterClass DstRC, MSAInst Insn, 3617 RegisterClass ViaRC> : 3618 MSAPat<(DstVT (bitconvert SrcVT:$src)), 3619 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 27), 3620 DstRC), 3621 [HasMSA, IsBE]>; 3622 3623 class MSABitconvertReverseHalvesPat<ValueType DstVT, ValueType SrcVT, 3624 RegisterClass DstRC, MSAInst Insn, 3625 RegisterClass ViaRC> : 3626 MSAPat<(DstVT (bitconvert SrcVT:$src)), 3627 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 177), 3628 DstRC), 3629 [HasMSA, IsBE]>; 3630 3631 class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT, 3632 RegisterClass DstRC> : 3633 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>; 3634 3635 class MSABitconvertReverseBInWPat<ValueType DstVT, ValueType SrcVT, 3636 RegisterClass DstRC> : 3637 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>; 3638 3639 class MSABitconvertReverseBInDPat<ValueType DstVT, ValueType SrcVT, 3640 RegisterClass DstRC> : 3641 MSAPat<(DstVT (bitconvert SrcVT:$src)), 3642 (COPY_TO_REGCLASS 3643 (SHF_W 3644 (COPY_TO_REGCLASS 3645 (SHF_B (COPY_TO_REGCLASS SrcVT:$src, MSA128B), 27), 3646 MSA128W), 177), 3647 DstRC), 3648 [HasMSA, IsBE]>; 3649 3650 class MSABitconvertReverseHInWPat<ValueType DstVT, ValueType SrcVT, 3651 RegisterClass DstRC> : 3652 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>; 3653 3654 class MSABitconvertReverseHInDPat<ValueType DstVT, ValueType SrcVT, 3655 RegisterClass DstRC> : 3656 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>; 3657 3658 class MSABitconvertReverseWInDPat<ValueType DstVT, ValueType SrcVT, 3659 RegisterClass DstRC> : 3660 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_W, MSA128W>; 3661 3662 def : MSABitconvertReverseBInHPat<v8i16, v16i8, MSA128H>; 3663 def : MSABitconvertReverseBInHPat<v8f16, v16i8, MSA128H>; 3664 def : MSABitconvertReverseBInWPat<v4i32, v16i8, MSA128W>; 3665 def : MSABitconvertReverseBInWPat<v4f32, v16i8, MSA128W>; 3666 def : MSABitconvertReverseBInDPat<v2i64, v16i8, MSA128D>; 3667 def : MSABitconvertReverseBInDPat<v2f64, v16i8, MSA128D>; 3668 3669 def : MSABitconvertReverseBInHPat<v16i8, v8i16, MSA128B>; 3670 def : MSABitconvertReverseHInWPat<v4i32, v8i16, MSA128W>; 3671 def : MSABitconvertReverseHInWPat<v4f32, v8i16, MSA128W>; 3672 def : MSABitconvertReverseHInDPat<v2i64, v8i16, MSA128D>; 3673 def : MSABitconvertReverseHInDPat<v2f64, v8i16, MSA128D>; 3674 3675 def : MSABitconvertReverseBInHPat<v16i8, v8f16, MSA128B>; 3676 def : MSABitconvertReverseHInWPat<v4i32, v8f16, MSA128W>; 3677 def : MSABitconvertReverseHInWPat<v4f32, v8f16, MSA128W>; 3678 def : MSABitconvertReverseHInDPat<v2i64, v8f16, MSA128D>; 3679 def : MSABitconvertReverseHInDPat<v2f64, v8f16, MSA128D>; 3680 3681 def : MSABitconvertReverseBInWPat<v16i8, v4i32, MSA128B>; 3682 def : MSABitconvertReverseHInWPat<v8i16, v4i32, MSA128H>; 3683 def : MSABitconvertReverseHInWPat<v8f16, v4i32, MSA128H>; 3684 def : MSABitconvertReverseWInDPat<v2i64, v4i32, MSA128D>; 3685 def : MSABitconvertReverseWInDPat<v2f64, v4i32, MSA128D>; 3686 3687 def : MSABitconvertReverseBInWPat<v16i8, v4f32, MSA128B>; 3688 def : MSABitconvertReverseHInWPat<v8i16, v4f32, MSA128H>; 3689 def : MSABitconvertReverseHInWPat<v8f16, v4f32, MSA128H>; 3690 def : MSABitconvertReverseWInDPat<v2i64, v4f32, MSA128D>; 3691 def : MSABitconvertReverseWInDPat<v2f64, v4f32, MSA128D>; 3692 3693 def : MSABitconvertReverseBInDPat<v16i8, v2i64, MSA128B>; 3694 def : MSABitconvertReverseHInDPat<v8i16, v2i64, MSA128H>; 3695 def : MSABitconvertReverseHInDPat<v8f16, v2i64, MSA128H>; 3696 def : MSABitconvertReverseWInDPat<v4i32, v2i64, MSA128W>; 3697 def : MSABitconvertReverseWInDPat<v4f32, v2i64, MSA128W>; 3698 3699 def : MSABitconvertReverseBInDPat<v16i8, v2f64, MSA128B>; 3700 def : MSABitconvertReverseHInDPat<v8i16, v2f64, MSA128H>; 3701 def : MSABitconvertReverseHInDPat<v8f16, v2f64, MSA128H>; 3702 def : MSABitconvertReverseWInDPat<v4i32, v2f64, MSA128W>; 3703 def : MSABitconvertReverseWInDPat<v4f32, v2f64, MSA128W>; 3704 3705 // Pseudos used to implement BNZ.df, and BZ.df 3706 3707 class MSA_CBRANCH_PSEUDO_DESC_BASE<SDPatternOperator OpNode, ValueType TyNode, 3708 RegisterClass RCWS, 3709 InstrItinClass itin = NoItinerary> : 3710 MipsPseudo<(outs GPR32:$dst), 3711 (ins RCWS:$ws), 3712 [(set GPR32:$dst, (OpNode (TyNode RCWS:$ws)))]> { 3713 bit usesCustomInserter = 1; 3714 } 3715 3716 def SNZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v16i8, 3717 MSA128B, NoItinerary>; 3718 def SNZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v8i16, 3719 MSA128H, NoItinerary>; 3720 def SNZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v4i32, 3721 MSA128W, NoItinerary>; 3722 def SNZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v2i64, 3723 MSA128D, NoItinerary>; 3724 def SNZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyNonZero, v16i8, 3725 MSA128B, NoItinerary>; 3726 3727 def SZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v16i8, 3728 MSA128B, NoItinerary>; 3729 def SZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v8i16, 3730 MSA128H, NoItinerary>; 3731 def SZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v4i32, 3732 MSA128W, NoItinerary>; 3733 def SZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v2i64, 3734 MSA128D, NoItinerary>; 3735 def SZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyZero, v16i8, 3736 MSA128B, NoItinerary>; 3737 3738 // Vector extraction with fixed index. 3739 // 3740 // Extracting 32-bit values on MSA32 should always use COPY_S_W rather than 3741 // COPY_U_W, even for the zero-extended case. This is because our forward 3742 // compatibility strategy is to consider registers to be infinitely 3743 // sign-extended so that a MIPS64 can execute MIPS32 code without getting 3744 // different register values. 3745 def : MSAPat<(vextract_zext_i32 (v4i32 MSA128W:$ws), immZExt2Ptr:$idx), 3746 (COPY_S_W MSA128W:$ws, immZExt2:$idx)>, ASE_MSA_NOT_MSA64; 3747 def : MSAPat<(vextract_zext_i32 (v4f32 MSA128W:$ws), immZExt2Ptr:$idx), 3748 (COPY_S_W MSA128W:$ws, immZExt2:$idx)>, ASE_MSA_NOT_MSA64; 3749 3750 // Extracting 64-bit values on MSA64 should always use COPY_S_D rather than 3751 // COPY_U_D, even for the zero-extended case. This is because our forward 3752 // compatibility strategy is to consider registers to be infinitely 3753 // sign-extended so that a hypothetical MIPS128 would be able to execute MIPS64 3754 // code without getting different register values. 3755 def : MSAPat<(vextract_zext_i64 (v2i64 MSA128D:$ws), immZExt1Ptr:$idx), 3756 (COPY_S_D MSA128D:$ws, immZExt1:$idx)>, ASE_MSA64; 3757 def : MSAPat<(vextract_zext_i64 (v2f64 MSA128D:$ws), immZExt1Ptr:$idx), 3758 (COPY_S_D MSA128D:$ws, immZExt1:$idx)>, ASE_MSA64; 3759 3760 // Vector extraction with variable index 3761 def : MSAPat<(i32 (vextract_sext_i8 v16i8:$ws, i32:$idx)), 3762 (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws, 3763 i32:$idx), 3764 sub_lo)), 3765 GPR32), (i32 24))>; 3766 def : MSAPat<(i32 (vextract_sext_i16 v8i16:$ws, i32:$idx)), 3767 (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws, 3768 i32:$idx), 3769 sub_lo)), 3770 GPR32), (i32 16))>; 3771 def : MSAPat<(i32 (vextract_sext_i32 v4i32:$ws, i32:$idx)), 3772 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws, 3773 i32:$idx), 3774 sub_lo)), 3775 GPR32)>; 3776 def : MSAPat<(i64 (vextract_sext_i64 v2i64:$ws, i32:$idx)), 3777 (COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws, 3778 i32:$idx), 3779 sub_64)), 3780 GPR64), [HasMSA, IsGP64bit]>; 3781 3782 def : MSAPat<(i32 (vextract_zext_i8 v16i8:$ws, i32:$idx)), 3783 (SRL (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws, 3784 i32:$idx), 3785 sub_lo)), 3786 GPR32), (i32 24))>; 3787 def : MSAPat<(i32 (vextract_zext_i16 v8i16:$ws, i32:$idx)), 3788 (SRL (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws, 3789 i32:$idx), 3790 sub_lo)), 3791 GPR32), (i32 16))>; 3792 def : MSAPat<(i32 (vextract_zext_i32 v4i32:$ws, i32:$idx)), 3793 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws, 3794 i32:$idx), 3795 sub_lo)), 3796 GPR32)>; 3797 def : MSAPat<(i64 (vextract_zext_i64 v2i64:$ws, i32:$idx)), 3798 (COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws, 3799 i32:$idx), 3800 sub_64)), 3801 GPR64), [HasMSA, IsGP64bit]>; 3802 3803 def : MSAPat<(f32 (vector_extract v4f32:$ws, i32:$idx)), 3804 (f32 (EXTRACT_SUBREG (SPLAT_W v4f32:$ws, 3805 i32:$idx), 3806 sub_lo))>; 3807 def : MSAPat<(f64 (vector_extract v2f64:$ws, i32:$idx)), 3808 (f64 (EXTRACT_SUBREG (SPLAT_D v2f64:$ws, 3809 i32:$idx), 3810 sub_64))>; 3811 3812 // Vector extraction with variable index (N64 ABI) 3813 def : MSAPat< 3814 (i32 (vextract_sext_i8 v16i8:$ws, i64:$idx)), 3815 (SRA (COPY_TO_REGCLASS 3816 (i32 (EXTRACT_SUBREG 3817 (SPLAT_B v16i8:$ws, 3818 (COPY_TO_REGCLASS 3819 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3820 sub_lo)), 3821 GPR32), 3822 (i32 24))>; 3823 def : MSAPat< 3824 (i32 (vextract_sext_i16 v8i16:$ws, i64:$idx)), 3825 (SRA (COPY_TO_REGCLASS 3826 (i32 (EXTRACT_SUBREG 3827 (SPLAT_H v8i16:$ws, 3828 (COPY_TO_REGCLASS 3829 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3830 sub_lo)), 3831 GPR32), 3832 (i32 16))>; 3833 def : MSAPat< 3834 (i32 (vextract_sext_i32 v4i32:$ws, i64:$idx)), 3835 (COPY_TO_REGCLASS 3836 (i32 (EXTRACT_SUBREG 3837 (SPLAT_W v4i32:$ws, 3838 (COPY_TO_REGCLASS 3839 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3840 sub_lo)), 3841 GPR32)>; 3842 def : MSAPat< 3843 (i64 (vextract_sext_i64 v2i64:$ws, i64:$idx)), 3844 (COPY_TO_REGCLASS 3845 (i64 (EXTRACT_SUBREG 3846 (SPLAT_D v2i64:$ws, 3847 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3848 sub_64)), 3849 GPR64), [HasMSA, IsGP64bit]>; 3850 3851 def : MSAPat< 3852 (i32 (vextract_zext_i8 v16i8:$ws, i64:$idx)), 3853 (SRL (COPY_TO_REGCLASS 3854 (i32 (EXTRACT_SUBREG 3855 (SPLAT_B v16i8:$ws, 3856 (COPY_TO_REGCLASS 3857 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3858 sub_lo)), 3859 GPR32), 3860 (i32 24))>; 3861 def : MSAPat< 3862 (i32 (vextract_zext_i16 v8i16:$ws, i64:$idx)), 3863 (SRL (COPY_TO_REGCLASS 3864 (i32 (EXTRACT_SUBREG 3865 (SPLAT_H v8i16:$ws, 3866 (COPY_TO_REGCLASS 3867 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3868 sub_lo)), 3869 GPR32), 3870 (i32 16))>; 3871 def : MSAPat< 3872 (i32 (vextract_zext_i32 v4i32:$ws, i64:$idx)), 3873 (COPY_TO_REGCLASS 3874 (i32 (EXTRACT_SUBREG 3875 (SPLAT_W v4i32:$ws, 3876 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3877 sub_lo)), 3878 GPR32)>; 3879 def : MSAPat< 3880 (i64 (vextract_zext_i64 v2i64:$ws, i64:$idx)), 3881 (COPY_TO_REGCLASS 3882 (i64 (EXTRACT_SUBREG 3883 (SPLAT_D v2i64:$ws, 3884 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3885 sub_64)), 3886 GPR64), 3887 [HasMSA, IsGP64bit]>; 3888 3889 def : MSAPat< 3890 (f32 (vector_extract v4f32:$ws, i64:$idx)), 3891 (f32 (EXTRACT_SUBREG 3892 (SPLAT_W v4f32:$ws, 3893 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3894 sub_lo))>; 3895 def : MSAPat< 3896 (f64 (vector_extract v2f64:$ws, i64:$idx)), 3897 (f64 (EXTRACT_SUBREG 3898 (SPLAT_D v2f64:$ws, 3899 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3900 sub_64))>; 3901
