1 //===- PPCCallingConv.td - Calling Conventions for PowerPC -*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This describes the calling conventions for the PowerPC 32- and 64-bit 11 // architectures. 12 // 13 //===----------------------------------------------------------------------===// 14 15 /// CCIfSubtarget - Match if the current subtarget has a feature F. 16 class CCIfSubtarget<string F, CCAction A> 17 : CCIf<!strconcat("static_cast<const PPCSubtarget&>" 18 "(State.getMachineFunction().getSubtarget()).", 19 F), 20 A>; 21 class CCIfNotSubtarget<string F, CCAction A> 22 : CCIf<!strconcat("!static_cast<const PPCSubtarget&>" 23 "(State.getMachineFunction().getSubtarget()).", 24 F), 25 A>; 26 27 //===----------------------------------------------------------------------===// 28 // Return Value Calling Convention 29 //===----------------------------------------------------------------------===// 30 31 // PPC64 AnyReg return-value convention. No explicit register is specified for 32 // the return-value. The register allocator is allowed and expected to choose 33 // any free register. 34 // 35 // This calling convention is currently only supported by the stackmap and 36 // patchpoint intrinsics. All other uses will result in an assert on Debug 37 // builds. On Release builds we fallback to the PPC C calling convention. 38 def RetCC_PPC64_AnyReg : CallingConv<[ 39 CCCustom<"CC_PPC_AnyReg_Error"> 40 ]>; 41 42 // Return-value convention for PowerPC 43 def RetCC_PPC : CallingConv<[ 44 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<RetCC_PPC64_AnyReg>>, 45 46 // On PPC64, integer return values are always promoted to i64 47 CCIfType<[i32, i1], CCIfSubtarget<"isPPC64()", CCPromoteToType<i64>>>, 48 CCIfType<[i1], CCIfNotSubtarget<"isPPC64()", CCPromoteToType<i32>>>, 49 50 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>, 51 CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6]>>, 52 CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>, 53 54 // Floating point types returned as "direct" go into F1 .. F8; note that 55 // only the ELFv2 ABI fully utilizes all these registers. 56 CCIfType<[f32], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>, 57 CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>, 58 59 // QPX vectors are returned in QF1 and QF2. 60 CCIfType<[v4f64, v4f32, v4i1], 61 CCIfSubtarget<"hasQPX()", CCAssignToReg<[QF1, QF2]>>>, 62 63 // Vector types returned as "direct" go into V2 .. V9; note that only the 64 // ELFv2 ABI fully utilizes all these registers. 65 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32], 66 CCIfSubtarget<"hasAltivec()", 67 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>>, 68 CCIfType<[v2f64, v2i64], CCIfSubtarget<"hasVSX()", 69 CCAssignToReg<[VSH2, VSH3, VSH4, VSH5, VSH6, VSH7, VSH8, VSH9]>>> 70 ]>; 71 72 // No explicit register is specified for the AnyReg calling convention. The 73 // register allocator may assign the arguments to any free register. 74 // 75 // This calling convention is currently only supported by the stackmap and 76 // patchpoint intrinsics. All other uses will result in an assert on Debug 77 // builds. On Release builds we fallback to the PPC C calling convention. 78 def CC_PPC64_AnyReg : CallingConv<[ 79 CCCustom<"CC_PPC_AnyReg_Error"> 80 ]>; 81 82 // Note that we don't currently have calling conventions for 64-bit 83 // PowerPC, but handle all the complexities of the ABI in the lowering 84 // logic. FIXME: See if the logic can be simplified with use of CCs. 85 // This may require some extensions to current table generation. 86 87 // Simple calling convention for 64-bit ELF PowerPC fast isel. 88 // Only handle ints and floats. All ints are promoted to i64. 89 // Vector types and quadword ints are not handled. 90 def CC_PPC64_ELF_FIS : CallingConv<[ 91 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<CC_PPC64_AnyReg>>, 92 93 CCIfType<[i1], CCPromoteToType<i64>>, 94 CCIfType<[i8], CCPromoteToType<i64>>, 95 CCIfType<[i16], CCPromoteToType<i64>>, 96 CCIfType<[i32], CCPromoteToType<i64>>, 97 CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6, X7, X8, X9, X10]>>, 98 CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>> 99 ]>; 100 101 // Simple return-value convention for 64-bit ELF PowerPC fast isel. 102 // All small ints are promoted to i64. Vector types, quadword ints, 103 // and multiple register returns are "supported" to avoid compile 104 // errors, but none are handled by the fast selector. 105 def RetCC_PPC64_ELF_FIS : CallingConv<[ 106 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<RetCC_PPC64_AnyReg>>, 107 108 CCIfType<[i1], CCPromoteToType<i64>>, 109 CCIfType<[i8], CCPromoteToType<i64>>, 110 CCIfType<[i16], CCPromoteToType<i64>>, 111 CCIfType<[i32], CCPromoteToType<i64>>, 112 CCIfType<[i64], CCAssignToReg<[X3, X4]>>, 113 CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>, 114 CCIfType<[f32], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>, 115 CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>, 116 CCIfType<[v4f64, v4f32, v4i1], 117 CCIfSubtarget<"hasQPX()", CCAssignToReg<[QF1, QF2]>>>, 118 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32], 119 CCIfSubtarget<"hasAltivec()", 120 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>>, 121 CCIfType<[v2f64, v2i64], CCIfSubtarget<"hasVSX()", 122 CCAssignToReg<[VSH2, VSH3, VSH4, VSH5, VSH6, VSH7, VSH8, VSH9]>>> 123 ]>; 124 125 //===----------------------------------------------------------------------===// 126 // PowerPC System V Release 4 32-bit ABI 127 //===----------------------------------------------------------------------===// 128 129 def CC_PPC32_SVR4_Common : CallingConv<[ 130 CCIfType<[i1], CCPromoteToType<i32>>, 131 132 // The ABI requires i64 to be passed in two adjacent registers with the first 133 // register having an odd register number. 134 CCIfType<[i32], CCIfSplit<CCCustom<"CC_PPC32_SVR4_Custom_AlignArgRegs">>>, 135 136 // The 'nest' parameter, if any, is passed in R11. 137 CCIfNest<CCAssignToReg<[R11]>>, 138 139 // The first 8 integer arguments are passed in integer registers. 140 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>, 141 142 // Make sure the i64 words from a long double are either both passed in 143 // registers or both passed on the stack. 144 CCIfType<[f64], CCIfSplit<CCCustom<"CC_PPC32_SVR4_Custom_AlignFPArgRegs">>>, 145 146 // FP values are passed in F1 - F8. 147 CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>, 148 149 // Split arguments have an alignment of 8 bytes on the stack. 150 CCIfType<[i32], CCIfSplit<CCAssignToStack<4, 8>>>, 151 152 CCIfType<[i32], CCAssignToStack<4, 4>>, 153 154 // Floats are stored in double precision format, thus they have the same 155 // alignment and size as doubles. 156 CCIfType<[f32,f64], CCAssignToStack<8, 8>>, 157 158 // QPX vectors that are stored in double precision need 32-byte alignment. 159 CCIfType<[v4f64, v4i1], CCAssignToStack<32, 32>>, 160 161 // Vectors get 16-byte stack slots that are 16-byte aligned. 162 CCIfType<[v16i8, v8i16, v4i32, v4f32, v2f64, v2i64], CCAssignToStack<16, 16>> 163 ]>; 164 165 // This calling convention puts vector arguments always on the stack. It is used 166 // to assign vector arguments which belong to the variable portion of the 167 // parameter list of a variable argument function. 168 def CC_PPC32_SVR4_VarArg : CallingConv<[ 169 CCDelegateTo<CC_PPC32_SVR4_Common> 170 ]>; 171 172 // In contrast to CC_PPC32_SVR4_VarArg, this calling convention first tries to 173 // put vector arguments in vector registers before putting them on the stack. 174 def CC_PPC32_SVR4 : CallingConv<[ 175 // QPX vectors mirror the scalar FP convention. 176 CCIfType<[v4f64, v4f32, v4i1], CCIfSubtarget<"hasQPX()", 177 CCAssignToReg<[QF1, QF2, QF3, QF4, QF5, QF6, QF7, QF8]>>>, 178 179 // The first 12 Vector arguments are passed in AltiVec registers. 180 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32], 181 CCIfSubtarget<"hasAltivec()", CCAssignToReg<[V2, V3, V4, V5, V6, V7, 182 V8, V9, V10, V11, V12, V13]>>>, 183 CCIfType<[v2f64, v2i64], CCIfSubtarget<"hasVSX()", 184 CCAssignToReg<[VSH2, VSH3, VSH4, VSH5, VSH6, VSH7, VSH8, VSH9, 185 VSH10, VSH11, VSH12, VSH13]>>>, 186 187 CCDelegateTo<CC_PPC32_SVR4_Common> 188 ]>; 189 190 // Helper "calling convention" to handle aggregate by value arguments. 191 // Aggregate by value arguments are always placed in the local variable space 192 // of the caller. This calling convention is only used to assign those stack 193 // offsets in the callers stack frame. 194 // 195 // Still, the address of the aggregate copy in the callers stack frame is passed 196 // in a GPR (or in the parameter list area if all GPRs are allocated) from the 197 // caller to the callee. The location for the address argument is assigned by 198 // the CC_PPC32_SVR4 calling convention. 199 // 200 // The only purpose of CC_PPC32_SVR4_Custom_Dummy is to skip arguments which are 201 // not passed by value. 202 203 def CC_PPC32_SVR4_ByVal : CallingConv<[ 204 CCIfByVal<CCPassByVal<4, 4>>, 205 206 CCCustom<"CC_PPC32_SVR4_Custom_Dummy"> 207 ]>; 208 209 def CSR_Altivec : CalleeSavedRegs<(add V20, V21, V22, V23, V24, V25, V26, V27, 210 V28, V29, V30, V31)>; 211 212 def CSR_Darwin32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20, 213 R21, R22, R23, R24, R25, R26, R27, R28, 214 R29, R30, R31, F14, F15, F16, F17, F18, 215 F19, F20, F21, F22, F23, F24, F25, F26, 216 F27, F28, F29, F30, F31, CR2, CR3, CR4 217 )>; 218 219 def CSR_Darwin32_Altivec : CalleeSavedRegs<(add CSR_Darwin32, CSR_Altivec)>; 220 221 def CSR_SVR432 : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20, 222 R21, R22, R23, R24, R25, R26, R27, R28, 223 R29, R30, R31, F14, F15, F16, F17, F18, 224 F19, F20, F21, F22, F23, F24, F25, F26, 225 F27, F28, F29, F30, F31, CR2, CR3, CR4 226 )>; 227 228 def CSR_SVR432_Altivec : CalleeSavedRegs<(add CSR_SVR432, CSR_Altivec)>; 229 230 def CSR_Darwin64 : CalleeSavedRegs<(add X13, X14, X15, X16, X17, X18, X19, X20, 231 X21, X22, X23, X24, X25, X26, X27, X28, 232 X29, X30, X31, F14, F15, F16, F17, F18, 233 F19, F20, F21, F22, F23, F24, F25, F26, 234 F27, F28, F29, F30, F31, CR2, CR3, CR4 235 )>; 236 237 def CSR_Darwin64_Altivec : CalleeSavedRegs<(add CSR_Darwin64, CSR_Altivec)>; 238 239 def CSR_SVR464 : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20, 240 X21, X22, X23, X24, X25, X26, X27, X28, 241 X29, X30, X31, F14, F15, F16, F17, F18, 242 F19, F20, F21, F22, F23, F24, F25, F26, 243 F27, F28, F29, F30, F31, CR2, CR3, CR4 244 )>; 245 246 def CSR_SVR464_Altivec : CalleeSavedRegs<(add CSR_SVR464, CSR_Altivec)>; 247 248 def CSR_SVR464_R2 : CalleeSavedRegs<(add CSR_SVR464, X2)>; 249 250 def CSR_SVR464_R2_Altivec : CalleeSavedRegs<(add CSR_SVR464_Altivec, X2)>; 251 252 def CSR_NoRegs : CalleeSavedRegs<(add)>; 253 254 def CSR_64_AllRegs: CalleeSavedRegs<(add X0, (sequence "X%u", 3, 10), 255 (sequence "X%u", 14, 31), 256 (sequence "F%u", 0, 31), 257 (sequence "CR%u", 0, 7))>; 258 259 def CSR_64_AllRegs_Altivec : CalleeSavedRegs<(add CSR_64_AllRegs, 260 (sequence "V%u", 0, 31))>; 261 262 def CSR_64_AllRegs_VSX : CalleeSavedRegs<(add CSR_64_AllRegs_Altivec, 263 (sequence "VSL%u", 0, 31), 264 (sequence "VSH%u", 0, 31))>; 265 266
