1 //===-- SparcInstrFormats.td - Sparc Instruction Formats ---*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern> 11 : Instruction { 12 field bits<32> Inst; 13 14 let Namespace = "SP"; 15 let Size = 4; 16 17 bits<2> op; 18 let Inst{31-30} = op; // Top two bits are the 'op' field 19 20 dag OutOperandList = outs; 21 dag InOperandList = ins; 22 let AsmString = asmstr; 23 let Pattern = pattern; 24 25 let DecoderNamespace = "Sparc"; 26 field bits<32> SoftFail = 0; 27 } 28 29 //===----------------------------------------------------------------------===// 30 // Format #2 instruction classes in the Sparc 31 //===----------------------------------------------------------------------===// 32 33 // Format 2 instructions 34 class F2<dag outs, dag ins, string asmstr, list<dag> pattern> 35 : InstSP<outs, ins, asmstr, pattern> { 36 bits<3> op2; 37 bits<22> imm22; 38 let op = 0; // op = 0 39 let Inst{24-22} = op2; 40 let Inst{21-0} = imm22; 41 } 42 43 // Specific F2 classes: SparcV8 manual, page 44 44 // 45 class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern> 46 : F2<outs, ins, asmstr, pattern> { 47 bits<5> rd; 48 49 let op2 = op2Val; 50 51 let Inst{29-25} = rd; 52 } 53 54 class F2_2<bits<3> op2Val, bit annul, dag outs, dag ins, string asmstr, 55 list<dag> pattern> : F2<outs, ins, asmstr, pattern> { 56 bits<4> cond; 57 let op2 = op2Val; 58 59 let Inst{29} = annul; 60 let Inst{28-25} = cond; 61 } 62 63 class F2_3<bits<3> op2Val, bit annul, bit pred, 64 dag outs, dag ins, string asmstr, list<dag> pattern> 65 : InstSP<outs, ins, asmstr, pattern> { 66 bits<2> cc; 67 bits<4> cond; 68 bits<19> imm19; 69 70 let op = 0; // op = 0 71 72 let Inst{29} = annul; 73 let Inst{28-25} = cond; 74 let Inst{24-22} = op2Val; 75 let Inst{21-20} = cc; 76 let Inst{19} = pred; 77 let Inst{18-0} = imm19; 78 } 79 80 class F2_4<bits<3> cond, bit annul, bit pred, 81 dag outs, dag ins, string asmstr, list<dag> pattern> 82 : InstSP<outs, ins, asmstr, pattern> { 83 bits<16> imm16; 84 bits<5> rs1; 85 86 let op = 0; // op = 0 87 88 let Inst{29} = annul; 89 let Inst{28} = 0; 90 let Inst{27-25} = cond; 91 let Inst{24-22} = 0b011; 92 let Inst{21-20} = imm16{15-14}; 93 let Inst{19} = pred; 94 let Inst{18-14} = rs1; 95 let Inst{13-0} = imm16{13-0}; 96 } 97 98 99 //===----------------------------------------------------------------------===// 100 // Format #3 instruction classes in the Sparc 101 //===----------------------------------------------------------------------===// 102 103 class F3<dag outs, dag ins, string asmstr, list<dag> pattern> 104 : InstSP<outs, ins, asmstr, pattern> { 105 bits<5> rd; 106 bits<6> op3; 107 bits<5> rs1; 108 let op{1} = 1; // Op = 2 or 3 109 let Inst{29-25} = rd; 110 let Inst{24-19} = op3; 111 let Inst{18-14} = rs1; 112 } 113 114 // Specific F3 classes: SparcV8 manual, page 44 115 // 116 class F3_1_asi<bits<2> opVal, bits<6> op3val, dag outs, dag ins, 117 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { 118 bits<8> asi; 119 bits<5> rs2; 120 121 let op = opVal; 122 let op3 = op3val; 123 124 let Inst{13} = 0; // i field = 0 125 let Inst{12-5} = asi; // address space identifier 126 let Inst{4-0} = rs2; 127 } 128 129 class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins, string asmstr, 130 list<dag> pattern> : F3_1_asi<opVal, op3val, outs, ins, 131 asmstr, pattern> { 132 let asi = 0; 133 } 134 135 class F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins, 136 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { 137 bits<13> simm13; 138 139 let op = opVal; 140 let op3 = op3val; 141 142 let Inst{13} = 1; // i field = 1 143 let Inst{12-0} = simm13; 144 } 145 146 // floating-point 147 class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins, 148 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { 149 bits<5> rs2; 150 151 let op = opVal; 152 let op3 = op3val; 153 154 let Inst{13-5} = opfval; // fp opcode 155 let Inst{4-0} = rs2; 156 } 157 158 // floating-point unary operations. 159 class F3_3u<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins, 160 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { 161 bits<5> rs2; 162 163 let op = opVal; 164 let op3 = op3val; 165 let rs1 = 0; 166 167 let Inst{13-5} = opfval; // fp opcode 168 let Inst{4-0} = rs2; 169 } 170 171 // floating-point compares. 172 class F3_3c<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins, 173 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { 174 bits<5> rs2; 175 176 let op = opVal; 177 let op3 = op3val; 178 179 let Inst{13-5} = opfval; // fp opcode 180 let Inst{4-0} = rs2; 181 } 182 183 // Shift by register rs2. 184 class F3_Sr<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins, 185 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { 186 bit x = xVal; // 1 for 64-bit shifts. 187 bits<5> rs2; 188 189 let op = opVal; 190 let op3 = op3val; 191 192 let Inst{13} = 0; // i field = 0 193 let Inst{12} = x; // extended registers. 194 let Inst{4-0} = rs2; 195 } 196 197 // Shift by immediate. 198 class F3_Si<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins, 199 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { 200 bit x = xVal; // 1 for 64-bit shifts. 201 bits<6> shcnt; // shcnt32 / shcnt64. 202 203 let op = opVal; 204 let op3 = op3val; 205 206 let Inst{13} = 1; // i field = 1 207 let Inst{12} = x; // extended registers. 208 let Inst{5-0} = shcnt; 209 } 210 211 // Define rr and ri shift instructions with patterns. 212 multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode, 213 ValueType VT, RegisterClass RC> { 214 def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, IntRegs:$rs2), 215 !strconcat(OpcStr, " $rs1, $rs2, $rd"), 216 [(set VT:$rd, (OpNode VT:$rs1, i32:$rs2))]>; 217 def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, i32imm:$shcnt), 218 !strconcat(OpcStr, " $rs1, $shcnt, $rd"), 219 [(set VT:$rd, (OpNode VT:$rs1, (i32 imm:$shcnt)))]>; 220 } 221 222 class F4<bits<6> op3, dag outs, dag ins, string asmstr, list<dag> pattern> 223 : InstSP<outs, ins, asmstr, pattern> { 224 bits<5> rd; 225 226 let op = 2; 227 let Inst{29-25} = rd; 228 let Inst{24-19} = op3; 229 } 230 231 232 class F4_1<bits<6> op3, dag outs, dag ins, 233 string asmstr, list<dag> pattern> 234 : F4<op3, outs, ins, asmstr, pattern> { 235 236 bit intcc; 237 bits<2> cc; 238 bits<4> cond; 239 bits<5> rs2; 240 241 let Inst{4-0} = rs2; 242 let Inst{12-11} = cc; 243 let Inst{13} = 0; 244 let Inst{17-14} = cond; 245 let Inst{18} = intcc; 246 247 } 248 249 class F4_2<bits<6> op3, dag outs, dag ins, 250 string asmstr, list<dag> pattern> 251 : F4<op3, outs, ins, asmstr, pattern> { 252 bit intcc; 253 bits<2> cc; 254 bits<4> cond; 255 bits<11> simm11; 256 257 let Inst{10-0} = simm11; 258 let Inst{12-11} = cc; 259 let Inst{13} = 1; 260 let Inst{17-14} = cond; 261 let Inst{18} = intcc; 262 } 263 264 class F4_3<bits<6> op3, bits<6> opf_low, dag outs, dag ins, 265 string asmstr, list<dag> pattern> 266 : F4<op3, outs, ins, asmstr, pattern> { 267 bits<4> cond; 268 bit intcc; 269 bits<2> opf_cc; 270 bits<5> rs2; 271 272 let Inst{18} = 0; 273 let Inst{17-14} = cond; 274 let Inst{13} = intcc; 275 let Inst{12-11} = opf_cc; 276 let Inst{10-5} = opf_low; 277 let Inst{4-0} = rs2; 278 } 279 280 class F4_4r<bits<6> op3, bits<5> opf_low, bits<3> rcond, dag outs, dag ins, 281 string asmstr, list<dag> pattern> 282 : F4<op3, outs, ins, asmstr, pattern> { 283 bits <5> rs1; 284 bits <5> rs2; 285 let Inst{18-14} = rs1; 286 let Inst{13} = 0; // IsImm 287 let Inst{12-10} = rcond; 288 let Inst{9-5} = opf_low; 289 let Inst{4-0} = rs2; 290 } 291 292 293 class F4_4i<bits<6> op3, bits<3> rcond, dag outs, dag ins, 294 string asmstr, list<dag> pattern> 295 : F4<op3, outs, ins, asmstr, pattern> { 296 bits<5> rs1; 297 bits<10> simm10; 298 let Inst{18-14} = rs1; 299 let Inst{13} = 1; // IsImm 300 let Inst{12-10} = rcond; 301 let Inst{9-0} = simm10; 302 } 303 304 305 class TRAPSP<bits<6> op3Val, bit isimm, dag outs, dag ins, string asmstr, 306 list<dag> pattern>: F3<outs, ins, asmstr, pattern> { 307 308 bits<4> cond; 309 bits<2> cc; 310 311 let op = 0b10; 312 let rd{4} = 0; 313 let rd{3-0} = cond; 314 let op3 = op3Val; 315 let Inst{13} = isimm; 316 let Inst{12-11} = cc; 317 318 } 319 320 class TRAPSPrr<bits<6> op3Val, dag outs, dag ins, string asmstr, 321 list<dag> pattern>: TRAPSP<op3Val, 0, outs, ins, asmstr, pattern> { 322 bits<5> rs2; 323 324 let Inst{10-5} = 0; 325 let Inst{4-0} = rs2; 326 } 327 class TRAPSPri<bits<6> op3Val, dag outs, dag ins, string asmstr, 328 list<dag> pattern>: TRAPSP<op3Val, 1, outs, ins, asmstr, pattern> { 329 bits<8> imm; 330 331 let Inst{10-8} = 0; 332 let Inst{7-0} = imm; 333 } 334 335 // Pseudo-instructions for alternate assembly syntax (never used by codegen). 336 // These are aliases that require C++ handling to convert to the target 337 // instruction, while InstAliases can be handled directly by tblgen. 338 class AsmPseudoInst<dag outs, dag ins, string asm> 339 : InstSP<outs, ins, asm, []> { 340 let isPseudo = 1; 341 } 342
