1 //===-- X86InstrExtension.td - Sign and Zero Extensions ----*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the sign and zero extension operations. 11 // 12 //===----------------------------------------------------------------------===// 13 14 let hasSideEffects = 0 in { 15 let Defs = [AX], Uses = [AL] in 16 def CBW : I<0x98, RawFrm, (outs), (ins), 17 "{cbtw|cbw}", [], IIC_CBW>, OpSize16; // AX = signext(AL) 18 let Defs = [EAX], Uses = [AX] in 19 def CWDE : I<0x98, RawFrm, (outs), (ins), 20 "{cwtl|cwde}", [], IIC_CBW>, OpSize32; // EAX = signext(AX) 21 22 let Defs = [AX,DX], Uses = [AX] in 23 def CWD : I<0x99, RawFrm, (outs), (ins), 24 "{cwtd|cwd}", [], IIC_CBW>, OpSize16; // DX:AX = signext(AX) 25 let Defs = [EAX,EDX], Uses = [EAX] in 26 def CDQ : I<0x99, RawFrm, (outs), (ins), 27 "{cltd|cdq}", [], IIC_CBW>, OpSize32; // EDX:EAX = signext(EAX) 28 29 30 let Defs = [RAX], Uses = [EAX] in 31 def CDQE : RI<0x98, RawFrm, (outs), (ins), 32 "{cltq|cdqe}", [], IIC_CBW>; // RAX = signext(EAX) 33 34 let Defs = [RAX,RDX], Uses = [RAX] in 35 def CQO : RI<0x99, RawFrm, (outs), (ins), 36 "{cqto|cqo}", [], IIC_CBW>; // RDX:RAX = signext(RAX) 37 } 38 39 40 41 // Sign/Zero extenders 42 let hasSideEffects = 0 in { 43 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src), 44 "movs{bw|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVSX_R16_R8>, 45 TB, OpSize16, Sched<[WriteALU]>; 46 let mayLoad = 1 in 47 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src), 48 "movs{bw|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVSX_R16_M8>, 49 TB, OpSize16, Sched<[WriteALULd]>; 50 } // hasSideEffects = 0 51 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8:$src), 52 "movs{bl|x}\t{$src, $dst|$dst, $src}", 53 [(set GR32:$dst, (sext GR8:$src))], IIC_MOVSX>, TB, 54 OpSize32, Sched<[WriteALU]>; 55 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src), 56 "movs{bl|x}\t{$src, $dst|$dst, $src}", 57 [(set GR32:$dst, (sextloadi32i8 addr:$src))], IIC_MOVSX>, TB, 58 OpSize32, Sched<[WriteALULd]>; 59 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src), 60 "movs{wl|x}\t{$src, $dst|$dst, $src}", 61 [(set GR32:$dst, (sext GR16:$src))], IIC_MOVSX>, TB, 62 OpSize32, Sched<[WriteALU]>; 63 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src), 64 "movs{wl|x}\t{$src, $dst|$dst, $src}", 65 [(set GR32:$dst, (sextloadi32i16 addr:$src))], IIC_MOVSX>, 66 OpSize32, TB, Sched<[WriteALULd]>; 67 68 let hasSideEffects = 0 in { 69 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src), 70 "movz{bw|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVZX_R16_R8>, 71 TB, OpSize16, Sched<[WriteALU]>; 72 let mayLoad = 1 in 73 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src), 74 "movz{bw|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVZX_R16_M8>, 75 TB, OpSize16, Sched<[WriteALULd]>; 76 } // hasSideEffects = 0 77 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src), 78 "movz{bl|x}\t{$src, $dst|$dst, $src}", 79 [(set GR32:$dst, (zext GR8:$src))], IIC_MOVZX>, TB, 80 OpSize32, Sched<[WriteALU]>; 81 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src), 82 "movz{bl|x}\t{$src, $dst|$dst, $src}", 83 [(set GR32:$dst, (zextloadi32i8 addr:$src))], IIC_MOVZX>, TB, 84 OpSize32, Sched<[WriteALULd]>; 85 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src), 86 "movz{wl|x}\t{$src, $dst|$dst, $src}", 87 [(set GR32:$dst, (zext GR16:$src))], IIC_MOVZX>, TB, 88 OpSize32, Sched<[WriteALU]>; 89 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src), 90 "movz{wl|x}\t{$src, $dst|$dst, $src}", 91 [(set GR32:$dst, (zextloadi32i16 addr:$src))], IIC_MOVZX>, 92 TB, OpSize32, Sched<[WriteALULd]>; 93 94 // These are the same as the regular MOVZX32rr8 and MOVZX32rm8 95 // except that they use GR32_NOREX for the output operand register class 96 // instead of GR32. This allows them to operate on h registers on x86-64. 97 let hasSideEffects = 0, isCodeGenOnly = 1 in { 98 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg, 99 (outs GR32_NOREX:$dst), (ins GR8_NOREX:$src), 100 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX", 101 [], IIC_MOVZX>, TB, Sched<[WriteALU]>; 102 let mayLoad = 1 in 103 def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem, 104 (outs GR32_NOREX:$dst), (ins i8mem_NOREX:$src), 105 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX", 106 [], IIC_MOVZX>, TB, Sched<[WriteALULd]>; 107 108 def MOVSX32_NOREXrr8 : I<0xBE, MRMSrcReg, 109 (outs GR32_NOREX:$dst), (ins GR8_NOREX:$src), 110 "movs{bl|x}\t{$src, $dst|$dst, $src} # NOREX", 111 [], IIC_MOVSX>, TB, Sched<[WriteALU]>; 112 let mayLoad = 1 in 113 def MOVSX32_NOREXrm8 : I<0xBE, MRMSrcMem, 114 (outs GR32_NOREX:$dst), (ins i8mem_NOREX:$src), 115 "movs{bl|x}\t{$src, $dst|$dst, $src} # NOREX", 116 [], IIC_MOVSX>, TB, Sched<[WriteALULd]>; 117 } 118 119 // MOVSX64rr8 always has a REX prefix and it has an 8-bit register 120 // operand, which makes it a rare instruction with an 8-bit register 121 // operand that can never access an h register. If support for h registers 122 // were generalized, this would require a special register class. 123 def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src), 124 "movs{bq|x}\t{$src, $dst|$dst, $src}", 125 [(set GR64:$dst, (sext GR8:$src))], IIC_MOVSX>, TB, 126 Sched<[WriteALU]>; 127 def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src), 128 "movs{bq|x}\t{$src, $dst|$dst, $src}", 129 [(set GR64:$dst, (sextloadi64i8 addr:$src))], IIC_MOVSX>, 130 TB, Sched<[WriteALULd]>; 131 def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src), 132 "movs{wq|x}\t{$src, $dst|$dst, $src}", 133 [(set GR64:$dst, (sext GR16:$src))], IIC_MOVSX>, TB, 134 Sched<[WriteALU]>; 135 def MOVSX64rm16: RI<0xBF, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src), 136 "movs{wq|x}\t{$src, $dst|$dst, $src}", 137 [(set GR64:$dst, (sextloadi64i16 addr:$src))], IIC_MOVSX>, 138 TB, Sched<[WriteALULd]>; 139 def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src), 140 "movs{lq|xd}\t{$src, $dst|$dst, $src}", 141 [(set GR64:$dst, (sext GR32:$src))], IIC_MOVSX>, 142 Sched<[WriteALU]>, Requires<[In64BitMode]>; 143 def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src), 144 "movs{lq|xd}\t{$src, $dst|$dst, $src}", 145 [(set GR64:$dst, (sextloadi64i32 addr:$src))], IIC_MOVSX>, 146 Sched<[WriteALULd]>, Requires<[In64BitMode]>; 147 148 // movzbq and movzwq encodings for the disassembler 149 def MOVZX64rr8_Q : RI<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8:$src), 150 "movz{bq|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVZX>, 151 TB, Sched<[WriteALU]>; 152 def MOVZX64rm8_Q : RI<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem:$src), 153 "movz{bq|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVZX>, 154 TB, Sched<[WriteALULd]>; 155 def MOVZX64rr16_Q : RI<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src), 156 "movz{wq|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVZX>, 157 TB, Sched<[WriteALU]>; 158 def MOVZX64rm16_Q : RI<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src), 159 "movz{wq|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVZX>, 160 TB, Sched<[WriteALULd]>; 161 162 // 64-bit zero-extension patterns use SUBREG_TO_REG and an operation writing a 163 // 32-bit register. 164 def : Pat<(i64 (zext GR8:$src)), 165 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8:$src), sub_32bit)>; 166 def : Pat<(zextloadi64i8 addr:$src), 167 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; 168 169 def : Pat<(i64 (zext GR16:$src)), 170 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16:$src), sub_32bit)>; 171 def : Pat<(zextloadi64i16 addr:$src), 172 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>; 173 174 // The preferred way to do 32-bit-to-64-bit zero extension on x86-64 is to use a 175 // SUBREG_TO_REG to utilize implicit zero-extension, however this isn't possible 176 // when the 32-bit value is defined by a truncate or is copied from something 177 // where the high bits aren't necessarily all zero. In such cases, we fall back 178 // to these explicit zext instructions. 179 def : Pat<(i64 (zext GR32:$src)), 180 (SUBREG_TO_REG (i64 0), (MOV32rr GR32:$src), sub_32bit)>; 181 def : Pat<(i64 (zextloadi64i32 addr:$src)), 182 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>; 183
