1 //===-- X86InstrFMA.td - FMA Instruction Set ---------------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes FMA (Fused Multiply-Add) instructions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 //===----------------------------------------------------------------------===// 15 // FMA3 - Intel 3 operand Fused Multiply-Add instructions 16 //===----------------------------------------------------------------------===// 17 18 // For all FMA opcodes declared in fma3p_rm and fma3s_rm milticlasses defined 19 // below, both the register and memory variants are commutable. 20 // For the register form the commutable operands are 1, 2 and 3. 21 // For the memory variant the folded operand must be in 3. Thus, 22 // in that case, only the operands 1 and 2 can be swapped. 23 // Commuting some of operands may require the opcode change. 24 // FMA*213*: 25 // operands 1 and 2 (memory & register forms): *213* --> *213*(no changes); 26 // operands 1 and 3 (register forms only): *213* --> *231*; 27 // operands 2 and 3 (register forms only): *213* --> *132*. 28 // FMA*132*: 29 // operands 1 and 2 (memory & register forms): *132* --> *231*; 30 // operands 1 and 3 (register forms only): *132* --> *132*(no changes); 31 // operands 2 and 3 (register forms only): *132* --> *213*. 32 // FMA*231*: 33 // operands 1 and 2 (memory & register forms): *231* --> *132*; 34 // operands 1 and 3 (register forms only): *231* --> *213*; 35 // operands 2 and 3 (register forms only): *231* --> *231*(no changes). 36 37 let Constraints = "$src1 = $dst", hasSideEffects = 0, isCommutable = 1 in 38 multiclass fma3p_rm<bits<8> opc, string OpcodeStr, 39 PatFrag MemFrag128, PatFrag MemFrag256, 40 ValueType OpVT128, ValueType OpVT256, 41 SDPatternOperator Op = null_frag> { 42 let usesCustomInserter = 1 in 43 def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst), 44 (ins VR128:$src1, VR128:$src2, VR128:$src3), 45 !strconcat(OpcodeStr, 46 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), 47 [(set VR128:$dst, (OpVT128 (Op VR128:$src2, 48 VR128:$src1, VR128:$src3)))]>; 49 50 let mayLoad = 1 in 51 def m : FMA3<opc, MRMSrcMem, (outs VR128:$dst), 52 (ins VR128:$src1, VR128:$src2, f128mem:$src3), 53 !strconcat(OpcodeStr, 54 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), 55 [(set VR128:$dst, (OpVT128 (Op VR128:$src2, VR128:$src1, 56 (MemFrag128 addr:$src3))))]>; 57 58 let usesCustomInserter = 1 in 59 def rY : FMA3<opc, MRMSrcReg, (outs VR256:$dst), 60 (ins VR256:$src1, VR256:$src2, VR256:$src3), 61 !strconcat(OpcodeStr, 62 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), 63 [(set VR256:$dst, (OpVT256 (Op VR256:$src2, VR256:$src1, 64 VR256:$src3)))]>, VEX_L; 65 66 let mayLoad = 1 in 67 def mY : FMA3<opc, MRMSrcMem, (outs VR256:$dst), 68 (ins VR256:$src1, VR256:$src2, f256mem:$src3), 69 !strconcat(OpcodeStr, 70 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), 71 [(set VR256:$dst, 72 (OpVT256 (Op VR256:$src2, VR256:$src1, 73 (MemFrag256 addr:$src3))))]>, VEX_L; 74 } 75 76 multiclass fma3p_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231, 77 string OpcodeStr, string PackTy, 78 PatFrag MemFrag128, PatFrag MemFrag256, 79 SDNode Op, ValueType OpTy128, ValueType OpTy256> { 80 defm r213 : fma3p_rm<opc213, 81 !strconcat(OpcodeStr, "213", PackTy), 82 MemFrag128, MemFrag256, OpTy128, OpTy256, Op>; 83 defm r132 : fma3p_rm<opc132, 84 !strconcat(OpcodeStr, "132", PackTy), 85 MemFrag128, MemFrag256, OpTy128, OpTy256>; 86 defm r231 : fma3p_rm<opc231, 87 !strconcat(OpcodeStr, "231", PackTy), 88 MemFrag128, MemFrag256, OpTy128, OpTy256>; 89 } 90 91 // Fused Multiply-Add 92 let ExeDomain = SSEPackedSingle in { 93 defm VFMADDPS : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "ps", loadv4f32, 94 loadv8f32, X86Fmadd, v4f32, v8f32>; 95 defm VFMSUBPS : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "ps", loadv4f32, 96 loadv8f32, X86Fmsub, v4f32, v8f32>; 97 defm VFMADDSUBPS : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "ps", 98 loadv4f32, loadv8f32, X86Fmaddsub, 99 v4f32, v8f32>; 100 defm VFMSUBADDPS : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "ps", 101 loadv4f32, loadv8f32, X86Fmsubadd, 102 v4f32, v8f32>; 103 } 104 105 let ExeDomain = SSEPackedDouble in { 106 defm VFMADDPD : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "pd", loadv2f64, 107 loadv4f64, X86Fmadd, v2f64, v4f64>, VEX_W; 108 defm VFMSUBPD : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "pd", loadv2f64, 109 loadv4f64, X86Fmsub, v2f64, v4f64>, VEX_W; 110 defm VFMADDSUBPD : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "pd", 111 loadv2f64, loadv4f64, X86Fmaddsub, 112 v2f64, v4f64>, VEX_W; 113 defm VFMSUBADDPD : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "pd", 114 loadv2f64, loadv4f64, X86Fmsubadd, 115 v2f64, v4f64>, VEX_W; 116 } 117 118 // Fused Negative Multiply-Add 119 let ExeDomain = SSEPackedSingle in { 120 defm VFNMADDPS : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "ps", loadv4f32, 121 loadv8f32, X86Fnmadd, v4f32, v8f32>; 122 defm VFNMSUBPS : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "ps", loadv4f32, 123 loadv8f32, X86Fnmsub, v4f32, v8f32>; 124 } 125 let ExeDomain = SSEPackedDouble in { 126 defm VFNMADDPD : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "pd", loadv2f64, 127 loadv4f64, X86Fnmadd, v2f64, v4f64>, VEX_W; 128 defm VFNMSUBPD : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "pd", 129 loadv2f64, loadv4f64, X86Fnmsub, v2f64, 130 v4f64>, VEX_W; 131 } 132 133 // All source register operands of FMA opcodes defined in fma3s_rm multiclass 134 // can be commuted. In many cases such commute transformation requres an opcode 135 // adjustment, for example, commuting the operands 1 and 2 in FMA*132 form 136 // would require an opcode change to FMA*231: 137 // FMA*132* reg1, reg2, reg3; // reg1 * reg3 + reg2; 138 // --> 139 // FMA*231* reg2, reg1, reg3; // reg1 * reg3 + reg2; 140 // Please see more detailed comment at the very beginning of the section 141 // defining FMA3 opcodes above. 142 let Constraints = "$src1 = $dst", isCommutable = 1, hasSideEffects = 0 in 143 multiclass fma3s_rm<bits<8> opc, string OpcodeStr, 144 X86MemOperand x86memop, RegisterClass RC, 145 SDPatternOperator OpNode = null_frag> { 146 let usesCustomInserter = 1 in 147 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst), 148 (ins RC:$src1, RC:$src2, RC:$src3), 149 !strconcat(OpcodeStr, 150 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), 151 [(set RC:$dst, (OpNode RC:$src2, RC:$src1, RC:$src3))]>; 152 153 let mayLoad = 1 in 154 def m : FMA3<opc, MRMSrcMem, (outs RC:$dst), 155 (ins RC:$src1, RC:$src2, x86memop:$src3), 156 !strconcat(OpcodeStr, 157 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), 158 [(set RC:$dst, 159 (OpNode RC:$src2, RC:$src1, (load addr:$src3)))]>; 160 } 161 162 // These FMA*_Int instructions are defined specially for being used when 163 // the scalar FMA intrinsics are lowered to machine instructions, and in that 164 // sense, they are similar to existing ADD*_Int, SUB*_Int, MUL*_Int, etc. 165 // instructions. 166 // 167 // All of the FMA*_Int opcodes are defined as commutable here. 168 // Commuting the 2nd and 3rd source register operands of FMAs is quite trivial 169 // and the corresponding optimizations have been developed. 170 // Commuting the 1st operand of FMA*_Int requires some additional analysis, 171 // the commute optimization is legal only if all users of FMA*_Int use only 172 // the lowest element of the FMA*_Int instruction. Even though such analysis 173 // may be not implemented yet we allow the routines doing the actual commute 174 // transformation to decide if one or another instruction is commutable or not. 175 let Constraints = "$src1 = $dst", isCommutable = 1, isCodeGenOnly = 1, 176 hasSideEffects = 0 in 177 multiclass fma3s_rm_int<bits<8> opc, string OpcodeStr, 178 Operand memopr, RegisterClass RC> { 179 def r_Int : FMA3<opc, MRMSrcReg, (outs RC:$dst), 180 (ins RC:$src1, RC:$src2, RC:$src3), 181 !strconcat(OpcodeStr, 182 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), 183 []>; 184 185 let mayLoad = 1 in 186 def m_Int : FMA3<opc, MRMSrcMem, (outs RC:$dst), 187 (ins RC:$src1, RC:$src2, memopr:$src3), 188 !strconcat(OpcodeStr, 189 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), 190 []>; 191 } 192 193 multiclass fma3s_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231, 194 string OpStr, string PackTy, 195 SDNode OpNode, RegisterClass RC, 196 X86MemOperand x86memop> { 197 defm r132 : fma3s_rm<opc132, !strconcat(OpStr, "132", PackTy), x86memop, RC>; 198 defm r213 : fma3s_rm<opc213, !strconcat(OpStr, "213", PackTy), x86memop, RC, 199 OpNode>; 200 defm r231 : fma3s_rm<opc231, !strconcat(OpStr, "231", PackTy), x86memop, RC>; 201 } 202 203 // The FMA 213 form is created for lowering of scalar FMA intrinscis 204 // to machine instructions. 205 // The FMA 132 form can trivially be get by commuting the 2nd and 3rd operands 206 // of FMA 213 form. 207 // The FMA 231 form can be get only by commuting the 1st operand of 213 or 132 208 // forms and is possible only after special analysis of all uses of the initial 209 // instruction. Such analysis do not exist yet and thus introducing the 231 210 // form of FMA*_Int instructions is done using an optimistic assumption that 211 // such analysis will be implemented eventually. 212 multiclass fma3s_int_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231, 213 string OpStr, string PackTy, 214 RegisterClass RC, Operand memop> { 215 defm r132 : fma3s_rm_int<opc132, !strconcat(OpStr, "132", PackTy), 216 memop, RC>; 217 defm r213 : fma3s_rm_int<opc213, !strconcat(OpStr, "213", PackTy), 218 memop, RC>; 219 defm r231 : fma3s_rm_int<opc231, !strconcat(OpStr, "231", PackTy), 220 memop, RC>; 221 } 222 223 multiclass fma3s<bits<8> opc132, bits<8> opc213, bits<8> opc231, 224 string OpStr, Intrinsic IntF32, Intrinsic IntF64, 225 SDNode OpNode> { 226 let ExeDomain = SSEPackedSingle in 227 defm SS : fma3s_forms<opc132, opc213, opc231, OpStr, "ss", OpNode, 228 FR32, f32mem>, 229 fma3s_int_forms<opc132, opc213, opc231, OpStr, "ss", VR128, ssmem>; 230 231 let ExeDomain = SSEPackedDouble in 232 defm SD : fma3s_forms<opc132, opc213, opc231, OpStr, "sd", OpNode, 233 FR64, f64mem>, 234 fma3s_int_forms<opc132, opc213, opc231, OpStr, "sd", VR128, sdmem>, 235 VEX_W; 236 237 // These patterns use the 123 ordering, instead of 213, even though 238 // they match the intrinsic to the 213 version of the instruction. 239 // This is because src1 is tied to dest, and the scalar intrinsics 240 // require the pass-through values to come from the first source 241 // operand, not the second. 242 def : Pat<(IntF32 VR128:$src1, VR128:$src2, VR128:$src3), 243 (COPY_TO_REGCLASS(!cast<Instruction>(NAME#"SSr213r_Int") 244 $src1, $src2, $src3), VR128)>; 245 246 def : Pat<(IntF64 VR128:$src1, VR128:$src2, VR128:$src3), 247 (COPY_TO_REGCLASS(!cast<Instruction>(NAME#"SDr213r_Int") 248 $src1, $src2, $src3), VR128)>; 249 } 250 251 defm VFMADD : fma3s<0x99, 0xA9, 0xB9, "vfmadd", int_x86_fma_vfmadd_ss, 252 int_x86_fma_vfmadd_sd, X86Fmadd>, VEX_LIG; 253 defm VFMSUB : fma3s<0x9B, 0xAB, 0xBB, "vfmsub", int_x86_fma_vfmsub_ss, 254 int_x86_fma_vfmsub_sd, X86Fmsub>, VEX_LIG; 255 256 defm VFNMADD : fma3s<0x9D, 0xAD, 0xBD, "vfnmadd", int_x86_fma_vfnmadd_ss, 257 int_x86_fma_vfnmadd_sd, X86Fnmadd>, VEX_LIG; 258 defm VFNMSUB : fma3s<0x9F, 0xAF, 0xBF, "vfnmsub", int_x86_fma_vfnmsub_ss, 259 int_x86_fma_vfnmsub_sd, X86Fnmsub>, VEX_LIG; 260 261 262 //===----------------------------------------------------------------------===// 263 // FMA4 - AMD 4 operand Fused Multiply-Add instructions 264 //===----------------------------------------------------------------------===// 265 266 267 multiclass fma4s<bits<8> opc, string OpcodeStr, RegisterClass RC, 268 X86MemOperand x86memop, ValueType OpVT, SDNode OpNode, 269 PatFrag mem_frag> { 270 let isCommutable = 1 in 271 def rr : FMA4<opc, MRMSrcReg, (outs RC:$dst), 272 (ins RC:$src1, RC:$src2, RC:$src3), 273 !strconcat(OpcodeStr, 274 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 275 [(set RC:$dst, 276 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>, VEX_W, VEX_LIG, MemOp4; 277 def rm : FMA4<opc, MRMSrcMem, (outs RC:$dst), 278 (ins RC:$src1, RC:$src2, x86memop:$src3), 279 !strconcat(OpcodeStr, 280 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 281 [(set RC:$dst, (OpNode RC:$src1, RC:$src2, 282 (mem_frag addr:$src3)))]>, VEX_W, VEX_LIG, MemOp4; 283 def mr : FMA4<opc, MRMSrcMem, (outs RC:$dst), 284 (ins RC:$src1, x86memop:$src2, RC:$src3), 285 !strconcat(OpcodeStr, 286 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 287 [(set RC:$dst, 288 (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3))]>, VEX_LIG; 289 // For disassembler 290 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in 291 def rr_REV : FMA4<opc, MRMSrcReg, (outs RC:$dst), 292 (ins RC:$src1, RC:$src2, RC:$src3), 293 !strconcat(OpcodeStr, 294 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>, 295 VEX_LIG; 296 } 297 298 multiclass fma4s_int<bits<8> opc, string OpcodeStr, Operand memop, 299 ComplexPattern mem_cpat, Intrinsic Int> { 300 let isCodeGenOnly = 1 in { 301 let isCommutable = 1 in 302 def rr_Int : FMA4<opc, MRMSrcReg, (outs VR128:$dst), 303 (ins VR128:$src1, VR128:$src2, VR128:$src3), 304 !strconcat(OpcodeStr, 305 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 306 [(set VR128:$dst, 307 (Int VR128:$src1, VR128:$src2, VR128:$src3))]>, VEX_W, VEX_LIG, MemOp4; 308 def rm_Int : FMA4<opc, MRMSrcMem, (outs VR128:$dst), 309 (ins VR128:$src1, VR128:$src2, memop:$src3), 310 !strconcat(OpcodeStr, 311 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 312 [(set VR128:$dst, (Int VR128:$src1, VR128:$src2, 313 mem_cpat:$src3))]>, VEX_W, VEX_LIG, MemOp4; 314 def mr_Int : FMA4<opc, MRMSrcMem, (outs VR128:$dst), 315 (ins VR128:$src1, memop:$src2, VR128:$src3), 316 !strconcat(OpcodeStr, 317 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 318 [(set VR128:$dst, 319 (Int VR128:$src1, mem_cpat:$src2, VR128:$src3))]>, VEX_LIG; 320 } // isCodeGenOnly = 1 321 } 322 323 multiclass fma4p<bits<8> opc, string OpcodeStr, SDNode OpNode, 324 ValueType OpVT128, ValueType OpVT256, 325 PatFrag ld_frag128, PatFrag ld_frag256> { 326 let isCommutable = 1 in 327 def rr : FMA4<opc, MRMSrcReg, (outs VR128:$dst), 328 (ins VR128:$src1, VR128:$src2, VR128:$src3), 329 !strconcat(OpcodeStr, 330 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 331 [(set VR128:$dst, 332 (OpVT128 (OpNode VR128:$src1, VR128:$src2, VR128:$src3)))]>, 333 VEX_W, MemOp4; 334 def rm : FMA4<opc, MRMSrcMem, (outs VR128:$dst), 335 (ins VR128:$src1, VR128:$src2, f128mem:$src3), 336 !strconcat(OpcodeStr, 337 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 338 [(set VR128:$dst, (OpNode VR128:$src1, VR128:$src2, 339 (ld_frag128 addr:$src3)))]>, VEX_W, MemOp4; 340 def mr : FMA4<opc, MRMSrcMem, (outs VR128:$dst), 341 (ins VR128:$src1, f128mem:$src2, VR128:$src3), 342 !strconcat(OpcodeStr, 343 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 344 [(set VR128:$dst, 345 (OpNode VR128:$src1, (ld_frag128 addr:$src2), VR128:$src3))]>; 346 let isCommutable = 1 in 347 def rrY : FMA4<opc, MRMSrcReg, (outs VR256:$dst), 348 (ins VR256:$src1, VR256:$src2, VR256:$src3), 349 !strconcat(OpcodeStr, 350 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 351 [(set VR256:$dst, 352 (OpVT256 (OpNode VR256:$src1, VR256:$src2, VR256:$src3)))]>, 353 VEX_W, MemOp4, VEX_L; 354 def rmY : FMA4<opc, MRMSrcMem, (outs VR256:$dst), 355 (ins VR256:$src1, VR256:$src2, f256mem:$src3), 356 !strconcat(OpcodeStr, 357 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 358 [(set VR256:$dst, (OpNode VR256:$src1, VR256:$src2, 359 (ld_frag256 addr:$src3)))]>, VEX_W, MemOp4, VEX_L; 360 def mrY : FMA4<opc, MRMSrcMem, (outs VR256:$dst), 361 (ins VR256:$src1, f256mem:$src2, VR256:$src3), 362 !strconcat(OpcodeStr, 363 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 364 [(set VR256:$dst, (OpNode VR256:$src1, 365 (ld_frag256 addr:$src2), VR256:$src3))]>, VEX_L; 366 // For disassembler 367 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in { 368 def rr_REV : FMA4<opc, MRMSrcReg, (outs VR128:$dst), 369 (ins VR128:$src1, VR128:$src2, VR128:$src3), 370 !strconcat(OpcodeStr, 371 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>; 372 def rrY_REV : FMA4<opc, MRMSrcReg, (outs VR256:$dst), 373 (ins VR256:$src1, VR256:$src2, VR256:$src3), 374 !strconcat(OpcodeStr, 375 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>, 376 VEX_L; 377 } // isCodeGenOnly = 1 378 } 379 380 let ExeDomain = SSEPackedSingle in { 381 // Scalar Instructions 382 defm VFMADDSS4 : fma4s<0x6A, "vfmaddss", FR32, f32mem, f32, X86Fmadd, loadf32>, 383 fma4s_int<0x6A, "vfmaddss", ssmem, sse_load_f32, 384 int_x86_fma_vfmadd_ss>; 385 defm VFMSUBSS4 : fma4s<0x6E, "vfmsubss", FR32, f32mem, f32, X86Fmsub, loadf32>, 386 fma4s_int<0x6E, "vfmsubss", ssmem, sse_load_f32, 387 int_x86_fma_vfmsub_ss>; 388 defm VFNMADDSS4 : fma4s<0x7A, "vfnmaddss", FR32, f32mem, f32, 389 X86Fnmadd, loadf32>, 390 fma4s_int<0x7A, "vfnmaddss", ssmem, sse_load_f32, 391 int_x86_fma_vfnmadd_ss>; 392 defm VFNMSUBSS4 : fma4s<0x7E, "vfnmsubss", FR32, f32mem, f32, 393 X86Fnmsub, loadf32>, 394 fma4s_int<0x7E, "vfnmsubss", ssmem, sse_load_f32, 395 int_x86_fma_vfnmsub_ss>; 396 // Packed Instructions 397 defm VFMADDPS4 : fma4p<0x68, "vfmaddps", X86Fmadd, v4f32, v8f32, 398 loadv4f32, loadv8f32>; 399 defm VFMSUBPS4 : fma4p<0x6C, "vfmsubps", X86Fmsub, v4f32, v8f32, 400 loadv4f32, loadv8f32>; 401 defm VFNMADDPS4 : fma4p<0x78, "vfnmaddps", X86Fnmadd, v4f32, v8f32, 402 loadv4f32, loadv8f32>; 403 defm VFNMSUBPS4 : fma4p<0x7C, "vfnmsubps", X86Fnmsub, v4f32, v8f32, 404 loadv4f32, loadv8f32>; 405 defm VFMADDSUBPS4 : fma4p<0x5C, "vfmaddsubps", X86Fmaddsub, v4f32, v8f32, 406 loadv4f32, loadv8f32>; 407 defm VFMSUBADDPS4 : fma4p<0x5E, "vfmsubaddps", X86Fmsubadd, v4f32, v8f32, 408 loadv4f32, loadv8f32>; 409 } 410 411 let ExeDomain = SSEPackedDouble in { 412 // Scalar Instructions 413 defm VFMADDSD4 : fma4s<0x6B, "vfmaddsd", FR64, f64mem, f64, X86Fmadd, loadf64>, 414 fma4s_int<0x6B, "vfmaddsd", sdmem, sse_load_f64, 415 int_x86_fma_vfmadd_sd>; 416 defm VFMSUBSD4 : fma4s<0x6F, "vfmsubsd", FR64, f64mem, f64, X86Fmsub, loadf64>, 417 fma4s_int<0x6F, "vfmsubsd", sdmem, sse_load_f64, 418 int_x86_fma_vfmsub_sd>; 419 defm VFNMADDSD4 : fma4s<0x7B, "vfnmaddsd", FR64, f64mem, f64, 420 X86Fnmadd, loadf64>, 421 fma4s_int<0x7B, "vfnmaddsd", sdmem, sse_load_f64, 422 int_x86_fma_vfnmadd_sd>; 423 defm VFNMSUBSD4 : fma4s<0x7F, "vfnmsubsd", FR64, f64mem, f64, 424 X86Fnmsub, loadf64>, 425 fma4s_int<0x7F, "vfnmsubsd", sdmem, sse_load_f64, 426 int_x86_fma_vfnmsub_sd>; 427 // Packed Instructions 428 defm VFMADDPD4 : fma4p<0x69, "vfmaddpd", X86Fmadd, v2f64, v4f64, 429 loadv2f64, loadv4f64>; 430 defm VFMSUBPD4 : fma4p<0x6D, "vfmsubpd", X86Fmsub, v2f64, v4f64, 431 loadv2f64, loadv4f64>; 432 defm VFNMADDPD4 : fma4p<0x79, "vfnmaddpd", X86Fnmadd, v2f64, v4f64, 433 loadv2f64, loadv4f64>; 434 defm VFNMSUBPD4 : fma4p<0x7D, "vfnmsubpd", X86Fnmsub, v2f64, v4f64, 435 loadv2f64, loadv4f64>; 436 defm VFMADDSUBPD4 : fma4p<0x5D, "vfmaddsubpd", X86Fmaddsub, v2f64, v4f64, 437 loadv2f64, loadv4f64>; 438 defm VFMSUBADDPD4 : fma4p<0x5F, "vfmsubaddpd", X86Fmsubadd, v2f64, v4f64, 439 loadv2f64, loadv4f64>; 440 } 441 442
