1 //===-- X86InstrFormats.td - X86 Instruction Formats -------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 //===----------------------------------------------------------------------===// 11 // X86 Instruction Format Definitions. 12 // 13 14 // Format specifies the encoding used by the instruction. This is part of the 15 // ad-hoc solution used to emit machine instruction encodings by our machine 16 // code emitter. 17 class Format<bits<7> val> { 18 bits<7> Value = val; 19 } 20 21 def Pseudo : Format<0>; def RawFrm : Format<1>; 22 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>; 23 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>; 24 def MRMSrcMem : Format<6>; def RawFrmMemOffs : Format<7>; 25 def RawFrmSrc : Format<8>; def RawFrmDst : Format<9>; 26 def RawFrmDstSrc: Format<10>; 27 def RawFrmImm8 : Format<11>; 28 def RawFrmImm16 : Format<12>; 29 def MRMXr : Format<14>; def MRMXm : Format<15>; 30 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>; 31 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>; 32 def MRM6r : Format<22>; def MRM7r : Format<23>; 33 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>; 34 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>; 35 def MRM6m : Format<30>; def MRM7m : Format<31>; 36 def MRM_C0 : Format<32>; def MRM_C1 : Format<33>; def MRM_C2 : Format<34>; 37 def MRM_C3 : Format<35>; def MRM_C4 : Format<36>; def MRM_C5 : Format<37>; 38 def MRM_C6 : Format<38>; def MRM_C7 : Format<39>; def MRM_C8 : Format<40>; 39 def MRM_C9 : Format<41>; def MRM_CA : Format<42>; def MRM_CB : Format<43>; 40 def MRM_CC : Format<44>; def MRM_CD : Format<45>; def MRM_CE : Format<46>; 41 def MRM_CF : Format<47>; def MRM_D0 : Format<48>; def MRM_D1 : Format<49>; 42 def MRM_D2 : Format<50>; def MRM_D3 : Format<51>; def MRM_D4 : Format<52>; 43 def MRM_D5 : Format<53>; def MRM_D6 : Format<54>; def MRM_D7 : Format<55>; 44 def MRM_D8 : Format<56>; def MRM_D9 : Format<57>; def MRM_DA : Format<58>; 45 def MRM_DB : Format<59>; def MRM_DC : Format<60>; def MRM_DD : Format<61>; 46 def MRM_DE : Format<62>; def MRM_DF : Format<63>; def MRM_E0 : Format<64>; 47 def MRM_E1 : Format<65>; def MRM_E2 : Format<66>; def MRM_E3 : Format<67>; 48 def MRM_E4 : Format<68>; def MRM_E5 : Format<69>; def MRM_E6 : Format<70>; 49 def MRM_E7 : Format<71>; def MRM_E8 : Format<72>; def MRM_E9 : Format<73>; 50 def MRM_EA : Format<74>; def MRM_EB : Format<75>; def MRM_EC : Format<76>; 51 def MRM_ED : Format<77>; def MRM_EE : Format<78>; def MRM_EF : Format<79>; 52 def MRM_F0 : Format<80>; def MRM_F1 : Format<81>; def MRM_F2 : Format<82>; 53 def MRM_F3 : Format<83>; def MRM_F4 : Format<84>; def MRM_F5 : Format<85>; 54 def MRM_F6 : Format<86>; def MRM_F7 : Format<87>; def MRM_F8 : Format<88>; 55 def MRM_F9 : Format<89>; def MRM_FA : Format<90>; def MRM_FB : Format<91>; 56 def MRM_FC : Format<92>; def MRM_FD : Format<93>; def MRM_FE : Format<94>; 57 def MRM_FF : Format<95>; 58 59 // ImmType - This specifies the immediate type used by an instruction. This is 60 // part of the ad-hoc solution used to emit machine instruction encodings by our 61 // machine code emitter. 62 class ImmType<bits<4> val> { 63 bits<4> Value = val; 64 } 65 def NoImm : ImmType<0>; 66 def Imm8 : ImmType<1>; 67 def Imm8PCRel : ImmType<2>; 68 def Imm16 : ImmType<3>; 69 def Imm16PCRel : ImmType<4>; 70 def Imm32 : ImmType<5>; 71 def Imm32PCRel : ImmType<6>; 72 def Imm32S : ImmType<7>; 73 def Imm64 : ImmType<8>; 74 75 // FPFormat - This specifies what form this FP instruction has. This is used by 76 // the Floating-Point stackifier pass. 77 class FPFormat<bits<3> val> { 78 bits<3> Value = val; 79 } 80 def NotFP : FPFormat<0>; 81 def ZeroArgFP : FPFormat<1>; 82 def OneArgFP : FPFormat<2>; 83 def OneArgFPRW : FPFormat<3>; 84 def TwoArgFP : FPFormat<4>; 85 def CompareFP : FPFormat<5>; 86 def CondMovFP : FPFormat<6>; 87 def SpecialFP : FPFormat<7>; 88 89 // Class specifying the SSE execution domain, used by the SSEDomainFix pass. 90 // Keep in sync with tables in X86InstrInfo.cpp. 91 class Domain<bits<2> val> { 92 bits<2> Value = val; 93 } 94 def GenericDomain : Domain<0>; 95 def SSEPackedSingle : Domain<1>; 96 def SSEPackedDouble : Domain<2>; 97 def SSEPackedInt : Domain<3>; 98 99 // Class specifying the vector form of the decompressed 100 // displacement of 8-bit. 101 class CD8VForm<bits<3> val> { 102 bits<3> Value = val; 103 } 104 def CD8VF : CD8VForm<0>; // v := VL 105 def CD8VH : CD8VForm<1>; // v := VL/2 106 def CD8VQ : CD8VForm<2>; // v := VL/4 107 def CD8VO : CD8VForm<3>; // v := VL/8 108 // The tuple (subvector) forms. 109 def CD8VT1 : CD8VForm<4>; // v := 1 110 def CD8VT2 : CD8VForm<5>; // v := 2 111 def CD8VT4 : CD8VForm<6>; // v := 4 112 def CD8VT8 : CD8VForm<7>; // v := 8 113 114 // Class specifying the prefix used an opcode extension. 115 class Prefix<bits<3> val> { 116 bits<3> Value = val; 117 } 118 def NoPrfx : Prefix<0>; 119 def PS : Prefix<1>; 120 def PD : Prefix<2>; 121 def XS : Prefix<3>; 122 def XD : Prefix<4>; 123 124 // Class specifying the opcode map. 125 class Map<bits<3> val> { 126 bits<3> Value = val; 127 } 128 def OB : Map<0>; 129 def TB : Map<1>; 130 def T8 : Map<2>; 131 def TA : Map<3>; 132 def XOP8 : Map<4>; 133 def XOP9 : Map<5>; 134 def XOPA : Map<6>; 135 136 // Class specifying the encoding 137 class Encoding<bits<2> val> { 138 bits<2> Value = val; 139 } 140 def EncNormal : Encoding<0>; 141 def EncVEX : Encoding<1>; 142 def EncXOP : Encoding<2>; 143 def EncEVEX : Encoding<3>; 144 145 // Operand size for encodings that change based on mode. 146 class OperandSize<bits<2> val> { 147 bits<2> Value = val; 148 } 149 def OpSizeFixed : OperandSize<0>; // Never needs a 0x66 prefix. 150 def OpSize16 : OperandSize<1>; // Needs 0x66 prefix in 32-bit mode. 151 def OpSize32 : OperandSize<2>; // Needs 0x66 prefix in 16-bit mode. 152 153 // Address size for encodings that change based on mode. 154 class AddressSize<bits<2> val> { 155 bits<2> Value = val; 156 } 157 def AdSizeX : AddressSize<0>; // Address size determined using addr operand. 158 def AdSize16 : AddressSize<1>; // Encodes a 16-bit address. 159 def AdSize32 : AddressSize<2>; // Encodes a 32-bit address. 160 def AdSize64 : AddressSize<3>; // Encodes a 64-bit address. 161 162 // Prefix byte classes which are used to indicate to the ad-hoc machine code 163 // emitter that various prefix bytes are required. 164 class OpSize16 { OperandSize OpSize = OpSize16; } 165 class OpSize32 { OperandSize OpSize = OpSize32; } 166 class AdSize16 { AddressSize AdSize = AdSize16; } 167 class AdSize32 { AddressSize AdSize = AdSize32; } 168 class AdSize64 { AddressSize AdSize = AdSize64; } 169 class REX_W { bit hasREX_WPrefix = 1; } 170 class LOCK { bit hasLockPrefix = 1; } 171 class REP { bit hasREPPrefix = 1; } 172 class TB { Map OpMap = TB; } 173 class T8 { Map OpMap = T8; } 174 class TA { Map OpMap = TA; } 175 class XOP8 { Map OpMap = XOP8; Prefix OpPrefix = PS; } 176 class XOP9 { Map OpMap = XOP9; Prefix OpPrefix = PS; } 177 class XOPA { Map OpMap = XOPA; Prefix OpPrefix = PS; } 178 class OBXS { Prefix OpPrefix = XS; } 179 class PS : TB { Prefix OpPrefix = PS; } 180 class PD : TB { Prefix OpPrefix = PD; } 181 class XD : TB { Prefix OpPrefix = XD; } 182 class XS : TB { Prefix OpPrefix = XS; } 183 class T8PS : T8 { Prefix OpPrefix = PS; } 184 class T8PD : T8 { Prefix OpPrefix = PD; } 185 class T8XD : T8 { Prefix OpPrefix = XD; } 186 class T8XS : T8 { Prefix OpPrefix = XS; } 187 class TAPS : TA { Prefix OpPrefix = PS; } 188 class TAPD : TA { Prefix OpPrefix = PD; } 189 class TAXD : TA { Prefix OpPrefix = XD; } 190 class VEX { Encoding OpEnc = EncVEX; } 191 class VEX_W { bit hasVEX_WPrefix = 1; } 192 class VEX_4V : VEX { bit hasVEX_4V = 1; } 193 class VEX_4VOp3 : VEX { bit hasVEX_4VOp3 = 1; } 194 class VEX_I8IMM { bit hasVEX_i8ImmReg = 1; } 195 class VEX_L { bit hasVEX_L = 1; } 196 class VEX_LIG { bit ignoresVEX_L = 1; } 197 class EVEX : VEX { Encoding OpEnc = EncEVEX; } 198 class EVEX_4V : VEX_4V { Encoding OpEnc = EncEVEX; } 199 class EVEX_K { bit hasEVEX_K = 1; } 200 class EVEX_KZ : EVEX_K { bit hasEVEX_Z = 1; } 201 class EVEX_B { bit hasEVEX_B = 1; } 202 class EVEX_RC { bit hasEVEX_RC = 1; } 203 class EVEX_V512 { bit hasEVEX_L2 = 1; bit hasVEX_L = 0; } 204 class EVEX_V256 { bit hasEVEX_L2 = 0; bit hasVEX_L = 1; } 205 class EVEX_V128 { bit hasEVEX_L2 = 0; bit hasVEX_L = 0; } 206 207 // Specify AVX512 8-bit compressed displacement encoding based on the vector 208 // element size in bits (8, 16, 32, 64) and the CDisp8 form. 209 class EVEX_CD8<int esize, CD8VForm form> { 210 int CD8_EltSize = !srl(esize, 3); 211 bits<3> CD8_Form = form.Value; 212 } 213 214 class Has3DNow0F0FOpcode { bit has3DNow0F0FOpcode = 1; } 215 class MemOp4 { bit hasMemOp4Prefix = 1; } 216 class XOP { Encoding OpEnc = EncXOP; } 217 class XOP_4V : XOP { bit hasVEX_4V = 1; } 218 class XOP_4VOp3 : XOP { bit hasVEX_4VOp3 = 1; } 219 220 class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins, 221 string AsmStr, 222 InstrItinClass itin, 223 Domain d = GenericDomain> 224 : Instruction { 225 let Namespace = "X86"; 226 227 bits<8> Opcode = opcod; 228 Format Form = f; 229 bits<7> FormBits = Form.Value; 230 ImmType ImmT = i; 231 232 dag OutOperandList = outs; 233 dag InOperandList = ins; 234 string AsmString = AsmStr; 235 236 // If this is a pseudo instruction, mark it isCodeGenOnly. 237 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo"); 238 239 let Itinerary = itin; 240 241 // 242 // Attributes specific to X86 instructions... 243 // 244 bit ForceDisassemble = 0; // Force instruction to disassemble even though it's 245 // isCodeGenonly. Needed to hide an ambiguous 246 // AsmString from the parser, but still disassemble. 247 248 OperandSize OpSize = OpSizeFixed; // Does this instruction's encoding change 249 // based on operand size of the mode? 250 bits<2> OpSizeBits = OpSize.Value; 251 AddressSize AdSize = AdSizeX; // Does this instruction's encoding change 252 // based on address size of the mode? 253 bits<2> AdSizeBits = AdSize.Value; 254 255 Prefix OpPrefix = NoPrfx; // Which prefix byte does this inst have? 256 bits<3> OpPrefixBits = OpPrefix.Value; 257 Map OpMap = OB; // Which opcode map does this inst have? 258 bits<3> OpMapBits = OpMap.Value; 259 bit hasREX_WPrefix = 0; // Does this inst require the REX.W prefix? 260 FPFormat FPForm = NotFP; // What flavor of FP instruction is this? 261 bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix? 262 Domain ExeDomain = d; 263 bit hasREPPrefix = 0; // Does this inst have a REP prefix? 264 Encoding OpEnc = EncNormal; // Encoding used by this instruction 265 bits<2> OpEncBits = OpEnc.Value; 266 bit hasVEX_WPrefix = 0; // Does this inst set the VEX_W field? 267 bit hasVEX_4V = 0; // Does this inst require the VEX.VVVV field? 268 bit hasVEX_4VOp3 = 0; // Does this inst require the VEX.VVVV field to 269 // encode the third operand? 270 bit hasVEX_i8ImmReg = 0; // Does this inst require the last source register 271 // to be encoded in a immediate field? 272 bit hasVEX_L = 0; // Does this inst use large (256-bit) registers? 273 bit ignoresVEX_L = 0; // Does this instruction ignore the L-bit 274 bit hasEVEX_K = 0; // Does this inst require masking? 275 bit hasEVEX_Z = 0; // Does this inst set the EVEX_Z field? 276 bit hasEVEX_L2 = 0; // Does this inst set the EVEX_L2 field? 277 bit hasEVEX_B = 0; // Does this inst set the EVEX_B field? 278 bits<3> CD8_Form = 0; // Compressed disp8 form - vector-width. 279 // Declare it int rather than bits<4> so that all bits are defined when 280 // assigning to bits<7>. 281 int CD8_EltSize = 0; // Compressed disp8 form - element-size in bytes. 282 bit has3DNow0F0FOpcode =0;// Wacky 3dNow! encoding? 283 bit hasMemOp4Prefix = 0; // Same bit as VEX_W, but used for swapping operands 284 bit hasEVEX_RC = 0; // Explicitly specified rounding control in FP instruction. 285 286 bits<2> EVEX_LL; 287 let EVEX_LL{0} = hasVEX_L; 288 let EVEX_LL{1} = hasEVEX_L2; 289 // Vector size in bytes. 290 bits<7> VectSize = !shl(16, EVEX_LL); 291 292 // The scaling factor for AVX512's compressed displacement is either 293 // - the size of a power-of-two number of elements or 294 // - the size of a single element for broadcasts or 295 // - the total vector size divided by a power-of-two number. 296 // Possible values are: 0 (non-AVX512 inst), 1, 2, 4, 8, 16, 32 and 64. 297 bits<7> CD8_Scale = !if (!eq (OpEnc.Value, EncEVEX.Value), 298 !if (CD8_Form{2}, 299 !shl(CD8_EltSize, CD8_Form{1-0}), 300 !if (hasEVEX_B, 301 CD8_EltSize, 302 !srl(VectSize, CD8_Form{1-0}))), 0); 303 304 // TSFlags layout should be kept in sync with X86BaseInfo.h. 305 let TSFlags{6-0} = FormBits; 306 let TSFlags{8-7} = OpSizeBits; 307 let TSFlags{10-9} = AdSizeBits; 308 let TSFlags{13-11} = OpPrefixBits; 309 let TSFlags{16-14} = OpMapBits; 310 let TSFlags{17} = hasREX_WPrefix; 311 let TSFlags{21-18} = ImmT.Value; 312 let TSFlags{24-22} = FPForm.Value; 313 let TSFlags{25} = hasLockPrefix; 314 let TSFlags{26} = hasREPPrefix; 315 let TSFlags{28-27} = ExeDomain.Value; 316 let TSFlags{30-29} = OpEncBits; 317 let TSFlags{38-31} = Opcode; 318 let TSFlags{39} = hasVEX_WPrefix; 319 let TSFlags{40} = hasVEX_4V; 320 let TSFlags{41} = hasVEX_4VOp3; 321 let TSFlags{42} = hasVEX_i8ImmReg; 322 let TSFlags{43} = hasVEX_L; 323 let TSFlags{44} = ignoresVEX_L; 324 let TSFlags{45} = hasEVEX_K; 325 let TSFlags{46} = hasEVEX_Z; 326 let TSFlags{47} = hasEVEX_L2; 327 let TSFlags{48} = hasEVEX_B; 328 // If we run out of TSFlags bits, it's possible to encode this in 3 bits. 329 let TSFlags{55-49} = CD8_Scale; 330 let TSFlags{56} = has3DNow0F0FOpcode; 331 let TSFlags{57} = hasMemOp4Prefix; 332 let TSFlags{58} = hasEVEX_RC; 333 } 334 335 class PseudoI<dag oops, dag iops, list<dag> pattern> 336 : X86Inst<0, Pseudo, NoImm, oops, iops, "", NoItinerary> { 337 let Pattern = pattern; 338 } 339 340 class I<bits<8> o, Format f, dag outs, dag ins, string asm, 341 list<dag> pattern, InstrItinClass itin = NoItinerary, 342 Domain d = GenericDomain> 343 : X86Inst<o, f, NoImm, outs, ins, asm, itin, d> { 344 let Pattern = pattern; 345 let CodeSize = 3; 346 } 347 class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm, 348 list<dag> pattern, InstrItinClass itin = NoItinerary, 349 Domain d = GenericDomain> 350 : X86Inst<o, f, Imm8, outs, ins, asm, itin, d> { 351 let Pattern = pattern; 352 let CodeSize = 3; 353 } 354 class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm, 355 list<dag> pattern, InstrItinClass itin = NoItinerary> 356 : X86Inst<o, f, Imm8PCRel, outs, ins, asm, itin> { 357 let Pattern = pattern; 358 let CodeSize = 3; 359 } 360 class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm, 361 list<dag> pattern, InstrItinClass itin = NoItinerary> 362 : X86Inst<o, f, Imm16, outs, ins, asm, itin> { 363 let Pattern = pattern; 364 let CodeSize = 3; 365 } 366 class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm, 367 list<dag> pattern, InstrItinClass itin = NoItinerary> 368 : X86Inst<o, f, Imm32, outs, ins, asm, itin> { 369 let Pattern = pattern; 370 let CodeSize = 3; 371 } 372 class Ii32S<bits<8> o, Format f, dag outs, dag ins, string asm, 373 list<dag> pattern, InstrItinClass itin = NoItinerary> 374 : X86Inst<o, f, Imm32S, outs, ins, asm, itin> { 375 let Pattern = pattern; 376 let CodeSize = 3; 377 } 378 379 class Ii16PCRel<bits<8> o, Format f, dag outs, dag ins, string asm, 380 list<dag> pattern, InstrItinClass itin = NoItinerary> 381 : X86Inst<o, f, Imm16PCRel, outs, ins, asm, itin> { 382 let Pattern = pattern; 383 let CodeSize = 3; 384 } 385 386 class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm, 387 list<dag> pattern, InstrItinClass itin = NoItinerary> 388 : X86Inst<o, f, Imm32PCRel, outs, ins, asm, itin> { 389 let Pattern = pattern; 390 let CodeSize = 3; 391 } 392 393 // FPStack Instruction Templates: 394 // FPI - Floating Point Instruction template. 395 class FPI<bits<8> o, Format F, dag outs, dag ins, string asm, 396 InstrItinClass itin = NoItinerary> 397 : I<o, F, outs, ins, asm, [], itin> {} 398 399 // FpI_ - Floating Point Pseudo Instruction template. Not Predicated. 400 class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern, 401 InstrItinClass itin = NoItinerary> 402 : X86Inst<0, Pseudo, NoImm, outs, ins, "", itin> { 403 let FPForm = fp; 404 let Pattern = pattern; 405 } 406 407 // Templates for instructions that use a 16- or 32-bit segmented address as 408 // their only operand: lcall (FAR CALL) and ljmp (FAR JMP) 409 // 410 // Iseg16 - 16-bit segment selector, 16-bit offset 411 // Iseg32 - 16-bit segment selector, 32-bit offset 412 413 class Iseg16 <bits<8> o, Format f, dag outs, dag ins, string asm, 414 list<dag> pattern, InstrItinClass itin = NoItinerary> 415 : X86Inst<o, f, Imm16, outs, ins, asm, itin> { 416 let Pattern = pattern; 417 let CodeSize = 3; 418 } 419 420 class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm, 421 list<dag> pattern, InstrItinClass itin = NoItinerary> 422 : X86Inst<o, f, Imm32, outs, ins, asm, itin> { 423 let Pattern = pattern; 424 let CodeSize = 3; 425 } 426 427 // SI - SSE 1 & 2 scalar instructions 428 class SI<bits<8> o, Format F, dag outs, dag ins, string asm, 429 list<dag> pattern, InstrItinClass itin = NoItinerary, 430 Domain d = GenericDomain> 431 : I<o, F, outs, ins, asm, pattern, itin, d> { 432 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], 433 !if(!eq(OpEnc.Value, EncVEX.Value), [UseAVX], 434 !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1], 435 !if(!eq(OpPrefix.Value, XD.Value), [UseSSE2], 436 !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2], 437 [UseSSE1]))))); 438 439 // AVX instructions have a 'v' prefix in the mnemonic 440 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm), 441 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm), 442 asm)); 443 } 444 445 // SI - SSE 1 & 2 scalar intrinsics - vex form available on AVX512 446 class SI_Int<bits<8> o, Format F, dag outs, dag ins, string asm, 447 list<dag> pattern, InstrItinClass itin = NoItinerary, 448 Domain d = GenericDomain> 449 : I<o, F, outs, ins, asm, pattern, itin, d> { 450 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], 451 !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX], 452 !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1], 453 !if(!eq(OpPrefix.Value, XD.Value), [UseSSE2], 454 !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2], 455 [UseSSE1]))))); 456 457 // AVX instructions have a 'v' prefix in the mnemonic 458 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm), 459 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm), 460 asm)); 461 } 462 // SIi8 - SSE 1 & 2 scalar instructions - vex form available on AVX512 463 class SIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 464 list<dag> pattern, InstrItinClass itin = NoItinerary> 465 : Ii8<o, F, outs, ins, asm, pattern, itin> { 466 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], 467 !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX], 468 !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1], 469 [UseSSE2]))); 470 471 // AVX instructions have a 'v' prefix in the mnemonic 472 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm), 473 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm), 474 asm)); 475 } 476 477 // PI - SSE 1 & 2 packed instructions 478 class PI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern, 479 InstrItinClass itin, Domain d> 480 : I<o, F, outs, ins, asm, pattern, itin, d> { 481 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], 482 !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX], 483 !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2], 484 [UseSSE1]))); 485 486 // AVX instructions have a 'v' prefix in the mnemonic 487 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm), 488 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm), 489 asm)); 490 } 491 492 // MMXPI - SSE 1 & 2 packed instructions with MMX operands 493 class MMXPI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern, 494 InstrItinClass itin, Domain d> 495 : I<o, F, outs, ins, asm, pattern, itin, d> { 496 let Predicates = !if(!eq(OpPrefix.Value, PD.Value), [HasSSE2], 497 [HasSSE1]); 498 } 499 500 // PIi8 - SSE 1 & 2 packed instructions with immediate 501 class PIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 502 list<dag> pattern, InstrItinClass itin, Domain d> 503 : Ii8<o, F, outs, ins, asm, pattern, itin, d> { 504 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], 505 !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX], 506 !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2], 507 [UseSSE1]))); 508 509 // AVX instructions have a 'v' prefix in the mnemonic 510 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm), 511 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm), 512 asm)); 513 } 514 515 // SSE1 Instruction Templates: 516 // 517 // SSI - SSE1 instructions with XS prefix. 518 // PSI - SSE1 instructions with PS prefix. 519 // PSIi8 - SSE1 instructions with ImmT == Imm8 and PS prefix. 520 // VSSI - SSE1 instructions with XS prefix in AVX form. 521 // VPSI - SSE1 instructions with PS prefix in AVX form, packed single. 522 523 class SSI<bits<8> o, Format F, dag outs, dag ins, string asm, 524 list<dag> pattern, InstrItinClass itin = NoItinerary> 525 : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>; 526 class SSIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 527 list<dag> pattern, InstrItinClass itin = NoItinerary> 528 : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>; 529 class PSI<bits<8> o, Format F, dag outs, dag ins, string asm, 530 list<dag> pattern, InstrItinClass itin = NoItinerary> 531 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, PS, 532 Requires<[UseSSE1]>; 533 class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 534 list<dag> pattern, InstrItinClass itin = NoItinerary> 535 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, PS, 536 Requires<[UseSSE1]>; 537 class VSSI<bits<8> o, Format F, dag outs, dag ins, string asm, 538 list<dag> pattern, InstrItinClass itin = NoItinerary> 539 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS, 540 Requires<[HasAVX]>; 541 class VPSI<bits<8> o, Format F, dag outs, dag ins, string asm, 542 list<dag> pattern, InstrItinClass itin = NoItinerary> 543 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedSingle>, PS, 544 Requires<[HasAVX]>; 545 546 // SSE2 Instruction Templates: 547 // 548 // SDI - SSE2 instructions with XD prefix. 549 // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix. 550 // S2SI - SSE2 instructions with XS prefix. 551 // SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix. 552 // PDI - SSE2 instructions with PD prefix, packed double domain. 553 // PDIi8 - SSE2 instructions with ImmT == Imm8 and PD prefix. 554 // VSDI - SSE2 scalar instructions with XD prefix in AVX form. 555 // VPDI - SSE2 vector instructions with PD prefix in AVX form, 556 // packed double domain. 557 // VS2I - SSE2 scalar instructions with PD prefix in AVX form. 558 // S2I - SSE2 scalar instructions with PD prefix. 559 // MMXSDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix as well as 560 // MMX operands. 561 // MMXSSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix as well as 562 // MMX operands. 563 564 class SDI<bits<8> o, Format F, dag outs, dag ins, string asm, 565 list<dag> pattern, InstrItinClass itin = NoItinerary> 566 : I<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>; 567 class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 568 list<dag> pattern, InstrItinClass itin = NoItinerary> 569 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>; 570 class S2SI<bits<8> o, Format F, dag outs, dag ins, string asm, 571 list<dag> pattern, InstrItinClass itin = NoItinerary> 572 : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE2]>; 573 class S2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 574 list<dag> pattern, InstrItinClass itin = NoItinerary> 575 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[UseSSE2]>; 576 class PDI<bits<8> o, Format F, dag outs, dag ins, string asm, 577 list<dag> pattern, InstrItinClass itin = NoItinerary> 578 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD, 579 Requires<[UseSSE2]>; 580 class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 581 list<dag> pattern, InstrItinClass itin = NoItinerary> 582 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD, 583 Requires<[UseSSE2]>; 584 class VSDI<bits<8> o, Format F, dag outs, dag ins, string asm, 585 list<dag> pattern, InstrItinClass itin = NoItinerary> 586 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XD, 587 Requires<[UseAVX]>; 588 class VS2SI<bits<8> o, Format F, dag outs, dag ins, string asm, 589 list<dag> pattern, InstrItinClass itin = NoItinerary> 590 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS, 591 Requires<[HasAVX]>; 592 class VPDI<bits<8> o, Format F, dag outs, dag ins, string asm, 593 list<dag> pattern, InstrItinClass itin = NoItinerary> 594 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedDouble>, 595 PD, Requires<[HasAVX]>; 596 class VS2I<bits<8> o, Format F, dag outs, dag ins, string asm, 597 list<dag> pattern, InstrItinClass itin = NoItinerary> 598 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, PD, 599 Requires<[UseAVX]>; 600 class S2I<bits<8> o, Format F, dag outs, dag ins, string asm, 601 list<dag> pattern, InstrItinClass itin = NoItinerary> 602 : I<o, F, outs, ins, asm, pattern, itin>, PD, Requires<[UseSSE2]>; 603 class MMXSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 604 list<dag> pattern, InstrItinClass itin = NoItinerary> 605 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasSSE2]>; 606 class MMXS2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 607 list<dag> pattern, InstrItinClass itin = NoItinerary> 608 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>; 609 610 // SSE3 Instruction Templates: 611 // 612 // S3I - SSE3 instructions with PD prefixes. 613 // S3SI - SSE3 instructions with XS prefix. 614 // S3DI - SSE3 instructions with XD prefix. 615 616 class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm, 617 list<dag> pattern, InstrItinClass itin = NoItinerary> 618 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, XS, 619 Requires<[UseSSE3]>; 620 class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm, 621 list<dag> pattern, InstrItinClass itin = NoItinerary> 622 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, XD, 623 Requires<[UseSSE3]>; 624 class S3I<bits<8> o, Format F, dag outs, dag ins, string asm, 625 list<dag> pattern, InstrItinClass itin = NoItinerary> 626 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD, 627 Requires<[UseSSE3]>; 628 629 630 // SSSE3 Instruction Templates: 631 // 632 // SS38I - SSSE3 instructions with T8 prefix. 633 // SS3AI - SSSE3 instructions with TA prefix. 634 // MMXSS38I - SSSE3 instructions with T8 prefix and MMX operands. 635 // MMXSS3AI - SSSE3 instructions with TA prefix and MMX operands. 636 // 637 // Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version 638 // uses the MMX registers. The 64-bit versions are grouped with the MMX 639 // classes. They need to be enabled even if AVX is enabled. 640 641 class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm, 642 list<dag> pattern, InstrItinClass itin = NoItinerary> 643 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD, 644 Requires<[UseSSSE3]>; 645 class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm, 646 list<dag> pattern, InstrItinClass itin = NoItinerary> 647 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD, 648 Requires<[UseSSSE3]>; 649 class MMXSS38I<bits<8> o, Format F, dag outs, dag ins, string asm, 650 list<dag> pattern, InstrItinClass itin = NoItinerary> 651 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PS, 652 Requires<[HasSSSE3]>; 653 class MMXSS3AI<bits<8> o, Format F, dag outs, dag ins, string asm, 654 list<dag> pattern, InstrItinClass itin = NoItinerary> 655 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPS, 656 Requires<[HasSSSE3]>; 657 658 // SSE4.1 Instruction Templates: 659 // 660 // SS48I - SSE 4.1 instructions with T8 prefix. 661 // SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8. 662 // 663 class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm, 664 list<dag> pattern, InstrItinClass itin = NoItinerary> 665 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD, 666 Requires<[UseSSE41]>; 667 class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 668 list<dag> pattern, InstrItinClass itin = NoItinerary> 669 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD, 670 Requires<[UseSSE41]>; 671 672 // SSE4.2 Instruction Templates: 673 // 674 // SS428I - SSE 4.2 instructions with T8 prefix. 675 class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm, 676 list<dag> pattern, InstrItinClass itin = NoItinerary> 677 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD, 678 Requires<[UseSSE42]>; 679 680 // SS42FI - SSE 4.2 instructions with T8XD prefix. 681 // NOTE: 'HasSSE42' is used as SS42FI is only used for CRC32 insns. 682 class SS42FI<bits<8> o, Format F, dag outs, dag ins, string asm, 683 list<dag> pattern, InstrItinClass itin = NoItinerary> 684 : I<o, F, outs, ins, asm, pattern, itin>, T8XD, Requires<[HasSSE42]>; 685 686 // SS42AI = SSE 4.2 instructions with TA prefix 687 class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm, 688 list<dag> pattern, InstrItinClass itin = NoItinerary> 689 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD, 690 Requires<[UseSSE42]>; 691 692 // AVX Instruction Templates: 693 // Instructions introduced in AVX (no SSE equivalent forms) 694 // 695 // AVX8I - AVX instructions with T8PD prefix. 696 // AVXAIi8 - AVX instructions with TAPD prefix and ImmT = Imm8. 697 class AVX8I<bits<8> o, Format F, dag outs, dag ins, string asm, 698 list<dag> pattern, InstrItinClass itin = NoItinerary> 699 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD, 700 Requires<[HasAVX]>; 701 class AVXAIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 702 list<dag> pattern, InstrItinClass itin = NoItinerary> 703 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD, 704 Requires<[HasAVX]>; 705 706 // AVX2 Instruction Templates: 707 // Instructions introduced in AVX2 (no SSE equivalent forms) 708 // 709 // AVX28I - AVX2 instructions with T8PD prefix. 710 // AVX2AIi8 - AVX2 instructions with TAPD prefix and ImmT = Imm8. 711 class AVX28I<bits<8> o, Format F, dag outs, dag ins, string asm, 712 list<dag> pattern, InstrItinClass itin = NoItinerary> 713 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD, 714 Requires<[HasAVX2]>; 715 class AVX2AIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 716 list<dag> pattern, InstrItinClass itin = NoItinerary> 717 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD, 718 Requires<[HasAVX2]>; 719 720 721 // AVX-512 Instruction Templates: 722 // Instructions introduced in AVX-512 (no SSE equivalent forms) 723 // 724 // AVX5128I - AVX-512 instructions with T8PD prefix. 725 // AVX512AIi8 - AVX-512 instructions with TAPD prefix and ImmT = Imm8. 726 // AVX512PDI - AVX-512 instructions with PD, double packed. 727 // AVX512PSI - AVX-512 instructions with PS, single packed. 728 // AVX512XS8I - AVX-512 instructions with T8 and XS prefixes. 729 // AVX512XSI - AVX-512 instructions with XS prefix, generic domain. 730 // AVX512BI - AVX-512 instructions with PD, int packed domain. 731 // AVX512SI - AVX-512 scalar instructions with PD prefix. 732 733 class AVX5128I<bits<8> o, Format F, dag outs, dag ins, string asm, 734 list<dag> pattern, InstrItinClass itin = NoItinerary> 735 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD, 736 Requires<[HasAVX512]>; 737 class AVX5128IBase : T8PD { 738 Domain ExeDomain = SSEPackedInt; 739 } 740 class AVX512XS8I<bits<8> o, Format F, dag outs, dag ins, string asm, 741 list<dag> pattern, InstrItinClass itin = NoItinerary> 742 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8XS, 743 Requires<[HasAVX512]>; 744 class AVX512XSI<bits<8> o, Format F, dag outs, dag ins, string asm, 745 list<dag> pattern, InstrItinClass itin = NoItinerary> 746 : I<o, F, outs, ins, asm, pattern, itin>, XS, 747 Requires<[HasAVX512]>; 748 class AVX512XDI<bits<8> o, Format F, dag outs, dag ins, string asm, 749 list<dag> pattern, InstrItinClass itin = NoItinerary> 750 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, XD, 751 Requires<[HasAVX512]>; 752 class AVX512BI<bits<8> o, Format F, dag outs, dag ins, string asm, 753 list<dag> pattern, InstrItinClass itin = NoItinerary> 754 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, PD, 755 Requires<[HasAVX512]>; 756 class AVX512BIBase : PD { 757 Domain ExeDomain = SSEPackedInt; 758 } 759 class AVX512BIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 760 list<dag> pattern, InstrItinClass itin = NoItinerary> 761 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, PD, 762 Requires<[HasAVX512]>; 763 class AVX512BIi8Base : PD { 764 Domain ExeDomain = SSEPackedInt; 765 ImmType ImmT = Imm8; 766 } 767 class AVX512XSIi8Base : XS { 768 Domain ExeDomain = SSEPackedInt; 769 ImmType ImmT = Imm8; 770 } 771 class AVX512XDIi8Base : XD { 772 Domain ExeDomain = SSEPackedInt; 773 ImmType ImmT = Imm8; 774 } 775 class AVX512PSIi8Base : PS { 776 Domain ExeDomain = SSEPackedSingle; 777 ImmType ImmT = Imm8; 778 } 779 class AVX512PDIi8Base : PD { 780 Domain ExeDomain = SSEPackedDouble; 781 ImmType ImmT = Imm8; 782 } 783 class AVX512AIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 784 list<dag> pattern, InstrItinClass itin = NoItinerary> 785 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD, 786 Requires<[HasAVX512]>; 787 class AVX512AIi8Base : TAPD { 788 Domain ExeDomain = SSEPackedInt; 789 ImmType ImmT = Imm8; 790 } 791 class AVX512Ii8<bits<8> o, Format F, dag outs, dag ins, string asm, 792 list<dag> pattern, InstrItinClass itin = NoItinerary> 793 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, 794 Requires<[HasAVX512]>; 795 class AVX512PDI<bits<8> o, Format F, dag outs, dag ins, string asm, 796 list<dag> pattern, InstrItinClass itin = NoItinerary> 797 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD, 798 Requires<[HasAVX512]>; 799 class AVX512PSI<bits<8> o, Format F, dag outs, dag ins, string asm, 800 list<dag> pattern, InstrItinClass itin = NoItinerary> 801 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, PS, 802 Requires<[HasAVX512]>; 803 class AVX512PIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 804 list<dag> pattern, Domain d, InstrItinClass itin = NoItinerary> 805 : Ii8<o, F, outs, ins, asm, pattern, itin, d>, Requires<[HasAVX512]>; 806 class AVX512PI<bits<8> o, Format F, dag outs, dag ins, string asm, 807 list<dag> pattern, Domain d, InstrItinClass itin = NoItinerary> 808 : I<o, F, outs, ins, asm, pattern, itin, d>, Requires<[HasAVX512]>; 809 class AVX512FMA3<bits<8> o, Format F, dag outs, dag ins, string asm, 810 list<dag>pattern, InstrItinClass itin = NoItinerary> 811 : I<o, F, outs, ins, asm, pattern, itin>, T8PD, 812 EVEX_4V, Requires<[HasAVX512]>; 813 class AVX512FMA3Base : T8PD, EVEX_4V; 814 815 class AVX512<bits<8> o, Format F, dag outs, dag ins, string asm, 816 list<dag>pattern, InstrItinClass itin = NoItinerary> 817 : I<o, F, outs, ins, asm, pattern, itin>, Requires<[HasAVX512]>; 818 819 // AES Instruction Templates: 820 // 821 // AES8I 822 // These use the same encoding as the SSE4.2 T8 and TA encodings. 823 class AES8I<bits<8> o, Format F, dag outs, dag ins, string asm, 824 list<dag>pattern, InstrItinClass itin = IIC_AES> 825 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD, 826 Requires<[HasAES]>; 827 828 class AESAI<bits<8> o, Format F, dag outs, dag ins, string asm, 829 list<dag> pattern, InstrItinClass itin = NoItinerary> 830 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD, 831 Requires<[HasAES]>; 832 833 // PCLMUL Instruction Templates 834 class PCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 835 list<dag>pattern, InstrItinClass itin = NoItinerary> 836 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD, 837 Requires<[HasPCLMUL]>; 838 839 class AVXPCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 840 list<dag>pattern, InstrItinClass itin = NoItinerary> 841 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD, 842 VEX_4V, Requires<[HasAVX, HasPCLMUL]>; 843 844 // FMA3 Instruction Templates 845 class FMA3<bits<8> o, Format F, dag outs, dag ins, string asm, 846 list<dag>pattern, InstrItinClass itin = NoItinerary> 847 : I<o, F, outs, ins, asm, pattern, itin>, T8PD, 848 VEX_4V, FMASC, Requires<[HasFMA]>; 849 850 // FMA4 Instruction Templates 851 class FMA4<bits<8> o, Format F, dag outs, dag ins, string asm, 852 list<dag>pattern, InstrItinClass itin = NoItinerary> 853 : Ii8<o, F, outs, ins, asm, pattern, itin>, TAPD, 854 VEX_4V, VEX_I8IMM, FMASC, Requires<[HasFMA4]>; 855 856 // XOP 2, 3 and 4 Operand Instruction Template 857 class IXOP<bits<8> o, Format F, dag outs, dag ins, string asm, 858 list<dag> pattern, InstrItinClass itin = NoItinerary> 859 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, 860 XOP9, Requires<[HasXOP]>; 861 862 // XOP 2, 3 and 4 Operand Instruction Templates with imm byte 863 class IXOPi8<bits<8> o, Format F, dag outs, dag ins, string asm, 864 list<dag> pattern, InstrItinClass itin = NoItinerary> 865 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, 866 XOP8, Requires<[HasXOP]>; 867 868 // XOP 5 operand instruction (VEX encoding!) 869 class IXOP5<bits<8> o, Format F, dag outs, dag ins, string asm, 870 list<dag>pattern, InstrItinClass itin = NoItinerary> 871 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD, 872 VEX_4V, VEX_I8IMM, Requires<[HasXOP]>; 873 874 // X86-64 Instruction templates... 875 // 876 877 class RI<bits<8> o, Format F, dag outs, dag ins, string asm, 878 list<dag> pattern, InstrItinClass itin = NoItinerary> 879 : I<o, F, outs, ins, asm, pattern, itin>, REX_W; 880 class RIi8 <bits<8> o, Format F, dag outs, dag ins, string asm, 881 list<dag> pattern, InstrItinClass itin = NoItinerary> 882 : Ii8<o, F, outs, ins, asm, pattern, itin>, REX_W; 883 class RIi16 <bits<8> o, Format F, dag outs, dag ins, string asm, 884 list<dag> pattern, InstrItinClass itin = NoItinerary> 885 : Ii16<o, F, outs, ins, asm, pattern, itin>, REX_W; 886 class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm, 887 list<dag> pattern, InstrItinClass itin = NoItinerary> 888 : Ii32<o, F, outs, ins, asm, pattern, itin>, REX_W; 889 class RIi32S <bits<8> o, Format F, dag outs, dag ins, string asm, 890 list<dag> pattern, InstrItinClass itin = NoItinerary> 891 : Ii32S<o, F, outs, ins, asm, pattern, itin>, REX_W; 892 893 class RIi64<bits<8> o, Format f, dag outs, dag ins, string asm, 894 list<dag> pattern, InstrItinClass itin = NoItinerary> 895 : X86Inst<o, f, Imm64, outs, ins, asm, itin>, REX_W { 896 let Pattern = pattern; 897 let CodeSize = 3; 898 } 899 900 class RIi64_NOREX<bits<8> o, Format f, dag outs, dag ins, string asm, 901 list<dag> pattern, InstrItinClass itin = NoItinerary> 902 : X86Inst<o, f, Imm64, outs, ins, asm, itin> { 903 let Pattern = pattern; 904 let CodeSize = 3; 905 } 906 907 class RS2I<bits<8> o, Format F, dag outs, dag ins, string asm, 908 list<dag> pattern, InstrItinClass itin = NoItinerary> 909 : S2I<o, F, outs, ins, asm, pattern, itin>, REX_W; 910 class VRS2I<bits<8> o, Format F, dag outs, dag ins, string asm, 911 list<dag> pattern, InstrItinClass itin = NoItinerary> 912 : VS2I<o, F, outs, ins, asm, pattern, itin>, VEX_W; 913 914 // MMX Instruction templates 915 // 916 917 // MMXI - MMX instructions with TB prefix. 918 // MMXI32 - MMX instructions with TB prefix valid only in 32 bit mode. 919 // MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode. 920 // MMX2I - MMX / SSE2 instructions with PD prefix. 921 // MMXIi8 - MMX instructions with ImmT == Imm8 and PS prefix. 922 // MMXIi8 - MMX instructions with ImmT == Imm8 and PS prefix. 923 // MMXID - MMX instructions with XD prefix. 924 // MMXIS - MMX instructions with XS prefix. 925 class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm, 926 list<dag> pattern, InstrItinClass itin = NoItinerary> 927 : I<o, F, outs, ins, asm, pattern, itin>, PS, Requires<[HasMMX]>; 928 class MMXI32<bits<8> o, Format F, dag outs, dag ins, string asm, 929 list<dag> pattern, InstrItinClass itin = NoItinerary> 930 : I<o, F, outs, ins, asm, pattern, itin>, PS, Requires<[HasMMX,Not64BitMode]>; 931 class MMXI64<bits<8> o, Format F, dag outs, dag ins, string asm, 932 list<dag> pattern, InstrItinClass itin = NoItinerary> 933 : I<o, F, outs, ins, asm, pattern, itin>, PS, Requires<[HasMMX,In64BitMode]>; 934 class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm, 935 list<dag> pattern, InstrItinClass itin = NoItinerary> 936 : I<o, F, outs, ins, asm, pattern, itin>, PS, REX_W, Requires<[HasMMX]>; 937 class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm, 938 list<dag> pattern, InstrItinClass itin = NoItinerary> 939 : I<o, F, outs, ins, asm, pattern, itin>, PD, Requires<[HasMMX]>; 940 class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 941 list<dag> pattern, InstrItinClass itin = NoItinerary> 942 : Ii8<o, F, outs, ins, asm, pattern, itin>, PS, Requires<[HasMMX]>; 943 class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm, 944 list<dag> pattern, InstrItinClass itin = NoItinerary> 945 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasMMX]>; 946 class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm, 947 list<dag> pattern, InstrItinClass itin = NoItinerary> 948 : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[HasMMX]>; 949
