1 //===-- X86InstrMMX.td - Describe the MMX Instruction Set --*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the X86 MMX instruction set, defining the instructions, 11 // and properties of the instructions which are needed for code generation, 12 // machine code emission, and analysis. 13 // 14 // All instructions that use MMX should be in this file, even if they also use 15 // SSE. 16 // 17 //===----------------------------------------------------------------------===// 18 19 //===----------------------------------------------------------------------===// 20 // MMX Multiclasses 21 //===----------------------------------------------------------------------===// 22 23 let Sched = WriteVecALU in { 24 def MMX_INTALU_ITINS : OpndItins< 25 IIC_MMX_ALU_RR, IIC_MMX_ALU_RM 26 >; 27 28 def MMX_INTALUQ_ITINS : OpndItins< 29 IIC_MMX_ALUQ_RR, IIC_MMX_ALUQ_RM 30 >; 31 32 def MMX_PHADDSUBW : OpndItins< 33 IIC_MMX_PHADDSUBW_RR, IIC_MMX_PHADDSUBW_RM 34 >; 35 36 def MMX_PHADDSUBD : OpndItins< 37 IIC_MMX_PHADDSUBD_RR, IIC_MMX_PHADDSUBD_RM 38 >; 39 } 40 41 let Sched = WriteVecLogic in 42 def MMX_INTALU_ITINS_VECLOGICSCHED : OpndItins< 43 IIC_MMX_ALU_RR, IIC_MMX_ALU_RM 44 >; 45 46 let Sched = WriteVecIMul in 47 def MMX_PMUL_ITINS : OpndItins< 48 IIC_MMX_PMUL, IIC_MMX_PMUL 49 >; 50 51 let Sched = WriteVecIMul in { 52 def MMX_PSADBW_ITINS : OpndItins< 53 IIC_MMX_PSADBW, IIC_MMX_PSADBW 54 >; 55 56 def MMX_MISC_FUNC_ITINS : OpndItins< 57 IIC_MMX_MISC_FUNC_MEM, IIC_MMX_MISC_FUNC_REG 58 >; 59 } 60 61 def MMX_SHIFT_ITINS : ShiftOpndItins< 62 IIC_MMX_SHIFT_RR, IIC_MMX_SHIFT_RM, IIC_MMX_SHIFT_RI 63 >; 64 65 let Sched = WriteShuffle in { 66 def MMX_UNPCK_H_ITINS : OpndItins< 67 IIC_MMX_UNPCK_H_RR, IIC_MMX_UNPCK_H_RM 68 >; 69 70 def MMX_UNPCK_L_ITINS : OpndItins< 71 IIC_MMX_UNPCK_L, IIC_MMX_UNPCK_L 72 >; 73 74 def MMX_PCK_ITINS : OpndItins< 75 IIC_MMX_PCK_RR, IIC_MMX_PCK_RM 76 >; 77 78 def MMX_PSHUF_ITINS : OpndItins< 79 IIC_MMX_PSHUF, IIC_MMX_PSHUF 80 >; 81 } // Sched 82 83 let Sched = WriteCvtF2I in { 84 def MMX_CVT_PD_ITINS : OpndItins< 85 IIC_MMX_CVT_PD_RR, IIC_MMX_CVT_PD_RM 86 >; 87 88 def MMX_CVT_PS_ITINS : OpndItins< 89 IIC_MMX_CVT_PS_RR, IIC_MMX_CVT_PS_RM 90 >; 91 } 92 93 let Constraints = "$src1 = $dst" in { 94 // MMXI_binop_rm_int - Simple MMX binary operator based on intrinsic. 95 // When this is cleaned up, remove the FIXME from X86RecognizableInstr.cpp. 96 multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId, 97 OpndItins itins, bit Commutable = 0> { 98 def irr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), 99 (ins VR64:$src1, VR64:$src2), 100 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), 101 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))], itins.rr>, 102 Sched<[itins.Sched]> { 103 let isCommutable = Commutable; 104 } 105 def irm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), 106 (ins VR64:$src1, i64mem:$src2), 107 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), 108 [(set VR64:$dst, (IntId VR64:$src1, 109 (bitconvert (load_mmx addr:$src2))))], 110 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>; 111 } 112 113 multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm, 114 string OpcodeStr, Intrinsic IntId, 115 Intrinsic IntId2, ShiftOpndItins itins> { 116 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), 117 (ins VR64:$src1, VR64:$src2), 118 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), 119 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))], itins.rr>, 120 Sched<[WriteVecShift]>; 121 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), 122 (ins VR64:$src1, i64mem:$src2), 123 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), 124 [(set VR64:$dst, (IntId VR64:$src1, 125 (bitconvert (load_mmx addr:$src2))))], 126 itins.rm>, Sched<[WriteVecShiftLd, ReadAfterLd]>; 127 def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst), 128 (ins VR64:$src1, i32u8imm:$src2), 129 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), 130 [(set VR64:$dst, (IntId2 VR64:$src1, imm:$src2))], itins.ri>, 131 Sched<[WriteVecShift]>; 132 } 133 } 134 135 /// Unary MMX instructions requiring SSSE3. 136 multiclass SS3I_unop_rm_int_mm<bits<8> opc, string OpcodeStr, 137 Intrinsic IntId64, OpndItins itins> { 138 def rr64 : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src), 139 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), 140 [(set VR64:$dst, (IntId64 VR64:$src))], itins.rr>, 141 Sched<[itins.Sched]>; 142 143 def rm64 : MMXSS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src), 144 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), 145 [(set VR64:$dst, 146 (IntId64 (bitconvert (memopmmx addr:$src))))], 147 itins.rm>, Sched<[itins.Sched.Folded]>; 148 } 149 150 /// Binary MMX instructions requiring SSSE3. 151 let ImmT = NoImm, Constraints = "$src1 = $dst" in { 152 multiclass SS3I_binop_rm_int_mm<bits<8> opc, string OpcodeStr, 153 Intrinsic IntId64, OpndItins itins> { 154 let isCommutable = 0 in 155 def rr64 : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst), 156 (ins VR64:$src1, VR64:$src2), 157 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), 158 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))], itins.rr>, 159 Sched<[itins.Sched]>; 160 def rm64 : MMXSS38I<opc, MRMSrcMem, (outs VR64:$dst), 161 (ins VR64:$src1, i64mem:$src2), 162 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), 163 [(set VR64:$dst, 164 (IntId64 VR64:$src1, 165 (bitconvert (memopmmx addr:$src2))))], itins.rm>, 166 Sched<[itins.Sched.Folded, ReadAfterLd]>; 167 } 168 } 169 170 /// PALIGN MMX instructions (require SSSE3). 171 multiclass ssse3_palign_mm<string asm, Intrinsic IntId> { 172 def R64irr : MMXSS3AI<0x0F, MRMSrcReg, (outs VR64:$dst), 173 (ins VR64:$src1, VR64:$src2, u8imm:$src3), 174 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), 175 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2, (i8 imm:$src3)))]>, 176 Sched<[WriteShuffle]>; 177 def R64irm : MMXSS3AI<0x0F, MRMSrcMem, (outs VR64:$dst), 178 (ins VR64:$src1, i64mem:$src2, u8imm:$src3), 179 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), 180 [(set VR64:$dst, (IntId VR64:$src1, 181 (bitconvert (load_mmx addr:$src2)), (i8 imm:$src3)))]>, 182 Sched<[WriteShuffleLd, ReadAfterLd]>; 183 } 184 185 multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC, 186 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag, 187 string asm, OpndItins itins, Domain d> { 188 def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm, 189 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr, d>, 190 Sched<[itins.Sched]>; 191 def irm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm, 192 [(set DstRC:$dst, (Int (ld_frag addr:$src)))], itins.rm, d>, 193 Sched<[itins.Sched.Folded]>; 194 } 195 196 multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC, 197 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop, 198 PatFrag ld_frag, string asm, Domain d> { 199 def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), 200 (ins DstRC:$src1, SrcRC:$src2), asm, 201 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))], 202 NoItinerary, d>, Sched<[WriteCvtI2F]>; 203 def irm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst), 204 (ins DstRC:$src1, x86memop:$src2), asm, 205 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))], 206 NoItinerary, d>, Sched<[WriteCvtI2FLd]>; 207 } 208 209 //===----------------------------------------------------------------------===// 210 // MMX EMMS Instruction 211 //===----------------------------------------------------------------------===// 212 213 def MMX_EMMS : MMXI<0x77, RawFrm, (outs), (ins), "emms", 214 [(int_x86_mmx_emms)], IIC_MMX_EMMS>; 215 216 //===----------------------------------------------------------------------===// 217 // MMX Scalar Instructions 218 //===----------------------------------------------------------------------===// 219 220 // Data Transfer Instructions 221 def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src), 222 "movd\t{$src, $dst|$dst, $src}", 223 [(set VR64:$dst, 224 (x86mmx (scalar_to_vector GR32:$src)))], 225 IIC_MMX_MOV_MM_RM>, Sched<[WriteMove]>; 226 def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src), 227 "movd\t{$src, $dst|$dst, $src}", 228 [(set VR64:$dst, 229 (x86mmx (scalar_to_vector (loadi32 addr:$src))))], 230 IIC_MMX_MOV_MM_RM>, Sched<[WriteLoad]>; 231 232 let Predicates = [HasMMX] in { 233 let AddedComplexity = 15 in 234 def : Pat<(x86mmx (MMX_X86movw2d GR32:$src)), 235 (MMX_MOVD64rr GR32:$src)>; 236 let AddedComplexity = 20 in 237 def : Pat<(x86mmx (MMX_X86movw2d (loadi32 addr:$src))), 238 (MMX_MOVD64rm addr:$src)>; 239 } 240 241 let mayStore = 1 in 242 def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src), 243 "movd\t{$src, $dst|$dst, $src}", [], IIC_MMX_MOV_MM_RM>, 244 Sched<[WriteStore]>; 245 246 def MMX_MOVD64grr : MMXI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR64:$src), 247 "movd\t{$src, $dst|$dst, $src}", 248 [(set GR32:$dst, 249 (MMX_X86movd2w (x86mmx VR64:$src)))], 250 IIC_MMX_MOV_REG_MM>, Sched<[WriteMove]>; 251 252 let isBitcast = 1 in 253 def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src), 254 "movd\t{$src, $dst|$dst, $src}", 255 [(set VR64:$dst, (bitconvert GR64:$src))], 256 IIC_MMX_MOV_MM_RM>, Sched<[WriteMove]>; 257 258 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in 259 def MMX_MOVD64to64rm : MMXRI<0x6E, MRMSrcMem, (outs VR64:$dst), 260 (ins i64mem:$src), "movd\t{$src, $dst|$dst, $src}", 261 [], IIC_MMX_MOVQ_RM>, Sched<[WriteLoad]>; 262 263 // These are 64 bit moves, but since the OS X assembler doesn't 264 // recognize a register-register movq, we write them as 265 // movd. 266 let SchedRW = [WriteMove], isBitcast = 1 in { 267 def MMX_MOVD64from64rr : MMXRI<0x7E, MRMDestReg, 268 (outs GR64:$dst), (ins VR64:$src), 269 "movd\t{$src, $dst|$dst, $src}", 270 [(set GR64:$dst, 271 (bitconvert VR64:$src))], IIC_MMX_MOV_REG_MM>; 272 let hasSideEffects = 0 in 273 def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src), 274 "movq\t{$src, $dst|$dst, $src}", [], 275 IIC_MMX_MOVQ_RR>; 276 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in { 277 def MMX_MOVQ64rr_REV : MMXI<0x7F, MRMDestReg, (outs VR64:$dst), (ins VR64:$src), 278 "movq\t{$src, $dst|$dst, $src}", [], 279 IIC_MMX_MOVQ_RR>; 280 } 281 } // SchedRW 282 283 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in 284 def MMX_MOVD64from64rm : MMXRI<0x7E, MRMDestMem, 285 (outs i64mem:$dst), (ins VR64:$src), 286 "movd\t{$src, $dst|$dst, $src}", 287 [], IIC_MMX_MOV_REG_MM>, Sched<[WriteStore]>; 288 289 let SchedRW = [WriteLoad] in { 290 let canFoldAsLoad = 1 in 291 def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src), 292 "movq\t{$src, $dst|$dst, $src}", 293 [(set VR64:$dst, (load_mmx addr:$src))], 294 IIC_MMX_MOVQ_RM>; 295 } // SchedRW 296 let SchedRW = [WriteStore] in 297 def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src), 298 "movq\t{$src, $dst|$dst, $src}", 299 [(store (x86mmx VR64:$src), addr:$dst)], 300 IIC_MMX_MOVQ_RM>; 301 302 let SchedRW = [WriteMove] in { 303 def MMX_MOVDQ2Qrr : MMXSDIi8<0xD6, MRMSrcReg, (outs VR64:$dst), 304 (ins VR128:$src), "movdq2q\t{$src, $dst|$dst, $src}", 305 [(set VR64:$dst, 306 (x86mmx (bitconvert 307 (i64 (extractelt (v2i64 VR128:$src), 308 (iPTR 0))))))], 309 IIC_MMX_MOVQ_RR>; 310 311 def MMX_MOVQ2DQrr : MMXS2SIi8<0xD6, MRMSrcReg, (outs VR128:$dst), 312 (ins VR64:$src), "movq2dq\t{$src, $dst|$dst, $src}", 313 [(set VR128:$dst, 314 (v2i64 315 (scalar_to_vector 316 (i64 (bitconvert (x86mmx VR64:$src))))))], 317 IIC_MMX_MOVQ_RR>; 318 319 let isCodeGenOnly = 1, hasSideEffects = 1 in { 320 def MMX_MOVQ2FR64rr: MMXS2SIi8<0xD6, MRMSrcReg, (outs FR64:$dst), 321 (ins VR64:$src), "movq2dq\t{$src, $dst|$dst, $src}", 322 [], IIC_MMX_MOVQ_RR>; 323 324 def MMX_MOVFR642Qrr: MMXSDIi8<0xD6, MRMSrcReg, (outs VR64:$dst), 325 (ins FR64:$src), "movdq2q\t{$src, $dst|$dst, $src}", 326 [], IIC_MMX_MOVQ_RR>; 327 } 328 } // SchedRW 329 330 let Predicates = [HasSSE1] in 331 def MMX_MOVNTQmr : MMXI<0xE7, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src), 332 "movntq\t{$src, $dst|$dst, $src}", 333 [(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)], 334 IIC_MMX_MOVQ_RM>, Sched<[WriteStore]>; 335 336 let Predicates = [HasMMX] in { 337 let AddedComplexity = 15 in 338 // movd to MMX register zero-extends 339 def : Pat<(x86mmx (X86vzmovl (x86mmx (scalar_to_vector GR32:$src)))), 340 (MMX_MOVD64rr GR32:$src)>; 341 let AddedComplexity = 20 in 342 def : Pat<(x86mmx (X86vzmovl (x86mmx (scalar_to_vector (loadi32 addr:$src))))), 343 (MMX_MOVD64rm addr:$src)>; 344 } 345 346 // Arithmetic Instructions 347 defm MMX_PABSB : SS3I_unop_rm_int_mm<0x1C, "pabsb", int_x86_ssse3_pabs_b, 348 MMX_INTALU_ITINS>; 349 defm MMX_PABSW : SS3I_unop_rm_int_mm<0x1D, "pabsw", int_x86_ssse3_pabs_w, 350 MMX_INTALU_ITINS>; 351 defm MMX_PABSD : SS3I_unop_rm_int_mm<0x1E, "pabsd", int_x86_ssse3_pabs_d, 352 MMX_INTALU_ITINS>; 353 // -- Addition 354 defm MMX_PADDB : MMXI_binop_rm_int<0xFC, "paddb", int_x86_mmx_padd_b, 355 MMX_INTALU_ITINS, 1>; 356 defm MMX_PADDW : MMXI_binop_rm_int<0xFD, "paddw", int_x86_mmx_padd_w, 357 MMX_INTALU_ITINS, 1>; 358 defm MMX_PADDD : MMXI_binop_rm_int<0xFE, "paddd", int_x86_mmx_padd_d, 359 MMX_INTALU_ITINS, 1>; 360 let Predicates = [HasSSE2] in 361 defm MMX_PADDQ : MMXI_binop_rm_int<0xD4, "paddq", int_x86_mmx_padd_q, 362 MMX_INTALUQ_ITINS, 1>; 363 defm MMX_PADDSB : MMXI_binop_rm_int<0xEC, "paddsb" , int_x86_mmx_padds_b, 364 MMX_INTALU_ITINS, 1>; 365 defm MMX_PADDSW : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w, 366 MMX_INTALU_ITINS, 1>; 367 368 defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b, 369 MMX_INTALU_ITINS, 1>; 370 defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w, 371 MMX_INTALU_ITINS, 1>; 372 373 defm MMX_PHADDW : SS3I_binop_rm_int_mm<0x01, "phaddw", int_x86_ssse3_phadd_w, 374 MMX_PHADDSUBW>; 375 defm MMX_PHADD : SS3I_binop_rm_int_mm<0x02, "phaddd", int_x86_ssse3_phadd_d, 376 MMX_PHADDSUBD>; 377 defm MMX_PHADDSW : SS3I_binop_rm_int_mm<0x03, "phaddsw",int_x86_ssse3_phadd_sw, 378 MMX_PHADDSUBW>; 379 380 381 // -- Subtraction 382 defm MMX_PSUBB : MMXI_binop_rm_int<0xF8, "psubb", int_x86_mmx_psub_b, 383 MMX_INTALU_ITINS>; 384 defm MMX_PSUBW : MMXI_binop_rm_int<0xF9, "psubw", int_x86_mmx_psub_w, 385 MMX_INTALU_ITINS>; 386 defm MMX_PSUBD : MMXI_binop_rm_int<0xFA, "psubd", int_x86_mmx_psub_d, 387 MMX_INTALU_ITINS>; 388 let Predicates = [HasSSE2] in 389 defm MMX_PSUBQ : MMXI_binop_rm_int<0xFB, "psubq", int_x86_mmx_psub_q, 390 MMX_INTALUQ_ITINS>; 391 392 defm MMX_PSUBSB : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b, 393 MMX_INTALU_ITINS>; 394 defm MMX_PSUBSW : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w, 395 MMX_INTALU_ITINS>; 396 397 defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b, 398 MMX_INTALU_ITINS>; 399 defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w, 400 MMX_INTALU_ITINS>; 401 402 defm MMX_PHSUBW : SS3I_binop_rm_int_mm<0x05, "phsubw", int_x86_ssse3_phsub_w, 403 MMX_PHADDSUBW>; 404 defm MMX_PHSUBD : SS3I_binop_rm_int_mm<0x06, "phsubd", int_x86_ssse3_phsub_d, 405 MMX_PHADDSUBD>; 406 defm MMX_PHSUBSW : SS3I_binop_rm_int_mm<0x07, "phsubsw",int_x86_ssse3_phsub_sw, 407 MMX_PHADDSUBW>; 408 409 // -- Multiplication 410 defm MMX_PMULLW : MMXI_binop_rm_int<0xD5, "pmullw", int_x86_mmx_pmull_w, 411 MMX_PMUL_ITINS, 1>; 412 413 defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw", int_x86_mmx_pmulh_w, 414 MMX_PMUL_ITINS, 1>; 415 let Predicates = [HasSSE1] in 416 defm MMX_PMULHUW : MMXI_binop_rm_int<0xE4, "pmulhuw", int_x86_mmx_pmulhu_w, 417 MMX_PMUL_ITINS, 1>; 418 let Predicates = [HasSSE2] in 419 defm MMX_PMULUDQ : MMXI_binop_rm_int<0xF4, "pmuludq", int_x86_mmx_pmulu_dq, 420 MMX_PMUL_ITINS, 1>; 421 let isCommutable = 1 in 422 defm MMX_PMULHRSW : SS3I_binop_rm_int_mm<0x0B, "pmulhrsw", 423 int_x86_ssse3_pmul_hr_sw, MMX_PMUL_ITINS>; 424 425 // -- Miscellanea 426 defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd, 427 MMX_PMUL_ITINS, 1>; 428 429 defm MMX_PMADDUBSW : SS3I_binop_rm_int_mm<0x04, "pmaddubsw", 430 int_x86_ssse3_pmadd_ub_sw, MMX_PMUL_ITINS>; 431 let Predicates = [HasSSE1] in { 432 defm MMX_PAVGB : MMXI_binop_rm_int<0xE0, "pavgb", int_x86_mmx_pavg_b, 433 MMX_MISC_FUNC_ITINS, 1>; 434 defm MMX_PAVGW : MMXI_binop_rm_int<0xE3, "pavgw", int_x86_mmx_pavg_w, 435 MMX_MISC_FUNC_ITINS, 1>; 436 437 defm MMX_PMINUB : MMXI_binop_rm_int<0xDA, "pminub", int_x86_mmx_pminu_b, 438 MMX_MISC_FUNC_ITINS, 1>; 439 defm MMX_PMINSW : MMXI_binop_rm_int<0xEA, "pminsw", int_x86_mmx_pmins_w, 440 MMX_MISC_FUNC_ITINS, 1>; 441 442 defm MMX_PMAXUB : MMXI_binop_rm_int<0xDE, "pmaxub", int_x86_mmx_pmaxu_b, 443 MMX_MISC_FUNC_ITINS, 1>; 444 defm MMX_PMAXSW : MMXI_binop_rm_int<0xEE, "pmaxsw", int_x86_mmx_pmaxs_w, 445 MMX_MISC_FUNC_ITINS, 1>; 446 447 defm MMX_PSADBW : MMXI_binop_rm_int<0xF6, "psadbw", int_x86_mmx_psad_bw, 448 MMX_PSADBW_ITINS, 1>; 449 } 450 451 defm MMX_PSIGNB : SS3I_binop_rm_int_mm<0x08, "psignb", int_x86_ssse3_psign_b, 452 MMX_MISC_FUNC_ITINS>; 453 defm MMX_PSIGNW : SS3I_binop_rm_int_mm<0x09, "psignw", int_x86_ssse3_psign_w, 454 MMX_MISC_FUNC_ITINS>; 455 defm MMX_PSIGND : SS3I_binop_rm_int_mm<0x0A, "psignd", int_x86_ssse3_psign_d, 456 MMX_MISC_FUNC_ITINS>; 457 let Constraints = "$src1 = $dst" in 458 defm MMX_PALIGN : ssse3_palign_mm<"palignr", int_x86_mmx_palignr_b>; 459 460 // Logical Instructions 461 defm MMX_PAND : MMXI_binop_rm_int<0xDB, "pand", int_x86_mmx_pand, 462 MMX_INTALU_ITINS_VECLOGICSCHED, 1>; 463 defm MMX_POR : MMXI_binop_rm_int<0xEB, "por" , int_x86_mmx_por, 464 MMX_INTALU_ITINS_VECLOGICSCHED, 1>; 465 defm MMX_PXOR : MMXI_binop_rm_int<0xEF, "pxor", int_x86_mmx_pxor, 466 MMX_INTALU_ITINS_VECLOGICSCHED, 1>; 467 defm MMX_PANDN : MMXI_binop_rm_int<0xDF, "pandn", int_x86_mmx_pandn, 468 MMX_INTALU_ITINS_VECLOGICSCHED>; 469 470 // Shift Instructions 471 defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw", 472 int_x86_mmx_psrl_w, int_x86_mmx_psrli_w, 473 MMX_SHIFT_ITINS>; 474 defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld", 475 int_x86_mmx_psrl_d, int_x86_mmx_psrli_d, 476 MMX_SHIFT_ITINS>; 477 defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq", 478 int_x86_mmx_psrl_q, int_x86_mmx_psrli_q, 479 MMX_SHIFT_ITINS>; 480 481 def : Pat<(int_x86_mmx_psrl_w VR64:$src1, (load_mvmmx addr:$src2)), 482 (MMX_PSRLWrm VR64:$src1, addr:$src2)>; 483 def : Pat<(int_x86_mmx_psrl_d VR64:$src1, (load_mvmmx addr:$src2)), 484 (MMX_PSRLDrm VR64:$src1, addr:$src2)>; 485 def : Pat<(int_x86_mmx_psrl_q VR64:$src1, (load_mvmmx addr:$src2)), 486 (MMX_PSRLQrm VR64:$src1, addr:$src2)>; 487 488 defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw", 489 int_x86_mmx_psll_w, int_x86_mmx_pslli_w, 490 MMX_SHIFT_ITINS>; 491 defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld", 492 int_x86_mmx_psll_d, int_x86_mmx_pslli_d, 493 MMX_SHIFT_ITINS>; 494 defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq", 495 int_x86_mmx_psll_q, int_x86_mmx_pslli_q, 496 MMX_SHIFT_ITINS>; 497 498 def : Pat<(int_x86_mmx_psll_w VR64:$src1, (load_mvmmx addr:$src2)), 499 (MMX_PSLLWrm VR64:$src1, addr:$src2)>; 500 def : Pat<(int_x86_mmx_psll_d VR64:$src1, (load_mvmmx addr:$src2)), 501 (MMX_PSLLDrm VR64:$src1, addr:$src2)>; 502 def : Pat<(int_x86_mmx_psll_q VR64:$src1, (load_mvmmx addr:$src2)), 503 (MMX_PSLLQrm VR64:$src1, addr:$src2)>; 504 505 defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw", 506 int_x86_mmx_psra_w, int_x86_mmx_psrai_w, 507 MMX_SHIFT_ITINS>; 508 defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad", 509 int_x86_mmx_psra_d, int_x86_mmx_psrai_d, 510 MMX_SHIFT_ITINS>; 511 512 def : Pat<(int_x86_mmx_psra_w VR64:$src1, (load_mvmmx addr:$src2)), 513 (MMX_PSRAWrm VR64:$src1, addr:$src2)>; 514 def : Pat<(int_x86_mmx_psra_d VR64:$src1, (load_mvmmx addr:$src2)), 515 (MMX_PSRADrm VR64:$src1, addr:$src2)>; 516 517 // Comparison Instructions 518 defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b, 519 MMX_INTALU_ITINS>; 520 defm MMX_PCMPEQW : MMXI_binop_rm_int<0x75, "pcmpeqw", int_x86_mmx_pcmpeq_w, 521 MMX_INTALU_ITINS>; 522 defm MMX_PCMPEQD : MMXI_binop_rm_int<0x76, "pcmpeqd", int_x86_mmx_pcmpeq_d, 523 MMX_INTALU_ITINS>; 524 525 defm MMX_PCMPGTB : MMXI_binop_rm_int<0x64, "pcmpgtb", int_x86_mmx_pcmpgt_b, 526 MMX_INTALU_ITINS>; 527 defm MMX_PCMPGTW : MMXI_binop_rm_int<0x65, "pcmpgtw", int_x86_mmx_pcmpgt_w, 528 MMX_INTALU_ITINS>; 529 defm MMX_PCMPGTD : MMXI_binop_rm_int<0x66, "pcmpgtd", int_x86_mmx_pcmpgt_d, 530 MMX_INTALU_ITINS>; 531 532 // -- Unpack Instructions 533 defm MMX_PUNPCKHBW : MMXI_binop_rm_int<0x68, "punpckhbw", 534 int_x86_mmx_punpckhbw, 535 MMX_UNPCK_H_ITINS>; 536 defm MMX_PUNPCKHWD : MMXI_binop_rm_int<0x69, "punpckhwd", 537 int_x86_mmx_punpckhwd, 538 MMX_UNPCK_H_ITINS>; 539 defm MMX_PUNPCKHDQ : MMXI_binop_rm_int<0x6A, "punpckhdq", 540 int_x86_mmx_punpckhdq, 541 MMX_UNPCK_H_ITINS>; 542 defm MMX_PUNPCKLBW : MMXI_binop_rm_int<0x60, "punpcklbw", 543 int_x86_mmx_punpcklbw, 544 MMX_UNPCK_L_ITINS>; 545 defm MMX_PUNPCKLWD : MMXI_binop_rm_int<0x61, "punpcklwd", 546 int_x86_mmx_punpcklwd, 547 MMX_UNPCK_L_ITINS>; 548 defm MMX_PUNPCKLDQ : MMXI_binop_rm_int<0x62, "punpckldq", 549 int_x86_mmx_punpckldq, 550 MMX_UNPCK_L_ITINS>; 551 552 // -- Pack Instructions 553 defm MMX_PACKSSWB : MMXI_binop_rm_int<0x63, "packsswb", int_x86_mmx_packsswb, 554 MMX_PCK_ITINS>; 555 defm MMX_PACKSSDW : MMXI_binop_rm_int<0x6B, "packssdw", int_x86_mmx_packssdw, 556 MMX_PCK_ITINS>; 557 defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb, 558 MMX_PCK_ITINS>; 559 560 // -- Shuffle Instructions 561 defm MMX_PSHUFB : SS3I_binop_rm_int_mm<0x00, "pshufb", int_x86_ssse3_pshuf_b, 562 MMX_PSHUF_ITINS>; 563 564 def MMX_PSHUFWri : MMXIi8<0x70, MRMSrcReg, 565 (outs VR64:$dst), (ins VR64:$src1, u8imm:$src2), 566 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}", 567 [(set VR64:$dst, 568 (int_x86_sse_pshuf_w VR64:$src1, imm:$src2))], 569 IIC_MMX_PSHUF>, Sched<[WriteShuffle]>; 570 def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem, 571 (outs VR64:$dst), (ins i64mem:$src1, u8imm:$src2), 572 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}", 573 [(set VR64:$dst, 574 (int_x86_sse_pshuf_w (load_mmx addr:$src1), 575 imm:$src2))], 576 IIC_MMX_PSHUF>, Sched<[WriteShuffleLd]>; 577 578 579 580 581 // -- Conversion Instructions 582 defm MMX_CVTPS2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtps2pi, 583 f64mem, load, "cvtps2pi\t{$src, $dst|$dst, $src}", 584 MMX_CVT_PS_ITINS, SSEPackedSingle>, PS; 585 defm MMX_CVTPD2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtpd2pi, 586 f128mem, memop, "cvtpd2pi\t{$src, $dst|$dst, $src}", 587 MMX_CVT_PD_ITINS, SSEPackedDouble>, PD; 588 defm MMX_CVTTPS2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttps2pi, 589 f64mem, load, "cvttps2pi\t{$src, $dst|$dst, $src}", 590 MMX_CVT_PS_ITINS, SSEPackedSingle>, PS; 591 defm MMX_CVTTPD2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttpd2pi, 592 f128mem, memop, "cvttpd2pi\t{$src, $dst|$dst, $src}", 593 MMX_CVT_PD_ITINS, SSEPackedDouble>, PD; 594 defm MMX_CVTPI2PD : sse12_cvt_pint<0x2A, VR64, VR128, int_x86_sse_cvtpi2pd, 595 i64mem, load, "cvtpi2pd\t{$src, $dst|$dst, $src}", 596 MMX_CVT_PD_ITINS, SSEPackedDouble>, PD; 597 let Constraints = "$src1 = $dst" in { 598 defm MMX_CVTPI2PS : sse12_cvt_pint_3addr<0x2A, VR64, VR128, 599 int_x86_sse_cvtpi2ps, 600 i64mem, load, "cvtpi2ps\t{$src2, $dst|$dst, $src2}", 601 SSEPackedSingle>, PS; 602 } 603 604 // Extract / Insert 605 let Predicates = [HasSSE1] in 606 def MMX_PEXTRWirri: MMXIi8<0xC5, MRMSrcReg, 607 (outs GR32orGR64:$dst), (ins VR64:$src1, i32u8imm:$src2), 608 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}", 609 [(set GR32orGR64:$dst, (int_x86_mmx_pextr_w VR64:$src1, 610 imm:$src2))], 611 IIC_MMX_PEXTR>, Sched<[WriteShuffle]>; 612 let Constraints = "$src1 = $dst" in { 613 let Predicates = [HasSSE1] in { 614 def MMX_PINSRWirri : MMXIi8<0xC4, MRMSrcReg, 615 (outs VR64:$dst), 616 (ins VR64:$src1, GR32orGR64:$src2, i32u8imm:$src3), 617 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}", 618 [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1, 619 GR32orGR64:$src2, imm:$src3))], 620 IIC_MMX_PINSRW>, Sched<[WriteShuffle]>; 621 622 def MMX_PINSRWirmi : MMXIi8<0xC4, MRMSrcMem, 623 (outs VR64:$dst), 624 (ins VR64:$src1, i16mem:$src2, i32u8imm:$src3), 625 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}", 626 [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1, 627 (i32 (anyext (loadi16 addr:$src2))), 628 imm:$src3))], 629 IIC_MMX_PINSRW>, Sched<[WriteShuffleLd, ReadAfterLd]>; 630 } 631 } 632 633 // Mask creation 634 let Predicates = [HasSSE1] in 635 def MMX_PMOVMSKBrr : MMXI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst), 636 (ins VR64:$src), 637 "pmovmskb\t{$src, $dst|$dst, $src}", 638 [(set GR32orGR64:$dst, 639 (int_x86_mmx_pmovmskb VR64:$src))]>; 640 641 642 // Low word of XMM to MMX. 643 def MMX_X86movdq2q : SDNode<"X86ISD::MOVDQ2Q", SDTypeProfile<1, 1, 644 [SDTCisVT<0, x86mmx>, SDTCisVT<1, v2i64>]>>; 645 646 def : Pat<(x86mmx (MMX_X86movdq2q VR128:$src)), 647 (x86mmx (MMX_MOVDQ2Qrr VR128:$src))>; 648 649 def : Pat<(x86mmx (MMX_X86movdq2q (loadv2i64 addr:$src))), 650 (x86mmx (MMX_MOVQ64rm addr:$src))>; 651 652 // Misc. 653 let SchedRW = [WriteShuffle] in { 654 let Uses = [EDI], Predicates = [HasSSE1,In32BitMode] in 655 def MMX_MASKMOVQ : MMXI32<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask), 656 "maskmovq\t{$mask, $src|$src, $mask}", 657 [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, EDI)], 658 IIC_MMX_MASKMOV>; 659 let Uses = [RDI], Predicates = [HasSSE1,In64BitMode] in 660 def MMX_MASKMOVQ64: MMXI64<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask), 661 "maskmovq\t{$mask, $src|$src, $mask}", 662 [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, RDI)], 663 IIC_MMX_MASKMOV>; 664 } 665 666 // 64-bit bit convert. 667 let Predicates = [HasSSE2] in { 668 def : Pat<(f64 (bitconvert (x86mmx VR64:$src))), 669 (MMX_MOVQ2FR64rr VR64:$src)>; 670 def : Pat<(x86mmx (bitconvert (f64 FR64:$src))), 671 (MMX_MOVFR642Qrr FR64:$src)>; 672 } 673 674 675
