1 //===-- X86InstrSVM.td - SVM Instruction Set Extension -----*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the instructions that make up the AMD SVM instruction 11 // set. 12 // 13 //===----------------------------------------------------------------------===// 14 15 //===----------------------------------------------------------------------===// 16 // SVM instructions 17 18 // 0F 01 D9 19 def VMMCALL : I<0x01, MRM_D9, (outs), (ins), "vmmcall", []>, TB; 20 21 // 0F 01 DC 22 def STGI : I<0x01, MRM_DC, (outs), (ins), "stgi", []>, TB; 23 24 // 0F 01 DD 25 def CLGI : I<0x01, MRM_DD, (outs), (ins), "clgi", []>, TB; 26 27 // 0F 01 DE 28 let Uses = [EAX] in 29 def SKINIT : I<0x01, MRM_DE, (outs), (ins), "skinit\t{%eax|eax}", []>, TB; 30 31 // 0F 01 D8 32 let Uses = [EAX] in 33 def VMRUN32 : I<0x01, MRM_D8, (outs), (ins), 34 "vmrun\t{%eax|eax}", []>, TB, Requires<[Not64BitMode]>; 35 let Uses = [RAX] in 36 def VMRUN64 : I<0x01, MRM_D8, (outs), (ins), 37 "vmrun\t{%rax|rax}", []>, TB, Requires<[In64BitMode]>; 38 39 // 0F 01 DA 40 let Uses = [EAX] in 41 def VMLOAD32 : I<0x01, MRM_DA, (outs), (ins), 42 "vmload\t{%eax|eax}", []>, TB, Requires<[Not64BitMode]>; 43 let Uses = [RAX] in 44 def VMLOAD64 : I<0x01, MRM_DA, (outs), (ins), 45 "vmload\t{%rax|rax}", []>, TB, Requires<[In64BitMode]>; 46 47 // 0F 01 DB 48 let Uses = [EAX] in 49 def VMSAVE32 : I<0x01, MRM_DB, (outs), (ins), 50 "vmsave\t{%eax|eax}", []>, TB, Requires<[Not64BitMode]>; 51 let Uses = [RAX] in 52 def VMSAVE64 : I<0x01, MRM_DB, (outs), (ins), 53 "vmsave\t{%rax|rax}", []>, TB, Requires<[In64BitMode]>; 54 55 // 0F 01 DF 56 let Uses = [EAX, ECX] in 57 def INVLPGA32 : I<0x01, MRM_DF, (outs), (ins), 58 "invlpga\t{%ecx, %eax|eax, ecx}", []>, TB, Requires<[Not64BitMode]>; 59 let Uses = [RAX, ECX] in 60 def INVLPGA64 : I<0x01, MRM_DF, (outs), (ins), 61 "invlpga\t{%ecx, %rax|rax, ecx}", []>, TB, Requires<[In64BitMode]>; 62 63