1 //===-- X86InstrXOP.td - XOP Instruction Set ---------------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes XOP (eXtended OPerations) 11 // 12 //===----------------------------------------------------------------------===// 13 14 multiclass xop2op<bits<8> opc, string OpcodeStr, Intrinsic Int, PatFrag memop> { 15 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), 16 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), 17 [(set VR128:$dst, (Int VR128:$src))]>, XOP; 18 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), 19 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), 20 [(set VR128:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP; 21 } 22 23 let ExeDomain = SSEPackedInt in { 24 defm VPHSUBWD : xop2op<0xE2, "vphsubwd", int_x86_xop_vphsubwd, loadv2i64>; 25 defm VPHSUBDQ : xop2op<0xE3, "vphsubdq", int_x86_xop_vphsubdq, loadv2i64>; 26 defm VPHSUBBW : xop2op<0xE1, "vphsubbw", int_x86_xop_vphsubbw, loadv2i64>; 27 defm VPHADDWQ : xop2op<0xC7, "vphaddwq", int_x86_xop_vphaddwq, loadv2i64>; 28 defm VPHADDWD : xop2op<0xC6, "vphaddwd", int_x86_xop_vphaddwd, loadv2i64>; 29 defm VPHADDUWQ : xop2op<0xD7, "vphadduwq", int_x86_xop_vphadduwq, loadv2i64>; 30 defm VPHADDUWD : xop2op<0xD6, "vphadduwd", int_x86_xop_vphadduwd, loadv2i64>; 31 defm VPHADDUDQ : xop2op<0xDB, "vphaddudq", int_x86_xop_vphaddudq, loadv2i64>; 32 defm VPHADDUBW : xop2op<0xD1, "vphaddubw", int_x86_xop_vphaddubw, loadv2i64>; 33 defm VPHADDUBQ : xop2op<0xD3, "vphaddubq", int_x86_xop_vphaddubq, loadv2i64>; 34 defm VPHADDUBD : xop2op<0xD2, "vphaddubd", int_x86_xop_vphaddubd, loadv2i64>; 35 defm VPHADDDQ : xop2op<0xCB, "vphadddq", int_x86_xop_vphadddq, loadv2i64>; 36 defm VPHADDBW : xop2op<0xC1, "vphaddbw", int_x86_xop_vphaddbw, loadv2i64>; 37 defm VPHADDBQ : xop2op<0xC3, "vphaddbq", int_x86_xop_vphaddbq, loadv2i64>; 38 defm VPHADDBD : xop2op<0xC2, "vphaddbd", int_x86_xop_vphaddbd, loadv2i64>; 39 } 40 41 // Scalar load 2 addr operand instructions 42 multiclass xop2opsld<bits<8> opc, string OpcodeStr, Intrinsic Int, 43 Operand memop, ComplexPattern mem_cpat> { 44 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), 45 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), 46 [(set VR128:$dst, (Int VR128:$src))]>, XOP; 47 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins memop:$src), 48 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), 49 [(set VR128:$dst, (Int (bitconvert mem_cpat:$src)))]>, XOP; 50 } 51 52 multiclass xop2op128<bits<8> opc, string OpcodeStr, Intrinsic Int, 53 PatFrag memop> { 54 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), 55 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), 56 [(set VR128:$dst, (Int VR128:$src))]>, XOP; 57 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), 58 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), 59 [(set VR128:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP; 60 } 61 62 multiclass xop2op256<bits<8> opc, string OpcodeStr, Intrinsic Int, 63 PatFrag memop> { 64 def rrY : IXOP<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src), 65 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), 66 [(set VR256:$dst, (Int VR256:$src))]>, XOP, VEX_L; 67 def rmY : IXOP<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src), 68 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), 69 [(set VR256:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP, VEX_L; 70 } 71 72 let ExeDomain = SSEPackedSingle in { 73 defm VFRCZSS : xop2opsld<0x82, "vfrczss", int_x86_xop_vfrcz_ss, 74 ssmem, sse_load_f32>; 75 defm VFRCZPS : xop2op128<0x80, "vfrczps", int_x86_xop_vfrcz_ps, loadv4f32>; 76 defm VFRCZPS : xop2op256<0x80, "vfrczps", int_x86_xop_vfrcz_ps_256, loadv8f32>; 77 } 78 79 let ExeDomain = SSEPackedDouble in { 80 defm VFRCZSD : xop2opsld<0x83, "vfrczsd", int_x86_xop_vfrcz_sd, 81 sdmem, sse_load_f64>; 82 defm VFRCZPD : xop2op128<0x81, "vfrczpd", int_x86_xop_vfrcz_pd, loadv2f64>; 83 defm VFRCZPD : xop2op256<0x81, "vfrczpd", int_x86_xop_vfrcz_pd_256, loadv4f64>; 84 } 85 86 multiclass xop3op<bits<8> opc, string OpcodeStr, SDNode OpNode, 87 ValueType vt128> { 88 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), 89 (ins VR128:$src1, VR128:$src2), 90 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 91 [(set VR128:$dst, 92 (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2))))]>, 93 XOP_4VOp3, Sched<[WriteVarVecShift]>; 94 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), 95 (ins VR128:$src1, i128mem:$src2), 96 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 97 [(set VR128:$dst, 98 (vt128 (OpNode (vt128 VR128:$src1), 99 (vt128 (bitconvert (loadv2i64 addr:$src2))))))]>, 100 XOP_4V, VEX_W, Sched<[WriteVarVecShift, ReadAfterLd]>; 101 def mr : IXOP<opc, MRMSrcMem, (outs VR128:$dst), 102 (ins i128mem:$src1, VR128:$src2), 103 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 104 [(set VR128:$dst, 105 (vt128 (OpNode (vt128 (bitconvert (loadv2i64 addr:$src1))), 106 (vt128 VR128:$src2))))]>, 107 XOP_4VOp3, Sched<[WriteVarVecShift, ReadAfterLd]>; 108 } 109 110 let ExeDomain = SSEPackedInt in { 111 defm VPROTB : xop3op<0x90, "vprotb", X86vprot, v16i8>; 112 defm VPROTD : xop3op<0x92, "vprotd", X86vprot, v4i32>; 113 defm VPROTQ : xop3op<0x93, "vprotq", X86vprot, v2i64>; 114 defm VPROTW : xop3op<0x91, "vprotw", X86vprot, v8i16>; 115 defm VPSHAB : xop3op<0x98, "vpshab", X86vpsha, v16i8>; 116 defm VPSHAD : xop3op<0x9A, "vpshad", X86vpsha, v4i32>; 117 defm VPSHAQ : xop3op<0x9B, "vpshaq", X86vpsha, v2i64>; 118 defm VPSHAW : xop3op<0x99, "vpshaw", X86vpsha, v8i16>; 119 defm VPSHLB : xop3op<0x94, "vpshlb", X86vpshl, v16i8>; 120 defm VPSHLD : xop3op<0x96, "vpshld", X86vpshl, v4i32>; 121 defm VPSHLQ : xop3op<0x97, "vpshlq", X86vpshl, v2i64>; 122 defm VPSHLW : xop3op<0x95, "vpshlw", X86vpshl, v8i16>; 123 } 124 125 multiclass xop3opimm<bits<8> opc, string OpcodeStr, SDNode OpNode, 126 ValueType vt128> { 127 def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst), 128 (ins VR128:$src1, u8imm:$src2), 129 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 130 [(set VR128:$dst, 131 (vt128 (OpNode (vt128 VR128:$src1), imm:$src2)))]>, XOP; 132 def mi : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst), 133 (ins i128mem:$src1, u8imm:$src2), 134 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 135 [(set VR128:$dst, 136 (vt128 (OpNode (vt128 (bitconvert (loadv2i64 addr:$src1))), imm:$src2)))]>, XOP; 137 } 138 139 let ExeDomain = SSEPackedInt in { 140 defm VPROTB : xop3opimm<0xC0, "vprotb", X86vproti, v16i8>; 141 defm VPROTD : xop3opimm<0xC2, "vprotd", X86vproti, v4i32>; 142 defm VPROTQ : xop3opimm<0xC3, "vprotq", X86vproti, v2i64>; 143 defm VPROTW : xop3opimm<0xC1, "vprotw", X86vproti, v8i16>; 144 } 145 146 // Instruction where second source can be memory, but third must be register 147 multiclass xop4opm2<bits<8> opc, string OpcodeStr, Intrinsic Int> { 148 let isCommutable = 1 in 149 def rr : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst), 150 (ins VR128:$src1, VR128:$src2, VR128:$src3), 151 !strconcat(OpcodeStr, 152 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 153 [(set VR128:$dst, 154 (Int VR128:$src1, VR128:$src2, VR128:$src3))]>, XOP_4V, VEX_I8IMM; 155 def rm : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst), 156 (ins VR128:$src1, i128mem:$src2, VR128:$src3), 157 !strconcat(OpcodeStr, 158 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 159 [(set VR128:$dst, 160 (Int VR128:$src1, (bitconvert (loadv2i64 addr:$src2)), 161 VR128:$src3))]>, XOP_4V, VEX_I8IMM; 162 } 163 164 let ExeDomain = SSEPackedInt in { 165 defm VPMADCSWD : xop4opm2<0xB6, "vpmadcswd", int_x86_xop_vpmadcswd>; 166 defm VPMADCSSWD : xop4opm2<0xA6, "vpmadcsswd", int_x86_xop_vpmadcsswd>; 167 defm VPMACSWW : xop4opm2<0x95, "vpmacsww", int_x86_xop_vpmacsww>; 168 defm VPMACSWD : xop4opm2<0x96, "vpmacswd", int_x86_xop_vpmacswd>; 169 defm VPMACSSWW : xop4opm2<0x85, "vpmacssww", int_x86_xop_vpmacssww>; 170 defm VPMACSSWD : xop4opm2<0x86, "vpmacsswd", int_x86_xop_vpmacsswd>; 171 defm VPMACSSDQL : xop4opm2<0x87, "vpmacssdql", int_x86_xop_vpmacssdql>; 172 defm VPMACSSDQH : xop4opm2<0x8F, "vpmacssdqh", int_x86_xop_vpmacssdqh>; 173 defm VPMACSSDD : xop4opm2<0x8E, "vpmacssdd", int_x86_xop_vpmacssdd>; 174 defm VPMACSDQL : xop4opm2<0x97, "vpmacsdql", int_x86_xop_vpmacsdql>; 175 defm VPMACSDQH : xop4opm2<0x9F, "vpmacsdqh", int_x86_xop_vpmacsdqh>; 176 defm VPMACSDD : xop4opm2<0x9E, "vpmacsdd", int_x86_xop_vpmacsdd>; 177 } 178 179 // Instruction where second source can be memory, third must be imm8 180 multiclass xopvpcom<bits<8> opc, string Suffix, SDNode OpNode, ValueType vt128> { 181 let isCommutable = 1 in 182 def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst), 183 (ins VR128:$src1, VR128:$src2, XOPCC:$cc), 184 !strconcat("vpcom${cc}", Suffix, 185 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 186 [(set VR128:$dst, 187 (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2), 188 i8immZExt3:$cc)))]>, 189 XOP_4V; 190 def mi : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst), 191 (ins VR128:$src1, i128mem:$src2, XOPCC:$cc), 192 !strconcat("vpcom${cc}", Suffix, 193 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 194 [(set VR128:$dst, 195 (vt128 (OpNode (vt128 VR128:$src1), 196 (vt128 (bitconvert (loadv2i64 addr:$src2))), 197 i8immZExt3:$cc)))]>, 198 XOP_4V; 199 let isAsmParserOnly = 1, hasSideEffects = 0 in { 200 def ri_alt : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst), 201 (ins VR128:$src1, VR128:$src2, u8imm:$src3), 202 !strconcat("vpcom", Suffix, 203 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 204 []>, XOP_4V; 205 let mayLoad = 1 in 206 def mi_alt : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst), 207 (ins VR128:$src1, i128mem:$src2, u8imm:$src3), 208 !strconcat("vpcom", Suffix, 209 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 210 []>, XOP_4V; 211 } 212 } 213 214 let ExeDomain = SSEPackedInt in { // SSE integer instructions 215 defm VPCOMB : xopvpcom<0xCC, "b", X86vpcom, v16i8>; 216 defm VPCOMW : xopvpcom<0xCD, "w", X86vpcom, v8i16>; 217 defm VPCOMD : xopvpcom<0xCE, "d", X86vpcom, v4i32>; 218 defm VPCOMQ : xopvpcom<0xCF, "q", X86vpcom, v2i64>; 219 defm VPCOMUB : xopvpcom<0xEC, "ub", X86vpcomu, v16i8>; 220 defm VPCOMUW : xopvpcom<0xED, "uw", X86vpcomu, v8i16>; 221 defm VPCOMUD : xopvpcom<0xEE, "ud", X86vpcomu, v4i32>; 222 defm VPCOMUQ : xopvpcom<0xEF, "uq", X86vpcomu, v2i64>; 223 } 224 225 // Instruction where either second or third source can be memory 226 multiclass xop4op<bits<8> opc, string OpcodeStr, Intrinsic Int> { 227 def rr : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst), 228 (ins VR128:$src1, VR128:$src2, VR128:$src3), 229 !strconcat(OpcodeStr, 230 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 231 [(set VR128:$dst, (Int VR128:$src1, VR128:$src2, VR128:$src3))]>, 232 XOP_4V, VEX_I8IMM; 233 def rm : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst), 234 (ins VR128:$src1, VR128:$src2, i128mem:$src3), 235 !strconcat(OpcodeStr, 236 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 237 [(set VR128:$dst, 238 (Int VR128:$src1, VR128:$src2, 239 (bitconvert (loadv2i64 addr:$src3))))]>, 240 XOP_4V, VEX_I8IMM, VEX_W, MemOp4; 241 def mr : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst), 242 (ins VR128:$src1, i128mem:$src2, VR128:$src3), 243 !strconcat(OpcodeStr, 244 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 245 [(set VR128:$dst, 246 (Int VR128:$src1, (bitconvert (loadv2i64 addr:$src2)), 247 VR128:$src3))]>, 248 XOP_4V, VEX_I8IMM; 249 } 250 251 let ExeDomain = SSEPackedInt in { 252 defm VPPERM : xop4op<0xA3, "vpperm", int_x86_xop_vpperm>; 253 defm VPCMOV : xop4op<0xA2, "vpcmov", int_x86_xop_vpcmov>; 254 } 255 256 multiclass xop4op256<bits<8> opc, string OpcodeStr, Intrinsic Int> { 257 def rrY : IXOPi8<opc, MRMSrcReg, (outs VR256:$dst), 258 (ins VR256:$src1, VR256:$src2, VR256:$src3), 259 !strconcat(OpcodeStr, 260 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 261 [(set VR256:$dst, (Int VR256:$src1, VR256:$src2, VR256:$src3))]>, 262 XOP_4V, VEX_I8IMM, VEX_L; 263 def rmY : IXOPi8<opc, MRMSrcMem, (outs VR256:$dst), 264 (ins VR256:$src1, VR256:$src2, i256mem:$src3), 265 !strconcat(OpcodeStr, 266 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 267 [(set VR256:$dst, 268 (Int VR256:$src1, VR256:$src2, 269 (bitconvert (loadv4i64 addr:$src3))))]>, 270 XOP_4V, VEX_I8IMM, VEX_W, MemOp4, VEX_L; 271 def mrY : IXOPi8<opc, MRMSrcMem, (outs VR256:$dst), 272 (ins VR256:$src1, f256mem:$src2, VR256:$src3), 273 !strconcat(OpcodeStr, 274 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 275 [(set VR256:$dst, 276 (Int VR256:$src1, (bitconvert (loadv4i64 addr:$src2)), 277 VR256:$src3))]>, 278 XOP_4V, VEX_I8IMM, VEX_L; 279 } 280 281 let ExeDomain = SSEPackedInt in 282 defm VPCMOV : xop4op256<0xA2, "vpcmov", int_x86_xop_vpcmov_256>; 283 284 let Predicates = [HasXOP] in { 285 def : Pat<(v2i64 (or (and VR128:$src3, VR128:$src1), 286 (X86andnp VR128:$src3, VR128:$src2))), 287 (VPCMOVrr VR128:$src1, VR128:$src2, VR128:$src3)>; 288 289 def : Pat<(v4i64 (or (and VR256:$src3, VR256:$src1), 290 (X86andnp VR256:$src3, VR256:$src2))), 291 (VPCMOVrrY VR256:$src1, VR256:$src2, VR256:$src3)>; 292 } 293 294 multiclass xop5op<bits<8> opc, string OpcodeStr, Intrinsic Int128, 295 Intrinsic Int256, PatFrag ld_128, PatFrag ld_256> { 296 def rr : IXOP5<opc, MRMSrcReg, (outs VR128:$dst), 297 (ins VR128:$src1, VR128:$src2, VR128:$src3, u8imm:$src4), 298 !strconcat(OpcodeStr, 299 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"), 300 [(set VR128:$dst, 301 (Int128 VR128:$src1, VR128:$src2, VR128:$src3, imm:$src4))]>; 302 def rm : IXOP5<opc, MRMSrcMem, (outs VR128:$dst), 303 (ins VR128:$src1, VR128:$src2, f128mem:$src3, u8imm:$src4), 304 !strconcat(OpcodeStr, 305 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"), 306 [(set VR128:$dst, 307 (Int128 VR128:$src1, VR128:$src2, (ld_128 addr:$src3), imm:$src4))]>, 308 VEX_W, MemOp4; 309 def mr : IXOP5<opc, MRMSrcMem, (outs VR128:$dst), 310 (ins VR128:$src1, f128mem:$src2, VR128:$src3, u8imm:$src4), 311 !strconcat(OpcodeStr, 312 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"), 313 [(set VR128:$dst, 314 (Int128 VR128:$src1, (ld_128 addr:$src2), VR128:$src3, imm:$src4))]>; 315 def rrY : IXOP5<opc, MRMSrcReg, (outs VR256:$dst), 316 (ins VR256:$src1, VR256:$src2, VR256:$src3, u8imm:$src4), 317 !strconcat(OpcodeStr, 318 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"), 319 [(set VR256:$dst, 320 (Int256 VR256:$src1, VR256:$src2, VR256:$src3, imm:$src4))]>, VEX_L; 321 def rmY : IXOP5<opc, MRMSrcMem, (outs VR256:$dst), 322 (ins VR256:$src1, VR256:$src2, f256mem:$src3, u8imm:$src4), 323 !strconcat(OpcodeStr, 324 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"), 325 [(set VR256:$dst, 326 (Int256 VR256:$src1, VR256:$src2, (ld_256 addr:$src3), imm:$src4))]>, 327 VEX_W, MemOp4, VEX_L; 328 def mrY : IXOP5<opc, MRMSrcMem, (outs VR256:$dst), 329 (ins VR256:$src1, f256mem:$src2, VR256:$src3, u8imm:$src4), 330 !strconcat(OpcodeStr, 331 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"), 332 [(set VR256:$dst, 333 (Int256 VR256:$src1, (ld_256 addr:$src2), VR256:$src3, imm:$src4))]>, 334 VEX_L; 335 } 336 337 let ExeDomain = SSEPackedDouble in 338 defm VPERMIL2PD : xop5op<0x49, "vpermil2pd", int_x86_xop_vpermil2pd, 339 int_x86_xop_vpermil2pd_256, loadv2f64, loadv4f64>; 340 341 let ExeDomain = SSEPackedSingle in 342 defm VPERMIL2PS : xop5op<0x48, "vpermil2ps", int_x86_xop_vpermil2ps, 343 int_x86_xop_vpermil2ps_256, loadv4f32, loadv8f32>; 344 345
