1 ; RUN: llc -O1 -mcpu=cortex-a15 -mtriple=armv7-linux-gnueabi -disable-a15-sd-optimization -verify-machineinstrs < %s | FileCheck -check-prefix=CHECK-DISABLED %s 2 ; RUN: llc -O1 -mcpu=cortex-a15 -mtriple=armv7-linux-gnueabi -verify-machineinstrs < %s | FileCheck -check-prefix=CHECK-ENABLED %s 3 4 ; CHECK-ENABLED-LABEL: t1: 5 ; CHECK-DISABLED-LABEL: t1: 6 define <2 x float> @t1(float %f) { 7 ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d0[0] 8 ; CHECK-DISABLED-NOT: vdup.32 d{{[0-9]*}}, d0[0] 9 %i1 = insertelement <2 x float> undef, float %f, i32 1 10 %i2 = fadd <2 x float> %i1, %i1 11 ret <2 x float> %i2 12 } 13 14 ; CHECK-ENABLED-LABEL: t2: 15 ; CHECK-DISABLED-LABEL: t2: 16 define <4 x float> @t2(float %g, float %f) { 17 ; CHECK-ENABLED: vdup.32 q{{[0-9]*}}, d0[0] 18 ; CHECK-DISABLED-NOT: vdup.32 d{{[0-9]*}}, d0[0] 19 %i1 = insertelement <4 x float> undef, float %f, i32 1 20 %i2 = fadd <4 x float> %i1, %i1 21 ret <4 x float> %i2 22 } 23 24 ; CHECK-ENABLED-LABEL: t3: 25 ; CHECK-DISABLED-LABEL: t3: 26 define arm_aapcs_vfpcc <2 x float> @t3(float %f) { 27 ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d0[0] 28 ; CHECK-DISABLED-NOT: vdup.32 d{{[0-9]*}}, d0[0] 29 %i1 = insertelement <2 x float> undef, float %f, i32 1 30 %i2 = fadd <2 x float> %i1, %i1 31 ret <2 x float> %i2 32 } 33 34 ; CHECK-ENABLED-LABEL: t4: 35 ; CHECK-DISABLED-LABEL: t4: 36 define <2 x float> @t4(float %f) { 37 ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d0[0] 38 ; CHECK-DISABLED-NOT: vdup 39 %i1 = insertelement <2 x float> undef, float %f, i32 1 40 br label %b 41 42 ; Block %b has an S-reg as live-in. 43 b: 44 %i2 = fadd <2 x float> %i1, %i1 45 ret <2 x float> %i2 46 } 47 48 ; CHECK-ENABLED-LABEL: t5: 49 ; CHECK-DISABLED-LABEL: t5: 50 define arm_aapcs_vfpcc <4 x float> @t5(<4 x float> %q, float %f) { 51 ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d{{[0-9]*}}[0] 52 ; CHECK-ENABLED: vadd.f32 53 ; CHECK-ENABLED-NEXT: bx lr 54 ; CHECK-DISABLED-NOT: vdup 55 %i1 = insertelement <4 x float> %q, float %f, i32 1 56 %i2 = fadd <4 x float> %i1, %i1 57 ret <4 x float> %i2 58 } 59 60 ; Test that DPair can be successfully passed as QPR. 61 ; CHECK-ENABLED-LABEL: test_DPair1: 62 ; CHECK-DISABLED-LABEL: test_DPair1: 63 define void @test_DPair1(i32 %vsout, i8* nocapture %out, float %x, float %y) { 64 entry: 65 %0 = insertelement <4 x float> undef, float %x, i32 1 66 %1 = insertelement <4 x float> %0, float %y, i32 0 67 ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d{{[0-9]*}}[0] 68 ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d{{[0-9]*}}[1] 69 ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d{{[0-9]*}}[0] 70 ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d{{[0-9]*}}[1] 71 ; CHECK-DISABLED-NOT: vdup 72 switch i32 %vsout, label %sw.epilog [ 73 i32 1, label %sw.bb 74 i32 0, label %sw.bb6 75 ] 76 77 sw.bb: ; preds = %entry 78 %2 = insertelement <4 x float> %1, float 0.000000e+00, i32 0 79 br label %sw.bb6 80 81 sw.bb6: ; preds = %sw.bb, %entry 82 %sum.0 = phi <4 x float> [ %1, %entry ], [ %2, %sw.bb ] 83 %3 = extractelement <4 x float> %sum.0, i32 0 84 %conv = fptoui float %3 to i8 85 store i8 %conv, i8* %out, align 1 86 ret void 87 88 sw.epilog: ; preds = %entry 89 ret void 90 } 91 92 ; CHECK-ENABLED-LABEL: test_DPair2: 93 ; CHECK-DISABLED-LABEL: test_DPair2: 94 define void @test_DPair2(i32 %vsout, i8* nocapture %out, float %x) { 95 entry: 96 %0 = insertelement <4 x float> undef, float %x, i32 0 97 ; CHECK-ENABLED: vdup.32 q{{[0-9]*}}, d{{[0-9]*}}[0] 98 ; CHECK-DISABLED-NOT: vdup 99 switch i32 %vsout, label %sw.epilog [ 100 i32 1, label %sw.bb 101 i32 0, label %sw.bb1 102 ] 103 104 sw.bb: ; preds = %entry 105 %1 = insertelement <4 x float> %0, float 0.000000e+00, i32 0 106 br label %sw.bb1 107 108 sw.bb1: ; preds = %entry, %sw.bb 109 %sum.0 = phi <4 x float> [ %0, %entry ], [ %1, %sw.bb ] 110 %2 = extractelement <4 x float> %sum.0, i32 0 111 %conv = fptoui float %2 to i8 112 store i8 %conv, i8* %out, align 1 113 br label %sw.epilog 114 115 sw.epilog: ; preds = %entry, %sw.bb1 116 ret void 117 }
