1 ; RUN: llc -mattr=+fp16 < %s | FileCheck %s --check-prefix=CHECK 2 3 target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4 target triple = "armv7a--none-eabi" 5 6 ; CHECK-LABEL: test_vec3: 7 ; CHECK: vcvtb.f32.f16 8 ; CHECK: vcvt.f32.s32 9 ; CHECK: vadd.f32 10 ; CHECK-NEXT: vcvtb.f16.f32 [[SREG:s[0-9]+]], {{.*}} 11 ; CHECK-NEXT: vmov [[RREG1:r[0-9]+]], [[SREG]] 12 ; CHECK-NEXT: uxth [[RREG2:r[0-9]+]], [[RREG1]] 13 ; CHECK-NEXT: pkhbt [[RREG3:r[0-9]+]], [[RREG1]], [[RREG1]], lsl #16 14 ; CHECK-DAG: strh [[RREG1]], [r0, #4] 15 ; CHECK-DAG: vmov [[DREG:d[0-9]+]], [[RREG3]], [[RREG2]] 16 ; CHECK-DAG: vst1.32 {[[DREG]][0]}, [r0:32] 17 ; CHECK-NEXT: bx lr 18 define void @test_vec3(<3 x half>* %arr, i32 %i) #0 { 19 %H = sitofp i32 %i to half 20 %S = fadd half %H, 0xH4A00 21 %1 = insertelement <3 x half> undef, half %S, i32 0 22 %2 = insertelement <3 x half> %1, half %S, i32 1 23 %3 = insertelement <3 x half> %2, half %S, i32 2 24 store <3 x half> %3, <3 x half>* %arr, align 8 25 ret void 26 } 27 28 ; CHECK-LABEL: test_bitcast: 29 ; CHECK: vcvtb.f16.f32 30 ; CHECK: vcvtb.f16.f32 31 ; CHECK: vcvtb.f16.f32 32 ; CHECK: pkhbt 33 ; CHECK: uxth 34 define void @test_bitcast(<3 x half> %inp, <3 x i16>* %arr) #0 { 35 %bc = bitcast <3 x half> %inp to <3 x i16> 36 store <3 x i16> %bc, <3 x i16>* %arr, align 8 37 ret void 38 } 39 40 attributes #0 = { nounwind } 41
