1 ; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+neon,+v6t2 -no-integrated-as %s -o - \ 2 ; RUN: | FileCheck %s 3 4 ; Radar 7449043 5 %struct.int32x4_t = type { <4 x i32> } 6 7 define void @t() nounwind { 8 entry: 9 ; CHECK: vmov.I64 q15, #0 10 ; CHECK: vmov.32 d30[0], 11 ; CHECK: vmov q8, q15 12 %tmp = alloca %struct.int32x4_t, align 16 13 call void asm sideeffect "vmov.I64 q15, #0\0Avmov.32 d30[0], $1\0Avmov ${0:q}, q15\0A", "=*w,r,~{d31},~{d30}"(%struct.int32x4_t* %tmp, i32 8192) nounwind 14 ret void 15 } 16 17 ; Radar 7457110 18 %struct.int32x2_t = type { <4 x i32> } 19 20 define void @t2() nounwind { 21 entry: 22 ; CHECK: vmov d30, d16 23 ; CHECK: vmov.32 r0, d30[0] 24 %asmtmp2 = tail call i32 asm sideeffect "vmov d30, $1\0Avmov.32 $0, d30[0]\0A", "=r,w,~{d30}"(<2 x i32> undef) nounwind 25 ret void 26 } 27 28 ; Radar 9306086 29 30 %0 = type { <8 x i8>, <16 x i8>* } 31 32 define hidden void @conv4_8_E() nounwind { 33 entry: 34 %asmtmp31 = call %0 asm "vld1.u8 {$0}, [$1:128]!\0A", "=w,=r,1"(<16 x i8>* undef) nounwind 35 unreachable 36 } 37 38 ; Radar 9037836 & 9119939 39 40 define i32 @t3() nounwind { 41 entry: 42 tail call void asm sideeffect "flds s15, $0 \0A", "^Uv|m,~{s15}"(float 1.000000e+00) nounwind 43 ret i32 0 44 } 45 46 ; Radar 9037836 & 9119939 47 48 @k.2126 = internal unnamed_addr global float 1.000000e+00 49 define i32 @t4() nounwind { 50 entry: 51 call void asm sideeffect "flds s15, $0 \0A", "*^Uv,~{s15}"(float* @k.2126) nounwind 52 ret i32 0 53 } 54 55 ; Radar 9037836 & 9119939 56 57 define i32 @t5() nounwind { 58 entry: 59 call void asm sideeffect "flds s15, $0 \0A", "*^Uvm,~{s15}"(float* @k.2126) nounwind 60 ret i32 0 61 } 62 63 ; Radar 9307836 & 9119939 64 65 define float @t6(float %y) nounwind { 66 entry: 67 ; CHECK: t6 68 ; CHECK: flds s15, s0 69 %0 = tail call float asm "flds s15, $0", "=x"() nounwind 70 ret float %0 71 } 72 73 ; Radar 9307836 & 9119939 74 75 define double @t7(double %y) nounwind { 76 entry: 77 ; CHECK: t7 78 ; CHECK: flds s15, d0 79 %0 = tail call double asm "flds s15, $0", "=x"() nounwind 80 ret double %0 81 } 82 83 ; Radar 9307836 & 9119939 84 85 define float @t8(float %y) nounwind { 86 entry: 87 ; CHECK: t8 88 ; CHECK: flds s15, s0 89 %0 = tail call float asm "flds s15, $0", "=t"() nounwind 90 ret float %0 91 } 92 93 ; Radar 9307836 & 9119939 94 95 define i32 @t9(i32 %r0) nounwind { 96 entry: 97 ; CHECK: t9 98 ; CHECK: movw r0, #27182 99 %0 = tail call i32 asm "movw $0, $1", "=r,j"(i32 27182) nounwind 100 ret i32 %0 101 } 102 103 ; Radar 9866494 104 105 define void @t10(i8* %f, i32 %g) nounwind { 106 entry: 107 ; CHECK: t10 108 ; CHECK: str r1, [r0] 109 %f.addr = alloca i8*, align 4 110 store i8* %f, i8** %f.addr, align 4 111 call void asm "str $1, $0", "=*Q,r"(i8** %f.addr, i32 %g) nounwind 112 ret void 113 } 114 115 ; Radar 10551006 116 117 define <4 x i32> @t11(i32* %p) nounwind { 118 entry: 119 ; CHECK: t11 120 ; CHECK: vld1.s32 {d16[], d17[]}, [r0] 121 %0 = tail call <4 x i32> asm "vld1.s32 {${0:e}[], ${0:f}[]}, [$1]", "=w,r"(i32* %p) nounwind 122 ret <4 x i32> %0 123 } 124
