1 ; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a8 -arm-atomic-cfg-tidy=0 | FileCheck %s 2 ; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a8 -arm-atomic-cfg-tidy=0 -regalloc=basic | FileCheck %s 3 ; Implementing vld / vst as REG_SEQUENCE eliminates the extra vmov's. 4 5 %struct.int16x8_t = type { <8 x i16> } 6 %struct.int32x4_t = type { <4 x i32> } 7 %struct.__neon_int8x8x2_t = type { <8 x i8>, <8 x i8> } 8 %struct.__neon_int8x8x3_t = type { <8 x i8>, <8 x i8>, <8 x i8> } 9 %struct.__neon_int16x8x2_t = type { <8 x i16>, <8 x i16> } 10 %struct.__neon_int32x4x2_t = type { <4 x i32>, <4 x i32> } 11 12 define void @t1(i16* %i_ptr, i16* %o_ptr, %struct.int32x4_t* nocapture %vT0ptr, %struct.int32x4_t* nocapture %vT1ptr) nounwind { 13 entry: 14 ; CHECK-LABEL: t1: 15 ; CHECK: vld1.16 16 ; CHECK-NOT: vmov d 17 ; CHECK: vmovl.s16 18 ; CHECK: vshrn.i32 19 ; CHECK: vshrn.i32 20 ; CHECK-NOT: vmov d 21 ; CHECK-NEXT: vst1.16 22 %0 = getelementptr inbounds %struct.int32x4_t, %struct.int32x4_t* %vT0ptr, i32 0, i32 0 ; <<4 x i32>*> [#uses=1] 23 %1 = load <4 x i32>, <4 x i32>* %0, align 16 ; <<4 x i32>> [#uses=1] 24 %2 = getelementptr inbounds %struct.int32x4_t, %struct.int32x4_t* %vT1ptr, i32 0, i32 0 ; <<4 x i32>*> [#uses=1] 25 %3 = load <4 x i32>, <4 x i32>* %2, align 16 ; <<4 x i32>> [#uses=1] 26 %4 = bitcast i16* %i_ptr to i8* ; <i8*> [#uses=1] 27 %5 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8* %4, i32 1) ; <<8 x i16>> [#uses=1] 28 %6 = bitcast <8 x i16> %5 to <2 x double> ; <<2 x double>> [#uses=2] 29 %7 = extractelement <2 x double> %6, i32 0 ; <double> [#uses=1] 30 %8 = bitcast double %7 to <4 x i16> ; <<4 x i16>> [#uses=1] 31 %9 = sext <4 x i16> %8 to <4 x i32> ; <<4 x i32>> [#uses=1] 32 %10 = extractelement <2 x double> %6, i32 1 ; <double> [#uses=1] 33 %11 = bitcast double %10 to <4 x i16> ; <<4 x i16>> [#uses=1] 34 %12 = sext <4 x i16> %11 to <4 x i32> ; <<4 x i32>> [#uses=1] 35 %13 = mul <4 x i32> %1, %9 ; <<4 x i32>> [#uses=1] 36 %14 = mul <4 x i32> %3, %12 ; <<4 x i32>> [#uses=1] 37 %15 = lshr <4 x i32> %13, <i32 12, i32 12, i32 12, i32 12> 38 %trunc_15 = trunc <4 x i32> %15 to <4 x i16> 39 %16 = lshr <4 x i32> %14, <i32 12, i32 12, i32 12, i32 12> 40 %trunc_16 = trunc <4 x i32> %16 to <4 x i16> 41 %17 = shufflevector <4 x i16> %trunc_15, <4 x i16> %trunc_16, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> ; <<8 x i16>> [#uses=1] 42 %18 = bitcast i16* %o_ptr to i8* ; <i8*> [#uses=1] 43 tail call void @llvm.arm.neon.vst1.p0i8.v8i16(i8* %18, <8 x i16> %17, i32 1) 44 ret void 45 } 46 47 define void @t2(i16* %i_ptr, i16* %o_ptr, %struct.int16x8_t* nocapture %vT0ptr, %struct.int16x8_t* nocapture %vT1ptr) nounwind { 48 entry: 49 ; CHECK-LABEL: t2: 50 ; CHECK: vld1.16 51 ; CHECK-NOT: vmov 52 ; CHECK: vmul.i16 53 ; CHECK: vld1.16 54 ; CHECK: vmul.i16 55 ; CHECK-NOT: vmov 56 ; CHECK: vst1.16 57 ; CHECK: vst1.16 58 %0 = getelementptr inbounds %struct.int16x8_t, %struct.int16x8_t* %vT0ptr, i32 0, i32 0 ; <<8 x i16>*> [#uses=1] 59 %1 = load <8 x i16>, <8 x i16>* %0, align 16 ; <<8 x i16>> [#uses=1] 60 %2 = getelementptr inbounds %struct.int16x8_t, %struct.int16x8_t* %vT1ptr, i32 0, i32 0 ; <<8 x i16>*> [#uses=1] 61 %3 = load <8 x i16>, <8 x i16>* %2, align 16 ; <<8 x i16>> [#uses=1] 62 %4 = bitcast i16* %i_ptr to i8* ; <i8*> [#uses=1] 63 %5 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8* %4, i32 1) ; <<8 x i16>> [#uses=1] 64 %6 = getelementptr inbounds i16, i16* %i_ptr, i32 8 ; <i16*> [#uses=1] 65 %7 = bitcast i16* %6 to i8* ; <i8*> [#uses=1] 66 %8 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8* %7, i32 1) ; <<8 x i16>> [#uses=1] 67 %9 = mul <8 x i16> %1, %5 ; <<8 x i16>> [#uses=1] 68 %10 = mul <8 x i16> %3, %8 ; <<8 x i16>> [#uses=1] 69 %11 = bitcast i16* %o_ptr to i8* ; <i8*> [#uses=1] 70 tail call void @llvm.arm.neon.vst1.p0i8.v8i16(i8* %11, <8 x i16> %9, i32 1) 71 %12 = getelementptr inbounds i16, i16* %o_ptr, i32 8 ; <i16*> [#uses=1] 72 %13 = bitcast i16* %12 to i8* ; <i8*> [#uses=1] 73 tail call void @llvm.arm.neon.vst1.p0i8.v8i16(i8* %13, <8 x i16> %10, i32 1) 74 ret void 75 } 76 77 define <8 x i8> @t3(i8* %A, i8* %B) nounwind { 78 ; CHECK-LABEL: t3: 79 ; CHECK: vld3.8 80 ; CHECK: vmul.i8 81 ; CHECK: vmov r 82 ; CHECK-NOT: vmov d 83 ; CHECK: vst3.8 84 %tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2] 85 %tmp2 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 0 ; <<8 x i8>> [#uses=1] 86 %tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 2 ; <<8 x i8>> [#uses=1] 87 %tmp4 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 1 ; <<8 x i8>> [#uses=1] 88 %tmp5 = sub <8 x i8> %tmp3, %tmp4 89 %tmp6 = add <8 x i8> %tmp2, %tmp3 ; <<8 x i8>> [#uses=1] 90 %tmp7 = mul <8 x i8> %tmp4, %tmp2 91 tail call void @llvm.arm.neon.vst3.p0i8.v8i8(i8* %B, <8 x i8> %tmp5, <8 x i8> %tmp6, <8 x i8> %tmp7, i32 1) 92 ret <8 x i8> %tmp4 93 } 94 95 define void @t4(i32* %in, i32* %out) nounwind { 96 entry: 97 ; CHECK-LABEL: t4: 98 ; CHECK: vld2.32 99 ; CHECK-NOT: vmov 100 ; CHECK: vld2.32 101 ; CHECK-NOT: vmov 102 ; CHECK: bne 103 %tmp1 = bitcast i32* %in to i8* ; <i8*> [#uses=1] 104 %tmp2 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32.p0i8(i8* %tmp1, i32 1) ; <%struct.__neon_int32x4x2_t> [#uses=2] 105 %tmp3 = getelementptr inbounds i32, i32* %in, i32 8 ; <i32*> [#uses=1] 106 %tmp4 = bitcast i32* %tmp3 to i8* ; <i8*> [#uses=1] 107 %tmp5 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32.p0i8(i8* %tmp4, i32 1) ; <%struct.__neon_int32x4x2_t> [#uses=2] 108 %tmp8 = bitcast i32* %out to i8* ; <i8*> [#uses=1] 109 br i1 undef, label %return1, label %return2 110 111 return1: 112 ; CHECK: %return1 113 ; CHECK-NOT: vmov 114 ; CHECK-NEXT: vadd.i32 115 ; CHECK-NEXT: vadd.i32 116 ; CHECK-NEXT: vst2.32 117 %tmp52 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 0 ; <<4 x i32>> [#uses=1] 118 %tmp57 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 1 ; <<4 x i32>> [#uses=1] 119 %tmp = extractvalue %struct.__neon_int32x4x2_t %tmp5, 0 ; <<4 x i32>> [#uses=1] 120 %tmp39 = extractvalue %struct.__neon_int32x4x2_t %tmp5, 1 ; <<4 x i32>> [#uses=1] 121 %tmp6 = add <4 x i32> %tmp52, %tmp ; <<4 x i32>> [#uses=1] 122 %tmp7 = add <4 x i32> %tmp57, %tmp39 ; <<4 x i32>> [#uses=1] 123 tail call void @llvm.arm.neon.vst2.p0i8.v4i32(i8* %tmp8, <4 x i32> %tmp6, <4 x i32> %tmp7, i32 1) 124 ret void 125 126 return2: 127 ; CHECK: %return2 128 ; CHECK: vadd.i32 129 ; CHECK-NOT: vmov 130 ; CHECK: vst2.32 {d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}} 131 %tmp100 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 0 ; <<4 x i32>> [#uses=1] 132 %tmp101 = extractvalue %struct.__neon_int32x4x2_t %tmp5, 1 ; <<4 x i32>> [#uses=1] 133 %tmp102 = add <4 x i32> %tmp100, %tmp101 ; <<4 x i32>> [#uses=1] 134 tail call void @llvm.arm.neon.vst2.p0i8.v4i32(i8* %tmp8, <4 x i32> %tmp102, <4 x i32> %tmp101, i32 1) 135 call void @llvm.trap() 136 unreachable 137 } 138 139 define <8 x i16> @t5(i16* %A, <8 x i16>* %B) nounwind { 140 ; CHECK-LABEL: t5: 141 ; CHECK: vld1.32 142 ; How can FileCheck match Q and D registers? We need a lisp interpreter. 143 ; CHECK: vorr {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}} 144 ; CHECK-NOT: vmov 145 ; CHECK: vld2.16 {d{{[0-9]+}}[1], d{{[0-9]+}}[1]}, [r0] 146 ; CHECK-NOT: vmov 147 ; CHECK: vadd.i16 148 %tmp0 = bitcast i16* %A to i8* ; <i8*> [#uses=1] 149 %tmp1 = load <8 x i16>, <8 x i16>* %B ; <<8 x i16>> [#uses=2] 150 %tmp2 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16.p0i8(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 1) ; <%struct.__neon_int16x8x2_t> [#uses=2] 151 %tmp3 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 0 ; <<8 x i16>> [#uses=1] 152 %tmp4 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 1 ; <<8 x i16>> [#uses=1] 153 %tmp5 = add <8 x i16> %tmp3, %tmp4 ; <<8 x i16>> [#uses=1] 154 ret <8 x i16> %tmp5 155 } 156 157 define <8 x i8> @t6(i8* %A, <8 x i8>* %B) nounwind { 158 ; CHECK-LABEL: t6: 159 ; CHECK: vldr 160 ; CHECK: vorr d[[D0:[0-9]+]], d[[D1:[0-9]+]] 161 ; CHECK-NEXT: vld2.8 {d[[D1]][1], d[[D0]][1]} 162 %tmp1 = load <8 x i8>, <8 x i8>* %B ; <<8 x i8>> [#uses=2] 163 %tmp2 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8.p0i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1) ; <%struct.__neon_int8x8x2_t> [#uses=2] 164 %tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 0 ; <<8 x i8>> [#uses=1] 165 %tmp4 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 1 ; <<8 x i8>> [#uses=1] 166 %tmp5 = add <8 x i8> %tmp3, %tmp4 ; <<8 x i8>> [#uses=1] 167 ret <8 x i8> %tmp5 168 } 169 170 define void @t7(i32* %iptr, i32* %optr) nounwind { 171 entry: 172 ; CHECK-LABEL: t7: 173 ; CHECK: vld2.32 174 ; CHECK: vst2.32 175 ; CHECK: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, 176 ; CHECK: vorr q[[Q0:[0-9]+]], q[[Q1:[0-9]+]], q[[Q1:[0-9]+]] 177 ; CHECK-NOT: vmov 178 ; CHECK: vuzp.32 q[[Q1]], q[[Q0]] 179 ; CHECK: vst1.32 180 %0 = bitcast i32* %iptr to i8* ; <i8*> [#uses=2] 181 %1 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32.p0i8(i8* %0, i32 1) ; <%struct.__neon_int32x4x2_t> [#uses=2] 182 %tmp57 = extractvalue %struct.__neon_int32x4x2_t %1, 0 ; <<4 x i32>> [#uses=1] 183 %tmp60 = extractvalue %struct.__neon_int32x4x2_t %1, 1 ; <<4 x i32>> [#uses=1] 184 %2 = bitcast i32* %optr to i8* ; <i8*> [#uses=2] 185 tail call void @llvm.arm.neon.vst2.p0i8.v4i32(i8* %2, <4 x i32> %tmp57, <4 x i32> %tmp60, i32 1) 186 %3 = tail call <4 x i32> @llvm.arm.neon.vld1.v4i32.p0i8(i8* %0, i32 1) ; <<4 x i32>> [#uses=1] 187 %4 = shufflevector <4 x i32> %3, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 0, i32 2> ; <<4 x i32>> [#uses=1] 188 tail call void @llvm.arm.neon.vst1.p0i8.v4i32(i8* %2, <4 x i32> %4, i32 1) 189 ret void 190 } 191 192 ; PR7156 193 define arm_aapcs_vfpcc i32 @t8() nounwind { 194 ; CHECK-LABEL: t8: 195 ; CHECK: vrsqrte.f32 q8, q8 196 bb.nph55.bb.nph55.split_crit_edge: 197 br label %bb3 198 199 bb3: ; preds = %bb3, %bb.nph55.bb.nph55.split_crit_edge 200 br i1 undef, label %bb5, label %bb3 201 202 bb5: ; preds = %bb3 203 br label %bb.i25 204 205 bb.i25: ; preds = %bb.i25, %bb5 206 %0 = shufflevector <2 x float> undef, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1] 207 %1 = call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %0) nounwind ; <<4 x float>> [#uses=1] 208 %2 = fmul <4 x float> %1, undef ; <<4 x float>> [#uses=1] 209 %3 = fmul <4 x float> undef, %2 ; <<4 x float>> [#uses=1] 210 %tmp26.i = bitcast <4 x float> %3 to <2 x double> ; <<2 x double>> [#uses=1] 211 %4 = extractelement <2 x double> %tmp26.i, i32 0 ; <double> [#uses=1] 212 %5 = bitcast double %4 to <2 x float> ; <<2 x float>> [#uses=1] 213 %6 = extractelement <2 x float> %5, i32 1 ; <float> [#uses=1] 214 store float %6, float* undef, align 4 215 br i1 undef, label %bb6, label %bb.i25 216 217 bb6: ; preds = %bb.i25 218 br i1 undef, label %bb7, label %bb14 219 220 bb7: ; preds = %bb6 221 br label %bb.i49 222 223 bb.i49: ; preds = %bb.i49, %bb7 224 br i1 undef, label %bb.i19, label %bb.i49 225 226 bb.i19: ; preds = %bb.i19, %bb.i49 227 br i1 undef, label %exit, label %bb.i19 228 229 exit: ; preds = %bb.i19 230 unreachable 231 232 bb14: ; preds = %bb6 233 ret i32 0 234 } 235 236 %0 = type { %1, %1, %1, %1 } 237 %1 = type { %2 } 238 %2 = type { <4 x float> } 239 %3 = type { %0, %1 } 240 241 ; PR7157 242 define arm_aapcs_vfpcc float @t9(%0* nocapture, %3* nocapture) nounwind { 243 ; CHECK-LABEL: t9: 244 ; CHECK: vmov.i32 d16, #0x0 245 ; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128] 246 ; CHECK-NEXT: vorr d17, d16, d16 247 ; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128] 248 %3 = bitcast double 0.000000e+00 to <2 x float> ; <<2 x float>> [#uses=2] 249 %4 = shufflevector <2 x float> %3, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1] 250 store <4 x float> %4, <4 x float>* undef, align 16 251 %5 = shufflevector <2 x float> %3, <2 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1] 252 store <4 x float> %5, <4 x float>* undef, align 16 253 br label %8 254 255 ; <label>:6 ; preds = %8 256 br label %7 257 258 ; <label>:7 ; preds = %6 259 br label %8 260 261 ; <label>:8 ; preds = %7, %2 262 br label %6 263 264 ; <label>:9 ; preds = %8 265 ret float undef 266 267 ; <label>:10 ; preds = %6 268 ret float 9.990000e+02 269 } 270 271 ; PR7162 272 define arm_aapcs_vfpcc i32 @t10() nounwind { 273 entry: 274 ; CHECK-LABEL: t10: 275 ; CHECK: vmov.i32 q[[Q0:[0-9]+]], #0x3f000000 276 ; CHECK: vmul.f32 q8, q8, d[[DREG:[0-1]+]] 277 ; CHECK: vadd.f32 q8, q8, q8 278 %0 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1] 279 %1 = insertelement <4 x float> %0, float undef, i32 1 ; <<4 x float>> [#uses=1] 280 %2 = insertelement <4 x float> %1, float undef, i32 2 ; <<4 x float>> [#uses=1] 281 %3 = insertelement <4 x float> %2, float undef, i32 3 ; <<4 x float>> [#uses=1] 282 %tmp54.i = bitcast <4 x float> %3 to <2 x double> ; <<2 x double>> [#uses=1] 283 %4 = extractelement <2 x double> %tmp54.i, i32 1 ; <double> [#uses=1] 284 %5 = bitcast double %4 to <2 x float> ; <<2 x float>> [#uses=1] 285 %6 = shufflevector <2 x float> %5, <2 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1] 286 %7 = fmul <4 x float> undef, %6 ; <<4 x float>> [#uses=1] 287 %8 = fadd <4 x float> %7, undef ; <<4 x float>> [#uses=1] 288 %9 = fadd <4 x float> %8, undef ; <<4 x float>> [#uses=1] 289 %10 = shufflevector <4 x float> undef, <4 x float> %9, <4 x i32> <i32 0, i32 1, i32 2, i32 7> ; <<4 x float>> [#uses=1] 290 %11 = fmul <4 x float> %10, <float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01> ; <<4 x float>> [#uses=1] 291 %12 = shufflevector <4 x float> %11, <4 x float> undef, <4 x i32> <i32 3, i32 undef, i32 undef, i32 undef> ; <<4 x float>> [#uses=1] 292 %13 = shufflevector <4 x float> %12, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1] 293 %14 = fmul <4 x float> %13, undef ; <<4 x float>> [#uses=1] 294 %15 = fadd <4 x float> undef, %14 ; <<4 x float>> [#uses=1] 295 %16 = shufflevector <4 x float> undef, <4 x float> %15, <4 x i32> <i32 0, i32 1, i32 6, i32 3> ; <<4 x float>> [#uses=1] 296 %17 = fmul <4 x float> %16, undef ; <<4 x float>> [#uses=1] 297 %18 = extractelement <4 x float> %17, i32 2 ; <float> [#uses=1] 298 store float %18, float* undef, align 4 299 br i1 undef, label %exit, label %bb14 300 301 exit: ; preds = %bb.i19 302 unreachable 303 304 bb14: ; preds = %bb6 305 ret i32 0 306 } 307 308 ; This test crashes the coalescer because live variables were not updated properly. 309 define <8 x i8> @t11(i8* %A1, i8* %A2, i8* %A3, i8* %A4, i8* %A5, i8* %A6, i8* %A7, i8* %A8, i8* %B) nounwind { 310 %tmp1d = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A4, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=1] 311 %tmp2d = extractvalue %struct.__neon_int8x8x3_t %tmp1d, 0 ; <<8 x i8>> [#uses=1] 312 %tmp1f = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A6, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=1] 313 %tmp2f = extractvalue %struct.__neon_int8x8x3_t %tmp1f, 0 ; <<8 x i8>> [#uses=1] 314 %tmp2bd = add <8 x i8> zeroinitializer, %tmp2d ; <<8 x i8>> [#uses=1] 315 %tmp2abcd = mul <8 x i8> zeroinitializer, %tmp2bd ; <<8 x i8>> [#uses=1] 316 %tmp2ef = sub <8 x i8> zeroinitializer, %tmp2f ; <<8 x i8>> [#uses=1] 317 %tmp2efgh = mul <8 x i8> %tmp2ef, undef ; <<8 x i8>> [#uses=2] 318 call void @llvm.arm.neon.vst3.p0i8.v8i8(i8* %A2, <8 x i8> undef, <8 x i8> undef, <8 x i8> %tmp2efgh, i32 1) 319 %tmp2 = sub <8 x i8> %tmp2efgh, %tmp2abcd ; <<8 x i8>> [#uses=1] 320 %tmp7 = mul <8 x i8> undef, %tmp2 ; <<8 x i8>> [#uses=1] 321 tail call void @llvm.arm.neon.vst3.p0i8.v8i8(i8* %B, <8 x i8> undef, <8 x i8> undef, <8 x i8> %tmp7, i32 1) 322 ret <8 x i8> undef 323 } 324 325 declare <4 x i32> @llvm.arm.neon.vld1.v4i32.p0i8(i8*, i32) nounwind readonly 326 327 declare <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8*, i32) nounwind readonly 328 329 declare <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone 330 331 declare void @llvm.arm.neon.vst1.p0i8.v4i32(i8*, <4 x i32>, i32) nounwind 332 333 declare void @llvm.arm.neon.vst1.p0i8.v8i16(i8*, <8 x i16>, i32) nounwind 334 335 declare void @llvm.arm.neon.vst3.p0i8.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, i32) 336 nounwind 337 338 declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8*, i32) nounwind readonly 339 340 declare %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32.p0i8(i8*, i32) nounwind readonly 341 342 declare %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8.p0i8(i8*, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly 343 344 declare %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16.p0i8(i8*, <8 x i16>, <8 x i16>, i32, i32) nounwind readonly 345 346 declare void @llvm.arm.neon.vst2.p0i8.v4i32(i8*, <4 x i32>, <4 x i32>, i32) nounwind 347 348 declare <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float>) nounwind readnone 349 350 declare void @llvm.trap() nounwind 351
