1 ; RUN: llc -mtriple=thumbv7-linux-gnueabihf -o - -show-mc-encoding -t2-reduce-limit=0 -t2-reduce-limit2=0 %s | FileCheck %s 2 ; RUN: llc -mtriple=thumbv7-linux-gnueabihf -o - -show-mc-encoding %s | FileCheck %s --check-prefix=CHECK-OPT 3 4 define i32 @and(i32 %a, i32 %b) nounwind readnone { 5 ; CHECK-LABEL: and: 6 ; CHECK: and.w r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}} @ encoding: [{{0x..,0x..,0x..,0x..}}] 7 ; CHECK-OPT: ands r{{[0-7]}}, r{{[0-7]}} @ encoding: [{{0x..,0x..}}] 8 entry: 9 %and = and i32 %b, %a 10 ret i32 %and 11 } 12 13 define i32 @asr-imm(i32 %a) nounwind readnone { 14 ; CHECK-LABEL: "asr-imm": 15 ; CHECK: asr.w r{{[0-9]+}}, r{{[0-9]+}}, #13 @ encoding: [{{0x..,0x..,0x..,0x..}}] 16 ; CHECK-OPT: asrs r{{[0-7]}}, r{{[0-7]}}, #13 @ encoding: [{{0x..,0x..}}] 17 entry: 18 %shr = ashr i32 %a, 13 19 ret i32 %shr 20 } 21 22 define i32 @asr-reg(i32 %a, i32 %b) nounwind readnone { 23 ; CHECK-LABEL: "asr-reg": 24 ; CHECK: asr.w r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}} @ encoding: [{{0x..,0x..,0x..,0x..}}] 25 ; CHECK-OPT: asrs r{{[0-7]}}, r{{[0-7]}} @ encoding: [{{0x..,0x..}}] 26 entry: 27 %shr = ashr i32 %a, %b 28 ret i32 %shr 29 } 30 31 define i32 @bic(i32 %a, i32 %b) nounwind readnone { 32 ; CHECK-LABEL: bic: 33 ; CHECK: bic.w r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}} @ encoding: [{{0x..,0x..,0x..,0x..}}] 34 ; CHECK-OPT: bics r{{[0-7]}}, r{{[0-7]}} @ encoding: [{{0x..,0x..}}] 35 entry: 36 %neg = xor i32 %b, -1 37 %and = and i32 %neg, %a 38 ret i32 %and 39 } 40 41 define i32 @eor(i32 %a, i32 %b) nounwind readnone { 42 ; CHECK-LABEL: eor: 43 ; CHECK: eor.w r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}} @ encoding: [{{0x..,0x..,0x..,0x..}}] 44 ; CHECK-OPT: eors r{{[0-7]}}, r{{[0-7]}} @ encoding: [{{0x..,0x..}}] 45 entry: 46 %eor = xor i32 %a, %b 47 ret i32 %eor 48 } 49 50 define i32 @lsl-imm(i32 %a) nounwind readnone { 51 ; CHECK-LABEL: "lsl-imm": 52 ; CHECK: lsl.w r{{[0-9]+}}, r{{[0-9]+}}, #13 @ encoding: [{{0x..,0x..,0x..,0x..}}] 53 ; CHECK-OPT: lsls r{{[0-7]}}, r{{[0-7]}}, #13 @ encoding: [{{0x..,0x..}}] 54 entry: 55 %shl = shl i32 %a, 13 56 ret i32 %shl 57 } 58 59 define i32 @lsl-reg(i32 %a, i32 %b) nounwind readnone { 60 ; CHECK-LABEL: "lsl-reg": 61 ; CHECK: lsl.w r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}} @ encoding: [{{0x..,0x..,0x..,0x..}}] 62 ; CHECK-OPT: lsls r{{[0-7]}}, r{{[0-7]}} @ encoding: [{{0x..,0x..}}] 63 entry: 64 %shl = shl i32 %a, %b 65 ret i32 %shl 66 } 67 68 define i32 @lsr-imm(i32 %a) nounwind readnone { 69 ; CHECK-LABEL: "lsr-imm": 70 ; CHECK: lsr.w r{{[0-9]+}}, r{{[0-9]+}}, #13 @ encoding: [{{0x..,0x..,0x..,0x..}}] 71 ; CHECK-OPT: lsrs r{{[0-7]}}, r{{[0-7]}}, #13 @ encoding: [{{0x..,0x..}}] 72 entry: 73 %shr = lshr i32 %a, 13 74 ret i32 %shr 75 } 76 77 define i32 @lsr-reg(i32 %a, i32 %b) nounwind readnone { 78 ; CHECK-LABEL: "lsr-reg": 79 ; CHECK: lsr.w r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}} @ encoding: [{{0x..,0x..,0x..,0x..}}] 80 ; CHECK-OPT: lsrs r{{[0-7]}}, r{{[0-7]}} @ encoding: [{{0x..,0x..}}] 81 entry: 82 %shr = lshr i32 %a, %b 83 ret i32 %shr 84 } 85
