1 ; RUN: llc -march=hexagon -hexagon-small-data-threshold=0 < %s | FileCheck %s 2 ; Check that we generate load instructions with absolute addressing mode. 3 ; XFAIL: * 4 5 @a0 = external global i32 6 @a1 = external global i32 7 @b0 = external global i8 8 @b1 = external global i8 9 @c0 = external global i16 10 @c1 = external global i16 11 @d = external global i64 12 13 define zeroext i8 @absStoreByte() nounwind { 14 ; CHECK: memb(##b1){{ *}}={{ *}}r{{[0-9]+}} 15 entry: 16 %0 = load i8, i8* @b0, align 1 17 %conv = zext i8 %0 to i32 18 %mul = mul nsw i32 100, %conv 19 %conv1 = trunc i32 %mul to i8 20 store i8 %conv1, i8* @b1, align 1 21 ret i8 %conv1 22 } 23 24 define signext i16 @absStoreHalf() nounwind { 25 ; CHECK: memh(##c1){{ *}}={{ *}}r{{[0-9]+}} 26 entry: 27 %0 = load i16, i16* @c0, align 2 28 %conv = sext i16 %0 to i32 29 %mul = mul nsw i32 100, %conv 30 %conv1 = trunc i32 %mul to i16 31 store i16 %conv1, i16* @c1, align 2 32 ret i16 %conv1 33 } 34 35 define i32 @absStoreWord() nounwind { 36 ; CHECK: memw(##a1){{ *}}={{ *}}r{{[0-9]+}} 37 entry: 38 %0 = load i32, i32* @a0, align 4 39 %mul = mul nsw i32 100, %0 40 store i32 %mul, i32* @a1, align 4 41 ret i32 %mul 42 } 43 44 define void @absStoreDouble() nounwind { 45 ; CHECK: memd(##d){{ *}}={{ *}}r{{[0-9]+}}:{{[0-9]+}} 46 entry: 47 store i64 100, i64* @d, align 8 48 ret void 49 } 50 51
