1 ; RUN: llc -march=hexagon -O0 < %s | FileCheck %s 2 3 ; CHECK-LABEL: @test00 4 ; CHECK: = cmp.eq(r1:0, r3:2) 5 define i32 @test00(i64 %Rs, i64 %Rt) #0 { 6 entry: 7 %0 = tail call i32 @llvm.hexagon.C2.cmpeqp(i64 %Rs, i64 %Rt) 8 ret i32 %0 9 } 10 11 ; CHECK-LABEL: @test01 12 ; CHECK: = cmp.gt(r1:0, r3:2) 13 define i32 @test01(i64 %Rs, i64 %Rt) #0 { 14 entry: 15 %0 = tail call i32 @llvm.hexagon.C2.cmpgtp(i64 %Rs, i64 %Rt) 16 ret i32 %0 17 } 18 19 ; CHECK-LABEL: @test02 20 ; CHECK: = cmp.gtu(r1:0, r3:2) 21 define i32 @test02(i64 %Rs, i64 %Rt) #0 { 22 entry: 23 %0 = tail call i32 @llvm.hexagon.C2.cmpgtup(i64 %Rs, i64 %Rt) 24 ret i32 %0 25 } 26 27 ; CHECK-LABEL: @test10 28 ; CHECK: = cmp.eq(r0, r1) 29 define i32 @test10(i32 %Rs, i32 %Rt) #0 { 30 entry: 31 %0 = tail call i32 @llvm.hexagon.A4.rcmpeq(i32 %Rs, i32 %Rt) 32 ret i32 %0 33 } 34 35 ; CHECK-LABEL: @test11 36 ; CHECK: = !cmp.eq(r0, r1) 37 define i32 @test11(i32 %Rs, i32 %Rt) #0 { 38 entry: 39 %0 = tail call i32 @llvm.hexagon.A4.rcmpneq(i32 %Rs, i32 %Rt) 40 ret i32 %0 41 } 42 43 ; CHECK-LABEL: @test12 44 ; CHECK: = cmp.eq(r0, #23) 45 define i32 @test12(i32 %Rs) #0 { 46 entry: 47 %0 = tail call i32 @llvm.hexagon.A4.rcmpeqi(i32 %Rs, i32 23) 48 ret i32 %0 49 } 50 51 ; CHECK-LABEL: @test13 52 ; CHECK: = !cmp.eq(r0, #47) 53 define i32 @test13(i32 %Rs) #0 { 54 entry: 55 %0 = tail call i32 @llvm.hexagon.A4.rcmpneqi(i32 %Rs, i32 47) 56 ret i32 %0 57 } 58 59 ; CHECK-LABEL: @test20 60 ; CHECK: = cmpb.eq(r0, r1) 61 define i32 @test20(i32 %Rs, i32 %Rt) #0 { 62 entry: 63 %0 = tail call i32 @llvm.hexagon.A4.cmpbeq(i32 %Rs, i32 %Rt) 64 ret i32 %0 65 } 66 67 ; CHECK-LABEL: @test21 68 ; CHECK: = cmpb.gt(r0, r1) 69 define i32 @test21(i32 %Rs, i32 %Rt) #0 { 70 entry: 71 %0 = tail call i32 @llvm.hexagon.A4.cmpbgt(i32 %Rs, i32 %Rt) 72 ret i32 %0 73 } 74 75 ; CHECK-LABEL: @test22 76 ; CHECK: = cmpb.gtu(r0, r1) 77 define i32 @test22(i32 %Rs, i32 %Rt) #0 { 78 entry: 79 %0 = tail call i32 @llvm.hexagon.A4.cmpbgtu(i32 %Rs, i32 %Rt) 80 ret i32 %0 81 } 82 83 ; CHECK-LABEL: @test23 84 ; CHECK: = cmpb.eq(r0, #56) 85 define i32 @test23(i32 %Rs) #0 { 86 entry: 87 %0 = tail call i32 @llvm.hexagon.A4.cmpbeqi(i32 %Rs, i32 56) 88 ret i32 %0 89 } 90 91 ; CHECK-LABEL: @test24 92 ; CHECK: = cmpb.gt(r0, #29) 93 define i32 @test24(i32 %Rs) #0 { 94 entry: 95 %0 = tail call i32 @llvm.hexagon.A4.cmpbgti(i32 %Rs, i32 29) 96 ret i32 %0 97 } 98 99 ; CHECK-LABEL: @test25 100 ; CHECK: = cmpb.gtu(r0, #111) 101 define i32 @test25(i32 %Rs) #0 { 102 entry: 103 %0 = tail call i32 @llvm.hexagon.A4.cmpbgtui(i32 %Rs, i32 111) 104 ret i32 %0 105 } 106 107 ; CHECK-LABEL: @test30 108 ; CHECK: = cmph.eq(r0, r1) 109 define i32 @test30(i32 %Rs, i32 %Rt) #0 { 110 entry: 111 %0 = tail call i32 @llvm.hexagon.A4.cmpheq(i32 %Rs, i32 %Rt) 112 ret i32 %0 113 } 114 115 ; CHECK-LABEL: @test31 116 ; CHECK: = cmph.gt(r0, r1) 117 define i32 @test31(i32 %Rs, i32 %Rt) #0 { 118 entry: 119 %0 = tail call i32 @llvm.hexagon.A4.cmphgt(i32 %Rs, i32 %Rt) 120 ret i32 %0 121 } 122 123 ; CHECK-LABEL: @test32 124 ; CHECK: = cmph.gtu(r0, r1) 125 define i32 @test32(i32 %Rs, i32 %Rt) #0 { 126 entry: 127 %0 = tail call i32 @llvm.hexagon.A4.cmphgtu(i32 %Rs, i32 %Rt) 128 ret i32 %0 129 } 130 131 ; CHECK-LABEL: @test33 132 ; CHECK: = cmph.eq(r0, #-123) 133 define i32 @test33(i32 %Rs) #0 { 134 entry: 135 %0 = tail call i32 @llvm.hexagon.A4.cmpheqi(i32 %Rs, i32 -123) 136 ret i32 %0 137 } 138 139 ; CHECK-LABEL: @test34 140 ; CHECK: = cmph.gt(r0, #-3) 141 define i32 @test34(i32 %Rs) #0 { 142 entry: 143 %0 = tail call i32 @llvm.hexagon.A4.cmphgti(i32 %Rs, i32 -3) 144 ret i32 %0 145 } 146 147 ; CHECK-LABEL: @test35 148 ; CHECK: = cmph.gtu(r0, #13) 149 define i32 @test35(i32 %Rs) #0 { 150 entry: 151 %0 = tail call i32 @llvm.hexagon.A4.cmphgtui(i32 %Rs, i32 13) 152 ret i32 %0 153 } 154 155 ; CHECK-LABEL: @test40 156 ; CHECK: = vmux(p0, r3:2, r5:4) 157 define i64 @test40(i32 %Pu, i64 %Rs, i64 %Rt) #0 { 158 entry: 159 %0 = tail call i64 @llvm.hexagon.C2.vmux(i32 %Pu, i64 %Rs, i64 %Rt) 160 ret i64 %0 161 } 162 163 ; CHECK-LABEL: @test41 164 ; CHECK: = any8(vcmpb.eq(r1:0, r3:2)) 165 define i32 @test41(i64 %Rs, i64 %Rt) #0 { 166 entry: 167 %0 = tail call i32 @llvm.hexagon.A4.vcmpbeq.any(i64 %Rs, i64 %Rt) 168 ret i32 %0 169 } 170 171 ; CHECK-LABEL: @test50 172 ; CHECK: = add(r1:0, r3:2) 173 define i64 @test50(i64 %Rs, i64 %Rt) #0 { 174 entry: 175 %0 = tail call i64 @llvm.hexagon.A2.addp(i64 %Rs, i64 %Rt) 176 ret i64 %0 177 } 178 179 ; CHECK-LABEL: @test51 180 ; CHECK: = add(r1:0, r3:2):sat 181 define i64 @test51(i64 %Rs, i64 %Rt) #0 { 182 entry: 183 %0 = tail call i64 @llvm.hexagon.A2.addpsat(i64 %Rs, i64 %Rt) 184 ret i64 %0 185 } 186 187 ; CHECK-LABEL: @test52 188 ; CHECK: = sub(r1:0, r3:2) 189 define i64 @test52(i64 %Rs, i64 %Rt) #0 { 190 entry: 191 %0 = tail call i64 @llvm.hexagon.A2.subp(i64 %Rs, i64 %Rt) 192 ret i64 %0 193 } 194 195 ; CHECK-LABEL: @test53 196 ; CHECK: = add(r1:0, r3:2):raw: 197 define i64 @test53(i32 %Rs, i64 %Rt) #0 { 198 entry: 199 %0 = tail call i64 @llvm.hexagon.A2.addsp(i32 %Rs, i64 %Rt) 200 ret i64 %0 201 } 202 203 ; CHECK-LABEL: @test54 204 ; CHECK: = and(r1:0, r3:2) 205 define i64 @test54(i64 %Rs, i64 %Rt) #0 { 206 entry: 207 %0 = tail call i64 @llvm.hexagon.A2.andp(i64 %Rs, i64 %Rt) 208 ret i64 %0 209 } 210 211 ; CHECK-LABEL: @test55 212 ; CHECK: = or(r1:0, r3:2) 213 define i64 @test55(i64 %Rs, i64 %Rt) #0 { 214 entry: 215 %0 = tail call i64 @llvm.hexagon.A2.orp(i64 %Rs, i64 %Rt) 216 ret i64 %0 217 } 218 219 ; CHECK-LABEL: @test56 220 ; CHECK: = xor(r1:0, r3:2) 221 define i64 @test56(i64 %Rs, i64 %Rt) #0 { 222 entry: 223 %0 = tail call i64 @llvm.hexagon.A2.xorp(i64 %Rs, i64 %Rt) 224 ret i64 %0 225 } 226 227 ; CHECK-LABEL: @test57 228 ; CHECK: = and(r1:0, ~r3:2) 229 define i64 @test57(i64 %Rs, i64 %Rt) #0 { 230 entry: 231 %0 = tail call i64 @llvm.hexagon.A4.andnp(i64 %Rs, i64 %Rt) 232 ret i64 %0 233 } 234 235 ; CHECK-LABEL: @test58 236 ; CHECK: = or(r1:0, ~r3:2) 237 define i64 @test58(i64 %Rs, i64 %Rt) #0 { 238 entry: 239 %0 = tail call i64 @llvm.hexagon.A4.ornp(i64 %Rs, i64 %Rt) 240 ret i64 %0 241 } 242 243 ; CHECK-LABEL: @test60 244 ; CHECK: = add(r0.l, r1.l) 245 define i32 @test60(i32 %Rs, i32 %Rt) #0 { 246 entry: 247 %0 = tail call i32 @llvm.hexagon.A2.addh.l16.ll(i32 %Rs, i32 %Rt) 248 ret i32 %0 249 } 250 251 ; CHECK-LABEL: @test61 252 ; CHECK: = add(r0.l, r1.h) 253 define i32 @test61(i32 %Rs, i32 %Rt) #0 { 254 entry: 255 %0 = tail call i32 @llvm.hexagon.A2.addh.l16.hl(i32 %Rs, i32 %Rt) 256 ret i32 %0 257 } 258 259 ; CHECK-LABEL: @test62 260 ; CHECK: = add(r0.l, r1.l):sat 261 define i32 @test62(i32 %Rs, i32 %Rt) #0 { 262 entry: 263 %0 = tail call i32 @llvm.hexagon.A2.addh.l16.sat.ll(i32 %Rs, i32 %Rt) 264 ret i32 %0 265 } 266 267 ; CHECK-LABEL: @test63 268 ; CHECK: = add(r0.l, r1.h):sat 269 define i32 @test63(i32 %Rs, i32 %Rt) #0 { 270 entry: 271 %0 = tail call i32 @llvm.hexagon.A2.addh.l16.sat.hl(i32 %Rs, i32 %Rt) 272 ret i32 %0 273 } 274 275 ; CHECK-LABEL: @test64 276 ; CHECK: = add(r0.l, r1.l):<<16 277 define i32 @test64(i32 %Rs, i32 %Rt) #0 { 278 entry: 279 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.ll(i32 %Rs, i32 %Rt) 280 ret i32 %0 281 } 282 283 ; CHECK-LABEL: @test65 284 ; CHECK: = add(r0.l, r1.h):<<16 285 define i32 @test65(i32 %Rs, i32 %Rt) #0 { 286 entry: 287 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.lh(i32 %Rs, i32 %Rt) 288 ret i32 %0 289 } 290 291 ; CHECK-LABEL: @test66 292 ; CHECK: = add(r0.h, r1.l):<<16 293 define i32 @test66(i32 %Rs, i32 %Rt) #0 { 294 entry: 295 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.hl(i32 %Rs, i32 %Rt) 296 ret i32 %0 297 } 298 299 ; CHECK-LABEL: @test67 300 ; CHECK: = add(r0.h, r1.h):<<16 301 define i32 @test67(i32 %Rs, i32 %Rt) #0 { 302 entry: 303 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.hh(i32 %Rs, i32 %Rt) 304 ret i32 %0 305 } 306 307 ; CHECK-LABEL: @test68 308 ; CHECK: = add(r0.l, r1.l):sat:<<16 309 define i32 @test68(i32 %Rs, i32 %Rt) #0 { 310 entry: 311 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.ll(i32 %Rs, i32 %Rt) 312 ret i32 %0 313 } 314 315 ; CHECK-LABEL: @test69 316 ; CHECK: = add(r0.l, r1.h):sat:<<16 317 define i32 @test69(i32 %Rs, i32 %Rt) #0 { 318 entry: 319 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.lh(i32 %Rs, i32 %Rt) 320 ret i32 %0 321 } 322 323 ; CHECK-LABEL: @test6A 324 ; CHECK: = add(r0.h, r1.l):sat:<<16 325 define i32 @test6A(i32 %Rs, i32 %Rt) #0 { 326 entry: 327 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.hl(i32 %Rs, i32 %Rt) 328 ret i32 %0 329 } 330 331 ; CHECK-LABEL: @test6B 332 ; CHECK: = add(r0.h, r1.h):sat:<<16 333 define i32 @test6B(i32 %Rs, i32 %Rt) #0 { 334 entry: 335 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.hh(i32 %Rs, i32 %Rt) 336 ret i32 %0 337 } 338 339 ; CHECK-LABEL: @test70 340 ; CHECK: = sub(r0.l, r1.l) 341 define i32 @test70(i32 %Rs, i32 %Rt) #0 { 342 entry: 343 %0 = tail call i32 @llvm.hexagon.A2.subh.l16.ll(i32 %Rs, i32 %Rt) 344 ret i32 %0 345 } 346 347 ; CHECK-LABEL: @test71 348 ; CHECK: = sub(r0.l, r1.h) 349 define i32 @test71(i32 %Rs, i32 %Rt) #0 { 350 entry: 351 %0 = tail call i32 @llvm.hexagon.A2.subh.l16.hl(i32 %Rs, i32 %Rt) 352 ret i32 %0 353 } 354 355 ; CHECK-LABEL: @test72 356 ; CHECK: = sub(r0.l, r1.l):sat 357 define i32 @test72(i32 %Rs, i32 %Rt) #0 { 358 entry: 359 %0 = tail call i32 @llvm.hexagon.A2.subh.l16.sat.ll(i32 %Rs, i32 %Rt) 360 ret i32 %0 361 } 362 363 ; CHECK-LABEL: @test73 364 ; CHECK: = sub(r0.l, r1.h):sat 365 define i32 @test73(i32 %Rs, i32 %Rt) #0 { 366 entry: 367 %0 = tail call i32 @llvm.hexagon.A2.subh.l16.sat.hl(i32 %Rs, i32 %Rt) 368 ret i32 %0 369 } 370 371 ; CHECK-LABEL: @test74 372 ; CHECK: = sub(r0.l, r1.l):<<16 373 define i32 @test74(i32 %Rs, i32 %Rt) #0 { 374 entry: 375 %0 = tail call i32 @llvm.hexagon.A2.subh.h16.ll(i32 %Rs, i32 %Rt) 376 ret i32 %0 377 } 378 379 ; CHECK-LABEL: @test75 380 ; CHECK: = sub(r0.l, r1.h):<<16 381 define i32 @test75(i32 %Rs, i32 %Rt) #0 { 382 entry: 383 %0 = tail call i32 @llvm.hexagon.A2.subh.h16.lh(i32 %Rs, i32 %Rt) 384 ret i32 %0 385 } 386 387 ; CHECK-LABEL: @test76 388 ; CHECK: = sub(r0.h, r1.l):<<16 389 define i32 @test76(i32 %Rs, i32 %Rt) #0 { 390 entry: 391 %0 = tail call i32 @llvm.hexagon.A2.subh.h16.hl(i32 %Rs, i32 %Rt) 392 ret i32 %0 393 } 394 395 ; CHECK-LABEL: @test77 396 ; CHECK: = sub(r0.h, r1.h):<<16 397 define i32 @test77(i32 %Rs, i32 %Rt) #0 { 398 entry: 399 %0 = tail call i32 @llvm.hexagon.A2.subh.h16.hh(i32 %Rs, i32 %Rt) 400 ret i32 %0 401 } 402 403 ; CHECK-LABEL: @test78 404 ; CHECK: = sub(r0.l, r1.l):sat:<<16 405 define i32 @test78(i32 %Rs, i32 %Rt) #0 { 406 entry: 407 %0 = tail call i32 @llvm.hexagon.A2.subh.h16.sat.ll(i32 %Rs, i32 %Rt) 408 ret i32 %0 409 } 410 411 ; CHECK-LABEL: @test79 412 ; CHECK: = sub(r0.l, r1.h):sat:<<16 413 define i32 @test79(i32 %Rs, i32 %Rt) #0 { 414 entry: 415 %0 = tail call i32 @llvm.hexagon.A2.subh.h16.sat.lh(i32 %Rs, i32 %Rt) 416 ret i32 %0 417 } 418 419 ; CHECK-LABEL: @test7A 420 ; CHECK: = sub(r0.h, r1.l):sat:<<16 421 define i32 @test7A(i32 %Rs, i32 %Rt) #0 { 422 entry: 423 %0 = tail call i32 @llvm.hexagon.A2.subh.h16.sat.hl(i32 %Rs, i32 %Rt) 424 ret i32 %0 425 } 426 427 ; CHECK-LABEL: @test7B 428 ; CHECK: = sub(r0.h, r1.h):sat:<<16 429 define i32 @test7B(i32 %Rs, i32 %Rt) #0 { 430 entry: 431 %0 = tail call i32 @llvm.hexagon.A2.subh.h16.sat.hh(i32 %Rs, i32 %Rt) 432 ret i32 %0 433 } 434 435 ; CHECK-LABEL: @test90 436 ; CHECK: = and(#1, asl(r0, #2)) 437 define i32 @test90(i32 %Rs) #0 { 438 entry: 439 %0 = tail call i32 @llvm.hexagon.S4.andi.asl.ri(i32 1, i32 %Rs, i32 2) 440 ret i32 %0 441 } 442 443 ; CHECK-LABEL: @test91 444 ; CHECK: = or(#1, asl(r0, #2)) 445 define i32 @test91(i32 %Rs) #0 { 446 entry: 447 %0 = tail call i32 @llvm.hexagon.S4.ori.asl.ri(i32 1, i32 %Rs, i32 2) 448 ret i32 %0 449 } 450 451 ; CHECK-LABEL: @test92 452 ; CHECK: = add(#1, asl(r0, #2)) 453 define i32 @test92(i32 %Rs) #0 { 454 entry: 455 %0 = tail call i32 @llvm.hexagon.S4.addi.asl.ri(i32 1, i32 %Rs, i32 2) 456 ret i32 %0 457 } 458 459 ; CHECK-LABEL: @test93 460 ; CHECK: = sub(#1, asl(r0, #2)) 461 define i32 @test93(i32 %Rs) #0 { 462 entry: 463 %0 = tail call i32 @llvm.hexagon.S4.subi.asl.ri(i32 1, i32 %Rs, i32 2) 464 ret i32 %0 465 } 466 467 ; CHECK-LABEL: @test94 468 ; CHECK: = and(#1, lsr(r0, #2)) 469 define i32 @test94(i32 %Rs) #0 { 470 entry: 471 %0 = tail call i32 @llvm.hexagon.S4.andi.lsr.ri(i32 1, i32 %Rs, i32 2) 472 ret i32 %0 473 } 474 475 ; CHECK-LABEL: @test95 476 ; CHECK: = or(#1, lsr(r0, #2)) 477 define i32 @test95(i32 %Rs) #0 { 478 entry: 479 %0 = tail call i32 @llvm.hexagon.S4.ori.lsr.ri(i32 1, i32 %Rs, i32 2) 480 ret i32 %0 481 } 482 483 ; CHECK-LABEL: @test96 484 ; CHECK: = add(#1, lsr(r0, #2)) 485 define i32 @test96(i32 %Rs) #0 { 486 entry: 487 %0 = tail call i32 @llvm.hexagon.S4.addi.lsr.ri(i32 1, i32 %Rs, i32 2) 488 ret i32 %0 489 } 490 491 ; CHECK-LABEL: @test97 492 ; CHECK: = sub(#1, lsr(r0, #2)) 493 define i32 @test97(i32 %Rs) #0 { 494 entry: 495 %0 = tail call i32 @llvm.hexagon.S4.subi.lsr.ri(i32 1, i32 %Rs, i32 2) 496 ret i32 %0 497 } 498 499 ; CHECK-LABEL: @test100 500 ; CHECK: = bitsplit(r0, r1) 501 define i64 @test100(i32 %Rs, i32 %Rt) #0 { 502 entry: 503 %0 = tail call i64 @llvm.hexagon.A4.bitsplit(i32 %Rs, i32 %Rt) 504 ret i64 %0 505 } 506 507 ; CHECK-LABEL: @test101 508 ; CHECK: = modwrap(r0, r1) 509 define i32 @test101(i32 %Rs, i32 %Rt) #0 { 510 entry: 511 %0 = tail call i32 @llvm.hexagon.A4.modwrapu(i32 %Rs, i32 %Rt) 512 ret i32 %0 513 } 514 515 ; CHECK-LABEL: @test102 516 ; CHECK: = parity(r1:0, r3:2) 517 define i32 @test102(i64 %Rs, i64 %Rt) #0 { 518 entry: 519 %0 = tail call i32 @llvm.hexagon.S2.parityp(i64 %Rs, i64 %Rt) 520 ret i32 %0 521 } 522 523 ; CHECK-LABEL: @test103 524 ; CHECK: = parity(r0, r1) 525 define i32 @test103(i32 %Rs, i32 %Rt) #0 { 526 entry: 527 %0 = tail call i32 @llvm.hexagon.S4.parity(i32 %Rs, i32 %Rt) 528 ret i32 %0 529 } 530 531 declare i32 @llvm.hexagon.C2.cmpeqp(i64, i64) #1 532 declare i32 @llvm.hexagon.C2.cmpgtp(i64, i64) #1 533 declare i32 @llvm.hexagon.C2.cmpgtup(i64, i64) #1 534 declare i32 @llvm.hexagon.A4.rcmpeq(i32, i32) #1 535 declare i32 @llvm.hexagon.A4.rcmpneq(i32, i32) #1 536 declare i32 @llvm.hexagon.A4.rcmpeqi(i32, i32) #1 537 declare i32 @llvm.hexagon.A4.rcmpneqi(i32, i32) #1 538 declare i32 @llvm.hexagon.A4.cmpbeq(i32, i32) #1 539 declare i32 @llvm.hexagon.A4.cmpbgt(i32, i32) #1 540 declare i32 @llvm.hexagon.A4.cmpbgtu(i32, i32) #1 541 declare i32 @llvm.hexagon.A4.cmpbeqi(i32, i32) #1 542 declare i32 @llvm.hexagon.A4.cmpbgti(i32, i32) #1 543 declare i32 @llvm.hexagon.A4.cmpbgtui(i32, i32) #1 544 declare i32 @llvm.hexagon.A4.cmpheq(i32, i32) #1 545 declare i32 @llvm.hexagon.A4.cmphgt(i32, i32) #1 546 declare i32 @llvm.hexagon.A4.cmphgtu(i32, i32) #1 547 declare i32 @llvm.hexagon.A4.cmpheqi(i32, i32) #1 548 declare i32 @llvm.hexagon.A4.cmphgti(i32, i32) #1 549 declare i32 @llvm.hexagon.A4.cmphgtui(i32, i32) #1 550 declare i64 @llvm.hexagon.C2.vmux(i32, i64, i64) #1 551 declare i32 @llvm.hexagon.A4.vcmpbeq.any(i64, i64) #1 552 declare i64 @llvm.hexagon.A2.addp(i64, i64) #1 553 declare i64 @llvm.hexagon.A2.addpsat(i64, i64) #1 554 declare i64 @llvm.hexagon.A2.subp(i64, i64) #1 555 declare i64 @llvm.hexagon.A2.addsp(i32, i64) #1 556 declare i64 @llvm.hexagon.A2.andp(i64, i64) #1 557 declare i64 @llvm.hexagon.A2.orp(i64, i64) #1 558 declare i64 @llvm.hexagon.A2.xorp(i64, i64) #1 559 declare i64 @llvm.hexagon.A4.ornp(i64, i64) #1 560 declare i64 @llvm.hexagon.A4.andnp(i64, i64) #1 561 declare i32 @llvm.hexagon.A2.addh.l16.ll(i32, i32) #1 562 declare i32 @llvm.hexagon.A2.addh.l16.hl(i32, i32) #1 563 declare i32 @llvm.hexagon.A2.addh.l16.sat.ll(i32, i32) #1 564 declare i32 @llvm.hexagon.A2.addh.l16.sat.hl(i32, i32) #1 565 declare i32 @llvm.hexagon.A2.addh.h16.ll(i32, i32) #1 566 declare i32 @llvm.hexagon.A2.addh.h16.lh(i32, i32) #1 567 declare i32 @llvm.hexagon.A2.addh.h16.hl(i32, i32) #1 568 declare i32 @llvm.hexagon.A2.addh.h16.hh(i32, i32) #1 569 declare i32 @llvm.hexagon.A2.addh.h16.sat.ll(i32, i32) #1 570 declare i32 @llvm.hexagon.A2.addh.h16.sat.lh(i32, i32) #1 571 declare i32 @llvm.hexagon.A2.addh.h16.sat.hl(i32, i32) #1 572 declare i32 @llvm.hexagon.A2.addh.h16.sat.hh(i32, i32) #1 573 declare i32 @llvm.hexagon.A2.subh.l16.ll(i32, i32) #1 574 declare i32 @llvm.hexagon.A2.subh.l16.hl(i32, i32) #1 575 declare i32 @llvm.hexagon.A2.subh.l16.sat.ll(i32, i32) #1 576 declare i32 @llvm.hexagon.A2.subh.l16.sat.hl(i32, i32) #1 577 declare i32 @llvm.hexagon.A2.subh.h16.ll(i32, i32) #1 578 declare i32 @llvm.hexagon.A2.subh.h16.lh(i32, i32) #1 579 declare i32 @llvm.hexagon.A2.subh.h16.hl(i32, i32) #1 580 declare i32 @llvm.hexagon.A2.subh.h16.hh(i32, i32) #1 581 declare i32 @llvm.hexagon.A2.subh.h16.sat.ll(i32, i32) #1 582 declare i32 @llvm.hexagon.A2.subh.h16.sat.lh(i32, i32) #1 583 declare i32 @llvm.hexagon.A2.subh.h16.sat.hl(i32, i32) #1 584 declare i32 @llvm.hexagon.A2.subh.h16.sat.hh(i32, i32) #1 585 declare i64 @llvm.hexagon.A4.bitsplit(i32, i32) #1 586 declare i32 @llvm.hexagon.A4.modwrapu(i32, i32) #1 587 declare i32 @llvm.hexagon.S2.parityp(i64, i64) #1 588 declare i32 @llvm.hexagon.S4.parity(i32, i32) #1 589 declare i32 @llvm.hexagon.S4.andi.asl.ri(i32, i32, i32) #1 590 declare i32 @llvm.hexagon.S4.ori.asl.ri(i32, i32, i32) #1 591 declare i32 @llvm.hexagon.S4.addi.asl.ri(i32, i32, i32) #1 592 declare i32 @llvm.hexagon.S4.subi.asl.ri(i32, i32, i32) #1 593 declare i32 @llvm.hexagon.S4.andi.lsr.ri(i32, i32, i32) #1 594 declare i32 @llvm.hexagon.S4.ori.lsr.ri(i32, i32, i32) #1 595 declare i32 @llvm.hexagon.S4.addi.lsr.ri(i32, i32, i32) #1 596 declare i32 @llvm.hexagon.S4.subi.lsr.ri(i32, i32, i32) #1 597 598 attributes #0 = { nounwind readnone "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } 599 attributes #1 = { nounwind readnone } 600
