1 ; RUN: llc -march=hexagon < %s | FileCheck %s 2 ; RUN: llc -march=hexagon -verify-machineinstrs=true < %s | FileCheck %s 3 ; Testing bitreverse load intrinsics: 4 ; Q6_bitrev_load_update_D(inputLR, pDelay, nConvLength); 5 ; Q6_bitrev_load_update_W(inputLR, pDelay, nConvLength); 6 ; Q6_bitrev_load_update_H(inputLR, pDelay, nConvLength); 7 ; Q6_bitrev_load_update_UH(inputLR, pDelay, nConvLength); 8 ; Q6_bitrev_load_update_UB(inputLR, pDelay, nConvLength); 9 ; Q6_bitrev_load_update_B(inputLR, pDelay, nConvLength); 10 ; producing these instructions: 11 ; r3:2 = memd(r0++m0:brev) 12 ; r1 = memw(r0++m0:brev) 13 ; r1 = memh(r0++m0:brev) 14 ; r1 = memuh(r0++m0:brev) 15 ; r1 = memub(r0++m0:brev) 16 ; r1 = memb(r0++m0:brev) 17 18 target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" 19 target triple = "hexagon" 20 21 define i64 @foo(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { 22 entry: 23 %inputLR = alloca i64, align 8 24 %conv = zext i16 %filtMemLen to i32 25 %shr1 = lshr i32 %conv, 1 26 %idxprom = sext i16 %filtMemIndex to i32 27 %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom 28 %0 = bitcast i16* %arrayidx to i8* 29 %1 = bitcast i64* %inputLR to i8* 30 %sub = sub i32 13, %shr1 31 %shl = shl i32 1, %sub 32 ; CHECK: memd(r{{[0-9]*}} ++ m{{[0-1]}}:brev) 33 %2 = call i8* @llvm.hexagon.brev.ldd(i8* %0, i8* %1, i32 %shl) 34 %3 = bitcast i8* %2 to i64* 35 %4 = load i64, i64* %3, align 8, !tbaa !0 36 ret i64 %4 37 } 38 39 declare i8* @llvm.hexagon.brev.ldd(i8*, i8*, i32) nounwind 40 41 define i32 @foo1(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { 42 entry: 43 %inputLR = alloca i32, align 4 44 %conv = zext i16 %filtMemLen to i32 45 %shr1 = lshr i32 %conv, 1 46 %idxprom = sext i16 %filtMemIndex to i32 47 %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom 48 %0 = bitcast i16* %arrayidx to i8* 49 %1 = bitcast i32* %inputLR to i8* 50 %sub = sub i32 14, %shr1 51 %shl = shl i32 1, %sub 52 ; CHECK: memw(r{{[0-9]*}} ++ m{{[0-1]}}:brev) 53 %2 = call i8* @llvm.hexagon.brev.ldw(i8* %0, i8* %1, i32 %shl) 54 %3 = bitcast i8* %2 to i32* 55 %4 = load i32, i32* %3, align 4, !tbaa !2 56 ret i32 %4 57 } 58 59 declare i8* @llvm.hexagon.brev.ldw(i8*, i8*, i32) nounwind 60 61 define signext i16 @foo2(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { 62 entry: 63 %inputLR = alloca i16, align 2 64 %conv = zext i16 %filtMemLen to i32 65 %shr1 = lshr i32 %conv, 1 66 %idxprom = sext i16 %filtMemIndex to i32 67 %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom 68 %0 = bitcast i16* %arrayidx to i8* 69 %1 = bitcast i16* %inputLR to i8* 70 %sub = sub i32 15, %shr1 71 %shl = shl i32 1, %sub 72 ; CHECK: memh(r{{[0-9]*}} ++ m0:brev) 73 %2 = call i8* @llvm.hexagon.brev.ldh(i8* %0, i8* %1, i32 %shl) 74 %3 = bitcast i8* %2 to i16* 75 %4 = load i16, i16* %3, align 2, !tbaa !3 76 ret i16 %4 77 } 78 79 declare i8* @llvm.hexagon.brev.ldh(i8*, i8*, i32) nounwind 80 81 define zeroext i16 @foo3(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { 82 entry: 83 %inputLR = alloca i16, align 2 84 %conv = zext i16 %filtMemLen to i32 85 %shr1 = lshr i32 %conv, 1 86 %idxprom = sext i16 %filtMemIndex to i32 87 %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom 88 %0 = bitcast i16* %arrayidx to i8* 89 %1 = bitcast i16* %inputLR to i8* 90 %sub = sub i32 15, %shr1 91 %shl = shl i32 1, %sub 92 ; CHECK: memuh(r{{[0-9]*}} ++ m0:brev) 93 %2 = call i8* @llvm.hexagon.brev.lduh(i8* %0, i8* %1, i32 %shl) 94 %3 = bitcast i8* %2 to i16* 95 %4 = load i16, i16* %3, align 2, !tbaa !3 96 ret i16 %4 97 } 98 99 declare i8* @llvm.hexagon.brev.lduh(i8*, i8*, i32) nounwind 100 101 define zeroext i8 @foo4(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { 102 entry: 103 %inputLR = alloca i8, align 1 104 %conv = zext i16 %filtMemLen to i32 105 %shr1 = lshr i32 %conv, 1 106 %idxprom = sext i16 %filtMemIndex to i32 107 %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom 108 %0 = bitcast i16* %arrayidx to i8* 109 %sub = sub nsw i32 16, %shr1 110 %shl = shl i32 1, %sub 111 ; CHECK: memub(r{{[0-9]*}} ++ m{{[0-1]}}:brev) 112 %1 = call i8* @llvm.hexagon.brev.ldub(i8* %0, i8* %inputLR, i32 %shl) 113 %2 = load i8, i8* %1, align 1, !tbaa !0 114 ret i8 %2 115 } 116 117 declare i8* @llvm.hexagon.brev.ldub(i8*, i8*, i32) nounwind 118 119 define zeroext i8 @foo5(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { 120 entry: 121 %inputLR = alloca i8, align 1 122 %conv = zext i16 %filtMemLen to i32 123 %shr1 = lshr i32 %conv, 1 124 %idxprom = sext i16 %filtMemIndex to i32 125 %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom 126 %0 = bitcast i16* %arrayidx to i8* 127 %sub = sub nsw i32 16, %shr1 128 %shl = shl i32 1, %sub 129 ; CHECK: memb(r{{[0-9]*}} ++ m{{[0-1]}}:brev) 130 %1 = call i8* @llvm.hexagon.brev.ldb(i8* %0, i8* %inputLR, i32 %shl) 131 %2 = load i8, i8* %1, align 1, !tbaa !0 132 ret i8 %2 133 } 134 135 declare i8* @llvm.hexagon.brev.ldb(i8*, i8*, i32) nounwind 136 137 !0 = !{!"omnipotent char", !1} 138 !1 = !{!"Simple C/C++ TBAA"} 139 !2 = !{!"int", !0} 140 !3 = !{!"short", !0} 141
