1 ; RUN: llc -march=hexagon < %s | FileCheck %s 2 ; RUN: llc -march=hexagon -verify-machineinstrs=true < %s | FileCheck %s 3 ; Test these 5 bitreverse store intrinsics: 4 ; Q6_bitrev_store_update_D(inputLR, pDelay, nConvLength); 5 ; Q6_bitrev_store_update_W(inputLR, pDelay, nConvLength); 6 ; Q6_bitrev_store_update_HL(inputLR, pDelay, nConvLength); 7 ; Q6_bitrev_store_update_HH(inputLR, pDelay, nConvLength); 8 ; Q6_bitrev_store_update_B(inputLR, pDelay, nConvLength); 9 ; producing these instructions: 10 ; memd(r0++m0:brev) = r1:0 11 ; memw(r0++m0:brev) = r0 12 ; memh(r0++m0:brev) = r3 13 ; memh(r0++m0:brev) = r3.h 14 ; memb(r0++m0:brev) = r3 15 16 ; ModuleID = 'brev_st.i' 17 target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" 18 target triple = "hexagon" 19 20 define i64 @foo(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { 21 entry: 22 %conv = zext i16 %filtMemLen to i32 23 %shr2 = lshr i32 %conv, 1 24 %idxprom = sext i16 %filtMemIndex to i32 25 %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom 26 %0 = bitcast i16* %arrayidx to i8* 27 %sub = sub i32 13, %shr2 28 %shl = shl i32 1, %sub 29 ; CHECK: memd(r{{[0-9]*}} ++ m{{[0-1]}}:brev) 30 %1 = tail call i8* @llvm.hexagon.brev.std(i8* %0, i64 undef, i32 %shl) 31 %2 = bitcast i8* %1 to i64* 32 %3 = load i64, i64* %2, align 8, !tbaa !0 33 ret i64 %3 34 } 35 36 declare i8* @llvm.hexagon.brev.std(i8*, i64, i32) nounwind 37 38 define i32 @foo1(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { 39 entry: 40 %conv = zext i16 %filtMemLen to i32 41 %shr1 = lshr i32 %conv, 1 42 %idxprom = sext i16 %filtMemIndex to i32 43 %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom 44 %0 = bitcast i16* %arrayidx to i8* 45 %sub = sub i32 14, %shr1 46 %shl = shl i32 1, %sub 47 ; CHECK: memw(r{{[0-9]*}} ++ m{{[0-1]}}:brev) 48 %1 = tail call i8* @llvm.hexagon.brev.stw(i8* %0, i32 undef, i32 %shl) 49 %2 = bitcast i8* %1 to i32* 50 %3 = load i32, i32* %2, align 4, !tbaa !2 51 ret i32 %3 52 } 53 54 declare i8* @llvm.hexagon.brev.stw(i8*, i32, i32) nounwind 55 56 define signext i16 @foo2(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { 57 entry: 58 %conv = zext i16 %filtMemLen to i32 59 %shr2 = lshr i32 %conv, 1 60 %idxprom = sext i16 %filtMemIndex to i32 61 %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom 62 %0 = bitcast i16* %arrayidx to i8* 63 %sub = sub i32 15, %shr2 64 %shl = shl i32 1, %sub 65 ; CHECK: memh(r{{[0-9]*}} ++ m{{[0-1]}}:brev) 66 %1 = tail call i8* @llvm.hexagon.brev.sth(i8* %0, i32 0, i32 %shl) 67 %2 = bitcast i8* %1 to i16* 68 %3 = load i16, i16* %2, align 2, !tbaa !3 69 ret i16 %3 70 } 71 72 declare i8* @llvm.hexagon.brev.sth(i8*, i32, i32) nounwind 73 74 define signext i16 @foo3(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { 75 entry: 76 %conv = zext i16 %filtMemLen to i32 77 %shr2 = lshr i32 %conv, 1 78 %idxprom = sext i16 %filtMemIndex to i32 79 %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom 80 %0 = bitcast i16* %arrayidx to i8* 81 %sub = sub i32 15, %shr2 82 %shl = shl i32 1, %sub 83 ; CHECK: memh(r{{[0-9]*}} ++ m{{[0-1]}}:brev){{ *}}={{ *}}r{{[0-9]*}}.h 84 %1 = tail call i8* @llvm.hexagon.brev.sthhi(i8* %0, i32 0, i32 %shl) 85 %2 = bitcast i8* %1 to i16* 86 %3 = load i16, i16* %2, align 2, !tbaa !3 87 ret i16 %3 88 } 89 90 declare i8* @llvm.hexagon.brev.sthhi(i8*, i32, i32) nounwind 91 92 define zeroext i8 @foo5(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { 93 entry: 94 %conv = zext i16 %filtMemLen to i32 95 %shr2 = lshr i32 %conv, 1 96 %idxprom = sext i16 %filtMemIndex to i32 97 %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom 98 %0 = bitcast i16* %arrayidx to i8* 99 %sub = sub nsw i32 16, %shr2 100 ; CHECK: memb(r{{[0-9]*}} ++ m{{[0-1]}}:brev) 101 %shl = shl i32 1, %sub 102 %1 = tail call i8* @llvm.hexagon.brev.stb(i8* %0, i32 0, i32 %shl) 103 %2 = load i8, i8* %1, align 1, !tbaa !0 104 ret i8 %2 105 } 106 107 declare i8* @llvm.hexagon.brev.stb(i8*, i32, i32) nounwind 108 109 !0 = !{!"omnipotent char", !1} 110 !1 = !{!"Simple C/C++ TBAA"} 111 !2 = !{!"int", !0} 112 !3 = !{!"short", !0} 113
