1 ; RUN: llc -march=hexagon -verify-machineinstrs=true < %s | FileCheck %s 2 ; Testing for these 5 variants of circular store: 3 ; Q6_circ_store_update_B(inputLR, pDelay, -1, nConvLength, 4); 4 ; Q6_circ_store_update_D(inputLR, pDelay, -1, nConvLength, 4); 5 ; Q6_circ_store_update_HL(inputLR, pDelay, -1, nConvLength, 4); 6 ; Q6_circ_store_update_HH(inputLR, pDelay, -1, nConvLength, 4); 7 ; Q6_circ_store_update_W(inputLR, pDelay, -1, nConvLength, 4); 8 ; producing these 9 ; memb(r1++#-1:circ(m0)) = r3 10 ; memd(r1++#-8:circ(m0)) = r1:0 11 ; memh(r1++#-2:circ(m0)) = r3 12 ; memh(r1++#-2:circ(m0)) = r3.h 13 ; memw(r1++#-4:circ(m0)) = r0 14 15 ; ModuleID = 'circ_st.i' 16 target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" 17 target triple = "hexagon" 18 19 define zeroext i8 @foo1(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { 20 entry: 21 %conv = zext i16 %filtMemLen to i32 22 %shr2 = lshr i32 %conv, 1 23 %idxprom = sext i16 %filtMemIndex to i32 24 %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom 25 %0 = bitcast i16* %arrayidx to i8* 26 %or = or i32 %shr2, 33554432 27 ; CHECK: memb(r{{[0-9]*}}{{.}}++{{.}}#-1:circ(m{{[0-1]}})) 28 %1 = tail call i8* @llvm.hexagon.circ.stb(i8* %0, i32 0, i32 %or, i32 -1) 29 %2 = load i8, i8* %1, align 1, !tbaa !0 30 ret i8 %2 31 } 32 33 declare i8* @llvm.hexagon.circ.stb(i8*, i32, i32, i32) nounwind 34 35 define i64 @foo2(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { 36 entry: 37 %conv = zext i16 %filtMemLen to i32 38 %shr1 = lshr i32 %conv, 1 39 %idxprom = sext i16 %filtMemIndex to i32 40 %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom 41 %0 = bitcast i16* %arrayidx to i8* 42 %shl = shl nuw nsw i32 %shr1, 3 43 %or = or i32 %shl, 83886080 44 ; CHECK: memd(r{{[0-9]*}}{{.}}++{{.}}#-8:circ(m{{[0-1]}})) 45 %1 = tail call i8* @llvm.hexagon.circ.std(i8* %0, i64 undef, i32 %or, i32 -8) 46 %2 = bitcast i8* %1 to i64* 47 %3 = load i64, i64* %2, align 8, !tbaa !0 48 ret i64 %3 49 } 50 51 declare i8* @llvm.hexagon.circ.std(i8*, i64, i32, i32) nounwind 52 53 define signext i16 @foo3(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { 54 entry: 55 %conv = zext i16 %filtMemLen to i32 56 %shr2 = and i32 %conv, 65534 57 %idxprom = sext i16 %filtMemIndex to i32 58 %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom 59 %0 = bitcast i16* %arrayidx to i8* 60 %or = or i32 %shr2, 50331648 61 ; CHECK: memh(r{{[0-9]*}}{{.}}++{{.}}#-2:circ(m{{[0-1]}})) 62 %1 = tail call i8* @llvm.hexagon.circ.sth(i8* %0, i32 0, i32 %or, i32 -2) 63 %2 = bitcast i8* %1 to i16* 64 %3 = load i16, i16* %2, align 2, !tbaa !2 65 ret i16 %3 66 } 67 68 declare i8* @llvm.hexagon.circ.sth(i8*, i32, i32, i32) nounwind 69 70 define signext i16 @foo5(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { 71 entry: 72 %conv = zext i16 %filtMemLen to i32 73 %shr2 = and i32 %conv, 65534 74 %idxprom = sext i16 %filtMemIndex to i32 75 %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom 76 %0 = bitcast i16* %arrayidx to i8* 77 %or = or i32 %shr2, 50331648 78 ; CHECK: memh(r{{[0-9]*}}{{.}}++{{.}}#-2:circ(m{{[0-1]}})){{ *}}={{ *}}r{{[0-9]*}}.h 79 %1 = tail call i8* @llvm.hexagon.circ.sthhi(i8* %0, i32 0, i32 %or, i32 -2) 80 %2 = bitcast i8* %1 to i16* 81 %3 = load i16, i16* %2, align 2, !tbaa !2 82 ret i16 %3 83 } 84 85 declare i8* @llvm.hexagon.circ.sthhi(i8*, i32, i32, i32) nounwind 86 87 define i32 @foo6(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { 88 entry: 89 %conv = zext i16 %filtMemLen to i32 90 %shr1 = lshr i32 %conv, 1 91 %idxprom = sext i16 %filtMemIndex to i32 92 %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom 93 %0 = bitcast i16* %arrayidx to i8* 94 %shl = shl nuw nsw i32 %shr1, 2 95 %or = or i32 %shl, 67108864 96 ; CHECK: memw(r{{[0-9]*}}{{.}}++{{.}}#-4:circ(m{{[0-1]}})) 97 %1 = tail call i8* @llvm.hexagon.circ.stw(i8* %0, i32 undef, i32 %or, i32 -4) 98 %2 = bitcast i8* %1 to i32* 99 %3 = load i32, i32* %2, align 4, !tbaa !3 100 ret i32 %3 101 } 102 103 declare i8* @llvm.hexagon.circ.stw(i8*, i32, i32, i32) nounwind 104 105 !0 = !{!"omnipotent char", !1} 106 !1 = !{!"Simple C/C++ TBAA"} 107 !2 = !{!"short", !0} 108 !3 = !{!"int", !0} 109
