1 # RUN: llc -mtriple=powerpc64-unknown-linux-gnu -start-after machine-combiner -stop-after machine-combiner -o /dev/null %s | FileCheck %s 2 # PR24724 3 4 --- | 5 define signext i32 @main(i32* %p) #0 { 6 entry: 7 %0 = load i32, i32* %p, align 4 8 %or = or i32 0, %0 9 store i32 %or, i32* %p, align 4 10 %lnot.1 = icmp eq i32 undef, 0 11 %lnot.ext.1 = zext i1 %lnot.1 to i32 12 %shr.i.1 = lshr i32 2072, %lnot.ext.1 13 %call.lobit.1 = lshr i32 %shr.i.1, 7 14 %1 = and i32 %call.lobit.1, 1 15 %or.1 = or i32 %1, %or 16 ret i32 %or.1 17 } 18 19 attributes #0 = { nounwind "target-cpu"="ppc64" } 20 ... 21 --- 22 name: main 23 isSSA: true 24 tracksRegLiveness: true 25 registers: 26 - { id: 0, class: g8rc_and_g8rc_nox0 } 27 - { id: 1, class: gprc } 28 - { id: 2, class: gprc } 29 - { id: 3, class: gprc } 30 - { id: 4, class: g8rc } 31 liveins: 32 - { reg: '%x3', virtual-reg: '%0' } 33 body: | 34 bb.0.entry: 35 liveins: %x3 36 37 %0 = COPY %x3 38 %1 = LWZ 0, %0 :: (load 4 from %ir.p) 39 %2 = LI 0 40 %3 = RLWIMI %2, killed %1, 0, 0, 31 41 %4 = EXTSW_32_64 killed %3 42 %x3 = COPY %4 43 ; CHECK: BLR8 implicit %lr8, implicit %rm, implicit %x3 44 BLR8 implicit %lr8, implicit %rm, implicit %x3 45 ... 46
